Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46766727	1			T1	179		T2	35861		T3	43383
triple_byte_access	2696148	1			T1	1		T2	723		T3	38968
halfword_access	4043791	1			T1	7		T2	1055		T3	58200
byte_access	5402913	1			T1	7		T2	1444		T3	77718
zero_access	1361673	1			T1	2		T2	394		T3	19442

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30079952

1

T1

109

T2

19802

T3

118807

auto[1]

30191300

1

T1

87

T2

19675

T3

118904

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	23334837	1			T1	98		T2	18011		T3	21807
auto[0]	triple_byte_access	1344533	1			T1	1		T2	355		T3	19551
auto[0]	halfword_access	2016936	1			T1	5		T2	527		T3	29044
auto[0]	byte_access	2699119	1			T1	4		T2	726		T3	38732
auto[0]	zero_access	684527	1			T1	1		T2	183		T3	9673
auto[1]	word_access	23431890	1			T1	81		T2	17850		T3	21576
auto[1]	triple_byte_access	1351615	1			T2	368		T3	19417		T10	2353
auto[1]	halfword_access	2026855	1			T1	2		T2	528		T3	29156
auto[1]	byte_access	2703794	1			T1	3		T2	718		T3	38986
auto[1]	zero_access	677146	1			T1	1		T2	211		T3	9769