Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.08 99.81 96.99 100.00 100.00 98.57 99.70 98.52


Total test records in report: 1026
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T797 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2484040793 May 16 01:19:05 PM PDT 24 May 16 01:19:09 PM PDT 24 101319656 ps
T798 /workspace/coverage/default/14.sram_ctrl_lc_escalation.1180827266 May 16 01:17:41 PM PDT 24 May 16 01:17:55 PM PDT 24 3783984517 ps
T799 /workspace/coverage/default/48.sram_ctrl_stress_all.3594484901 May 16 01:20:29 PM PDT 24 May 16 01:52:11 PM PDT 24 223833509450 ps
T800 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3598760511 May 16 01:17:37 PM PDT 24 May 16 01:18:49 PM PDT 24 490396592 ps
T801 /workspace/coverage/default/46.sram_ctrl_ram_cfg.391982177 May 16 01:20:15 PM PDT 24 May 16 01:20:18 PM PDT 24 81013259 ps
T802 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.3729024360 May 16 01:19:28 PM PDT 24 May 16 01:19:39 PM PDT 24 605015150 ps
T803 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2327121698 May 16 01:17:50 PM PDT 24 May 16 01:17:54 PM PDT 24 65531208 ps
T804 /workspace/coverage/default/30.sram_ctrl_executable.3445053353 May 16 01:18:49 PM PDT 24 May 16 01:38:26 PM PDT 24 64484419156 ps
T805 /workspace/coverage/default/12.sram_ctrl_smoke.2076294030 May 16 01:17:38 PM PDT 24 May 16 01:17:49 PM PDT 24 2699752824 ps
T806 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1331076855 May 16 01:20:20 PM PDT 24 May 16 01:23:51 PM PDT 24 8157185830 ps
T807 /workspace/coverage/default/18.sram_ctrl_smoke.2268314087 May 16 01:18:01 PM PDT 24 May 16 01:18:12 PM PDT 24 353914345 ps
T808 /workspace/coverage/default/2.sram_ctrl_smoke.3258783897 May 16 01:16:45 PM PDT 24 May 16 01:16:52 PM PDT 24 254967029 ps
T809 /workspace/coverage/default/49.sram_ctrl_alert_test.3323074197 May 16 01:20:31 PM PDT 24 May 16 01:20:35 PM PDT 24 20061167 ps
T810 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.4294452282 May 16 01:19:06 PM PDT 24 May 16 01:22:22 PM PDT 24 7100480792 ps
T811 /workspace/coverage/default/10.sram_ctrl_smoke.2203467020 May 16 01:17:34 PM PDT 24 May 16 01:17:42 PM PDT 24 143584597 ps
T812 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2471077749 May 16 01:20:12 PM PDT 24 May 16 01:20:20 PM PDT 24 354082665 ps
T813 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.441365826 May 16 01:19:53 PM PDT 24 May 16 01:29:23 PM PDT 24 85227990889 ps
T814 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2601416314 May 16 01:17:39 PM PDT 24 May 16 01:19:38 PM PDT 24 5177087882 ps
T815 /workspace/coverage/default/22.sram_ctrl_max_throughput.2921459061 May 16 01:18:12 PM PDT 24 May 16 01:19:25 PM PDT 24 213073561 ps
T816 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2892593667 May 16 01:18:39 PM PDT 24 May 16 01:18:58 PM PDT 24 316745208 ps
T817 /workspace/coverage/default/31.sram_ctrl_regwen.3996971814 May 16 01:19:06 PM PDT 24 May 16 01:29:28 PM PDT 24 28271154238 ps
T818 /workspace/coverage/default/8.sram_ctrl_executable.2097096244 May 16 01:17:24 PM PDT 24 May 16 01:26:46 PM PDT 24 30810439511 ps
T819 /workspace/coverage/default/44.sram_ctrl_max_throughput.1666776044 May 16 01:20:05 PM PDT 24 May 16 01:20:09 PM PDT 24 122641932 ps
T820 /workspace/coverage/default/41.sram_ctrl_ram_cfg.3829789005 May 16 01:19:51 PM PDT 24 May 16 01:19:54 PM PDT 24 32079971 ps
T821 /workspace/coverage/default/18.sram_ctrl_stress_all.1100211758 May 16 01:18:02 PM PDT 24 May 16 02:39:18 PM PDT 24 348584031044 ps
T822 /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4237430665 May 16 01:17:18 PM PDT 24 May 16 01:45:31 PM PDT 24 20653667710 ps
T823 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.790551082 May 16 01:19:52 PM PDT 24 May 16 01:25:33 PM PDT 24 4179423582 ps
T824 /workspace/coverage/default/1.sram_ctrl_ram_cfg.1791866020 May 16 01:16:44 PM PDT 24 May 16 01:16:47 PM PDT 24 61333329 ps
T825 /workspace/coverage/default/10.sram_ctrl_max_throughput.1634658125 May 16 01:17:28 PM PDT 24 May 16 01:18:27 PM PDT 24 423583161 ps
T826 /workspace/coverage/default/43.sram_ctrl_executable.418644790 May 16 01:20:02 PM PDT 24 May 16 01:32:47 PM PDT 24 36259874503 ps
T827 /workspace/coverage/default/26.sram_ctrl_partial_access.751279866 May 16 01:18:35 PM PDT 24 May 16 01:18:37 PM PDT 24 117644232 ps
T828 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2785483038 May 16 01:17:11 PM PDT 24 May 16 01:22:37 PM PDT 24 7308582207 ps
T829 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2240815350 May 16 01:17:20 PM PDT 24 May 16 01:22:55 PM PDT 24 3343663999 ps
T830 /workspace/coverage/default/27.sram_ctrl_smoke.2775118941 May 16 01:18:35 PM PDT 24 May 16 01:19:02 PM PDT 24 348158676 ps
T831 /workspace/coverage/default/45.sram_ctrl_stress_all.413669298 May 16 01:20:11 PM PDT 24 May 16 02:09:09 PM PDT 24 48359828975 ps
T832 /workspace/coverage/default/2.sram_ctrl_executable.2079364833 May 16 01:16:44 PM PDT 24 May 16 01:39:44 PM PDT 24 9373978258 ps
T833 /workspace/coverage/default/38.sram_ctrl_regwen.243359957 May 16 01:19:32 PM PDT 24 May 16 01:28:57 PM PDT 24 39439128824 ps
T834 /workspace/coverage/default/23.sram_ctrl_max_throughput.2852512599 May 16 01:18:18 PM PDT 24 May 16 01:20:29 PM PDT 24 150411696 ps
T835 /workspace/coverage/default/18.sram_ctrl_executable.2174034369 May 16 01:18:02 PM PDT 24 May 16 01:35:42 PM PDT 24 70185505363 ps
T836 /workspace/coverage/default/11.sram_ctrl_executable.3811665048 May 16 01:17:38 PM PDT 24 May 16 01:31:40 PM PDT 24 58969473476 ps
T837 /workspace/coverage/default/22.sram_ctrl_alert_test.2123951748 May 16 01:18:24 PM PDT 24 May 16 01:18:28 PM PDT 24 73871200 ps
T838 /workspace/coverage/default/7.sram_ctrl_regwen.4137362786 May 16 01:17:17 PM PDT 24 May 16 01:34:16 PM PDT 24 51630304583 ps
T839 /workspace/coverage/default/15.sram_ctrl_regwen.3642042753 May 16 01:17:46 PM PDT 24 May 16 01:33:35 PM PDT 24 6411224663 ps
T840 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2895460532 May 16 01:18:13 PM PDT 24 May 16 01:19:18 PM PDT 24 879100660 ps
T841 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2245024165 May 16 01:19:26 PM PDT 24 May 16 01:30:45 PM PDT 24 2973168021 ps
T842 /workspace/coverage/default/37.sram_ctrl_mem_walk.269129472 May 16 01:19:28 PM PDT 24 May 16 01:19:43 PM PDT 24 865690937 ps
T843 /workspace/coverage/default/20.sram_ctrl_partial_access.2381212946 May 16 01:18:17 PM PDT 24 May 16 01:18:35 PM PDT 24 277088950 ps
T844 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1841669450 May 16 01:17:45 PM PDT 24 May 16 01:19:08 PM PDT 24 1319483458 ps
T845 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3244739243 May 16 01:17:38 PM PDT 24 May 16 01:18:57 PM PDT 24 3761731651 ps
T846 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1508397020 May 16 01:19:34 PM PDT 24 May 16 01:28:47 PM PDT 24 2106403319 ps
T847 /workspace/coverage/default/30.sram_ctrl_mem_walk.2218674080 May 16 01:19:05 PM PDT 24 May 16 01:19:14 PM PDT 24 898259909 ps
T848 /workspace/coverage/default/17.sram_ctrl_alert_test.2898738286 May 16 01:17:59 PM PDT 24 May 16 01:18:03 PM PDT 24 17062368 ps
T849 /workspace/coverage/default/35.sram_ctrl_smoke.3704407581 May 16 01:19:25 PM PDT 24 May 16 01:21:12 PM PDT 24 575314979 ps
T850 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.12175104 May 16 01:18:36 PM PDT 24 May 16 01:22:55 PM PDT 24 11348619340 ps
T851 /workspace/coverage/default/41.sram_ctrl_alert_test.1054321476 May 16 01:19:45 PM PDT 24 May 16 01:19:48 PM PDT 24 58104168 ps
T852 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3223858668 May 16 01:17:38 PM PDT 24 May 16 01:18:08 PM PDT 24 380664411 ps
T853 /workspace/coverage/default/28.sram_ctrl_smoke.2630756083 May 16 01:18:35 PM PDT 24 May 16 01:18:44 PM PDT 24 323423974 ps
T854 /workspace/coverage/default/19.sram_ctrl_smoke.3139421128 May 16 01:18:01 PM PDT 24 May 16 01:18:10 PM PDT 24 278352447 ps
T855 /workspace/coverage/default/42.sram_ctrl_alert_test.3245881254 May 16 01:19:51 PM PDT 24 May 16 01:19:55 PM PDT 24 31062923 ps
T856 /workspace/coverage/default/4.sram_ctrl_lc_escalation.2998207466 May 16 01:17:00 PM PDT 24 May 16 01:17:09 PM PDT 24 484489262 ps
T857 /workspace/coverage/default/35.sram_ctrl_lc_escalation.4210386309 May 16 01:19:21 PM PDT 24 May 16 01:19:25 PM PDT 24 57677222 ps
T858 /workspace/coverage/default/0.sram_ctrl_bijection.2975901290 May 16 01:16:43 PM PDT 24 May 16 01:17:53 PM PDT 24 5030136232 ps
T859 /workspace/coverage/default/34.sram_ctrl_partial_access.2078215783 May 16 01:19:23 PM PDT 24 May 16 01:19:28 PM PDT 24 123726808 ps
T860 /workspace/coverage/default/26.sram_ctrl_smoke.2161253810 May 16 01:18:38 PM PDT 24 May 16 01:20:14 PM PDT 24 2162409629 ps
T861 /workspace/coverage/default/9.sram_ctrl_alert_test.959646231 May 16 01:17:29 PM PDT 24 May 16 01:17:33 PM PDT 24 12515500 ps
T862 /workspace/coverage/default/45.sram_ctrl_partial_access.1644131079 May 16 01:20:12 PM PDT 24 May 16 01:21:01 PM PDT 24 1835346351 ps
T863 /workspace/coverage/default/5.sram_ctrl_partial_access.2444382006 May 16 01:17:08 PM PDT 24 May 16 01:17:29 PM PDT 24 8938745303 ps
T864 /workspace/coverage/default/39.sram_ctrl_alert_test.3282311988 May 16 01:19:36 PM PDT 24 May 16 01:19:42 PM PDT 24 15861857 ps
T865 /workspace/coverage/default/29.sram_ctrl_max_throughput.1286442219 May 16 01:18:49 PM PDT 24 May 16 01:19:42 PM PDT 24 110968344 ps
T866 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4158579590 May 16 01:18:37 PM PDT 24 May 16 01:28:49 PM PDT 24 10079043280 ps
T867 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1159709844 May 16 01:18:26 PM PDT 24 May 16 01:24:54 PM PDT 24 5899640040 ps
T868 /workspace/coverage/default/16.sram_ctrl_bijection.1873881980 May 16 01:17:48 PM PDT 24 May 16 01:18:57 PM PDT 24 7012485455 ps
T869 /workspace/coverage/default/1.sram_ctrl_mem_walk.3742595693 May 16 01:16:45 PM PDT 24 May 16 01:16:53 PM PDT 24 303843853 ps
T870 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1885871326 May 16 01:17:11 PM PDT 24 May 16 01:22:09 PM PDT 24 4021559856 ps
T871 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2823477299 May 16 01:18:47 PM PDT 24 May 16 01:24:27 PM PDT 24 4644253959 ps
T872 /workspace/coverage/default/42.sram_ctrl_ram_cfg.507036004 May 16 01:19:51 PM PDT 24 May 16 01:19:56 PM PDT 24 109123857 ps
T873 /workspace/coverage/default/26.sram_ctrl_max_throughput.883324706 May 16 01:18:38 PM PDT 24 May 16 01:20:42 PM PDT 24 475601755 ps
T874 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1998867823 May 16 01:20:13 PM PDT 24 May 16 01:28:20 PM PDT 24 1478704268 ps
T875 /workspace/coverage/default/14.sram_ctrl_alert_test.1628468043 May 16 01:17:47 PM PDT 24 May 16 01:17:51 PM PDT 24 36846433 ps
T876 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3377145414 May 16 01:19:53 PM PDT 24 May 16 01:22:44 PM PDT 24 3720939088 ps
T877 /workspace/coverage/default/33.sram_ctrl_bijection.1291295831 May 16 01:19:20 PM PDT 24 May 16 01:20:12 PM PDT 24 6363411764 ps
T878 /workspace/coverage/default/2.sram_ctrl_regwen.1115404964 May 16 01:16:49 PM PDT 24 May 16 01:35:27 PM PDT 24 35557943083 ps
T879 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2133722733 May 16 01:17:18 PM PDT 24 May 16 01:22:44 PM PDT 24 25765776025 ps
T880 /workspace/coverage/default/46.sram_ctrl_executable.1173106568 May 16 01:20:13 PM PDT 24 May 16 01:37:58 PM PDT 24 12992269162 ps
T881 /workspace/coverage/default/22.sram_ctrl_ram_cfg.2168353488 May 16 01:18:15 PM PDT 24 May 16 01:18:21 PM PDT 24 32675342 ps
T882 /workspace/coverage/default/1.sram_ctrl_regwen.2363779706 May 16 01:16:53 PM PDT 24 May 16 01:29:43 PM PDT 24 16652073041 ps
T883 /workspace/coverage/default/40.sram_ctrl_bijection.622446443 May 16 01:19:35 PM PDT 24 May 16 01:19:56 PM PDT 24 744285007 ps
T884 /workspace/coverage/default/37.sram_ctrl_lc_escalation.131318409 May 16 01:19:32 PM PDT 24 May 16 01:19:44 PM PDT 24 1550301770 ps
T885 /workspace/coverage/default/46.sram_ctrl_multiple_keys.578528201 May 16 01:20:11 PM PDT 24 May 16 01:28:25 PM PDT 24 6693699247 ps
T886 /workspace/coverage/default/23.sram_ctrl_regwen.104966516 May 16 01:18:11 PM PDT 24 May 16 01:18:49 PM PDT 24 6151138101 ps
T887 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2645642479 May 16 01:19:28 PM PDT 24 May 16 01:24:40 PM PDT 24 8965027773 ps
T888 /workspace/coverage/default/39.sram_ctrl_multiple_keys.664219640 May 16 01:19:35 PM PDT 24 May 16 01:20:08 PM PDT 24 2058065491 ps
T889 /workspace/coverage/default/6.sram_ctrl_smoke.1227507771 May 16 01:17:10 PM PDT 24 May 16 01:17:22 PM PDT 24 383501660 ps
T890 /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.3240367362 May 16 01:18:50 PM PDT 24 May 16 01:25:27 PM PDT 24 2351825677 ps
T891 /workspace/coverage/default/38.sram_ctrl_max_throughput.1684935534 May 16 01:19:30 PM PDT 24 May 16 01:22:06 PM PDT 24 134841127 ps
T892 /workspace/coverage/default/40.sram_ctrl_multiple_keys.3290089917 May 16 01:19:35 PM PDT 24 May 16 01:23:42 PM PDT 24 5752040498 ps
T893 /workspace/coverage/default/26.sram_ctrl_lc_escalation.349531112 May 16 01:18:40 PM PDT 24 May 16 01:18:54 PM PDT 24 994981290 ps
T894 /workspace/coverage/default/40.sram_ctrl_mem_walk.4166358977 May 16 01:19:43 PM PDT 24 May 16 01:19:50 PM PDT 24 1003997321 ps
T895 /workspace/coverage/default/30.sram_ctrl_smoke.392265602 May 16 01:18:50 PM PDT 24 May 16 01:19:06 PM PDT 24 720666257 ps
T896 /workspace/coverage/default/30.sram_ctrl_max_throughput.1515632517 May 16 01:18:50 PM PDT 24 May 16 01:19:06 PM PDT 24 67390549 ps
T897 /workspace/coverage/default/22.sram_ctrl_mem_walk.335731716 May 16 01:18:16 PM PDT 24 May 16 01:18:30 PM PDT 24 4345926237 ps
T898 /workspace/coverage/default/16.sram_ctrl_regwen.2204548067 May 16 01:17:49 PM PDT 24 May 16 01:23:55 PM PDT 24 9239133225 ps
T899 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2388432134 May 16 01:16:47 PM PDT 24 May 16 01:16:52 PM PDT 24 25369896 ps
T900 /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3296573836 May 16 01:19:04 PM PDT 24 May 16 01:19:53 PM PDT 24 10683588302 ps
T901 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3907409908 May 16 01:20:10 PM PDT 24 May 16 01:20:20 PM PDT 24 2263683486 ps
T902 /workspace/coverage/default/45.sram_ctrl_mem_partial_access.230315155 May 16 01:20:12 PM PDT 24 May 16 01:20:19 PM PDT 24 123633471 ps
T903 /workspace/coverage/default/7.sram_ctrl_stress_all.1136102480 May 16 01:17:23 PM PDT 24 May 16 01:26:44 PM PDT 24 54717624765 ps
T904 /workspace/coverage/default/10.sram_ctrl_ram_cfg.2966024805 May 16 01:17:28 PM PDT 24 May 16 01:17:32 PM PDT 24 51570949 ps
T905 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.2650388450 May 16 01:18:38 PM PDT 24 May 16 01:40:07 PM PDT 24 15657333715 ps
T906 /workspace/coverage/default/47.sram_ctrl_partial_access.2356103215 May 16 01:20:22 PM PDT 24 May 16 01:21:01 PM PDT 24 272423384 ps
T907 /workspace/coverage/default/9.sram_ctrl_stress_all.1194955905 May 16 01:17:27 PM PDT 24 May 16 01:37:42 PM PDT 24 5363762957 ps
T908 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3938360698 May 16 01:17:51 PM PDT 24 May 16 01:20:18 PM PDT 24 1640218920 ps
T909 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3123023961 May 16 01:16:59 PM PDT 24 May 16 01:22:43 PM PDT 24 14898176302 ps
T910 /workspace/coverage/default/0.sram_ctrl_partial_access.2740237592 May 16 01:16:42 PM PDT 24 May 16 01:16:54 PM PDT 24 956795030 ps
T911 /workspace/coverage/default/47.sram_ctrl_smoke.212446986 May 16 01:20:24 PM PDT 24 May 16 01:20:31 PM PDT 24 167207349 ps
T912 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.882456402 May 16 01:17:17 PM PDT 24 May 16 01:17:23 PM PDT 24 168503486 ps
T913 /workspace/coverage/default/7.sram_ctrl_partial_access.365100977 May 16 01:17:16 PM PDT 24 May 16 01:18:14 PM PDT 24 162285095 ps
T914 /workspace/coverage/default/39.sram_ctrl_bijection.837712519 May 16 01:19:38 PM PDT 24 May 16 01:20:07 PM PDT 24 5517327803 ps
T915 /workspace/coverage/default/33.sram_ctrl_partial_access.2171345732 May 16 01:19:22 PM PDT 24 May 16 01:19:41 PM PDT 24 641647968 ps
T916 /workspace/coverage/default/25.sram_ctrl_bijection.588697762 May 16 01:18:30 PM PDT 24 May 16 01:19:03 PM PDT 24 2114458961 ps
T917 /workspace/coverage/default/36.sram_ctrl_bijection.1185443778 May 16 01:19:32 PM PDT 24 May 16 01:20:44 PM PDT 24 3284091192 ps
T918 /workspace/coverage/default/4.sram_ctrl_executable.937494504 May 16 01:17:00 PM PDT 24 May 16 01:34:57 PM PDT 24 16722985475 ps
T919 /workspace/coverage/default/11.sram_ctrl_smoke.4211205670 May 16 01:17:28 PM PDT 24 May 16 01:17:47 PM PDT 24 235692110 ps
T920 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.884611620 May 16 01:18:23 PM PDT 24 May 16 01:18:48 PM PDT 24 84337688 ps
T921 /workspace/coverage/default/31.sram_ctrl_executable.195798931 May 16 01:19:07 PM PDT 24 May 16 01:27:25 PM PDT 24 8294421374 ps
T922 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.612913958 May 16 01:19:28 PM PDT 24 May 16 01:20:47 PM PDT 24 530535062 ps
T923 /workspace/coverage/default/46.sram_ctrl_bijection.1999475567 May 16 01:20:12 PM PDT 24 May 16 01:20:32 PM PDT 24 1116374330 ps
T924 /workspace/coverage/default/48.sram_ctrl_partial_access.3799800441 May 16 01:20:20 PM PDT 24 May 16 01:20:41 PM PDT 24 512356157 ps
T925 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3802533930 May 16 01:19:25 PM PDT 24 May 16 01:36:38 PM PDT 24 16911529143 ps
T926 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2351320146 May 16 01:18:19 PM PDT 24 May 16 01:25:47 PM PDT 24 35597606118 ps
T927 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2020812931 May 16 01:16:49 PM PDT 24 May 16 01:23:09 PM PDT 24 7956589007 ps
T928 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2140822486 May 16 01:17:01 PM PDT 24 May 16 01:20:33 PM PDT 24 46683702219 ps
T929 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.365215097 May 16 01:17:47 PM PDT 24 May 16 01:22:11 PM PDT 24 3559543777 ps
T930 /workspace/coverage/default/26.sram_ctrl_stress_all.3965370269 May 16 01:18:39 PM PDT 24 May 16 02:46:19 PM PDT 24 50243546405 ps
T931 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3602974405 May 16 01:20:29 PM PDT 24 May 16 01:20:38 PM PDT 24 4069016003 ps
T932 /workspace/coverage/default/15.sram_ctrl_executable.170453521 May 16 01:17:49 PM PDT 24 May 16 01:27:22 PM PDT 24 8757182873 ps
T933 /workspace/coverage/default/34.sram_ctrl_max_throughput.15385025 May 16 01:19:20 PM PDT 24 May 16 01:19:28 PM PDT 24 110120323 ps
T934 /workspace/coverage/default/48.sram_ctrl_ram_cfg.3020764886 May 16 01:20:24 PM PDT 24 May 16 01:20:28 PM PDT 24 33956235 ps
T935 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2443462364 May 16 01:18:24 PM PDT 24 May 16 01:22:19 PM PDT 24 2321112903 ps
T936 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.356584423 May 16 01:17:12 PM PDT 24 May 16 01:17:21 PM PDT 24 64984749 ps
T937 /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.635128762 May 16 01:17:28 PM PDT 24 May 16 01:20:31 PM PDT 24 158048818 ps
T938 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.324967702 May 16 01:18:17 PM PDT 24 May 16 01:23:43 PM PDT 24 3285785925 ps
T939 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2133355707 May 16 01:18:12 PM PDT 24 May 16 01:18:20 PM PDT 24 1000742967 ps
T68 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1415410275 May 16 12:59:57 PM PDT 24 May 16 01:00:42 PM PDT 24 741916105 ps
T116 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2344223907 May 16 12:59:56 PM PDT 24 May 16 01:00:39 PM PDT 24 156320242 ps
T117 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1878994083 May 16 12:59:53 PM PDT 24 May 16 01:00:35 PM PDT 24 321358599 ps
T113 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1279503559 May 16 12:59:45 PM PDT 24 May 16 01:00:24 PM PDT 24 40827224 ps
T101 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1156366326 May 16 12:59:56 PM PDT 24 May 16 01:00:38 PM PDT 24 19097031 ps
T118 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2553528205 May 16 12:59:47 PM PDT 24 May 16 01:00:28 PM PDT 24 1000654786 ps
T940 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3055364628 May 16 12:59:48 PM PDT 24 May 16 01:00:27 PM PDT 24 72872136 ps
T69 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.827116912 May 16 12:59:56 PM PDT 24 May 16 01:00:41 PM PDT 24 823875363 ps
T941 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2105874625 May 16 12:59:51 PM PDT 24 May 16 01:00:32 PM PDT 24 69896172 ps
T942 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.166000410 May 16 12:59:54 PM PDT 24 May 16 01:00:38 PM PDT 24 158510355 ps
T133 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3057573001 May 16 01:00:00 PM PDT 24 May 16 01:00:42 PM PDT 24 136974647 ps
T114 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.995317492 May 16 12:59:48 PM PDT 24 May 16 01:00:28 PM PDT 24 121320222 ps
T70 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2298167850 May 16 12:59:51 PM PDT 24 May 16 01:00:32 PM PDT 24 849478521 ps
T943 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2318444454 May 16 12:59:47 PM PDT 24 May 16 01:00:29 PM PDT 24 39945334 ps
T71 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3659570725 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 21743263 ps
T115 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1379433085 May 16 12:59:50 PM PDT 24 May 16 01:00:30 PM PDT 24 45790849 ps
T72 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3828639801 May 16 12:59:44 PM PDT 24 May 16 01:00:22 PM PDT 24 21672010 ps
T102 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.224978434 May 16 12:59:51 PM PDT 24 May 16 01:00:31 PM PDT 24 21682055 ps
T73 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1321629866 May 16 12:59:45 PM PDT 24 May 16 01:00:24 PM PDT 24 58171400 ps
T74 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1664935098 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 15126026 ps
T134 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3932898275 May 16 12:59:46 PM PDT 24 May 16 01:00:27 PM PDT 24 216034190 ps
T75 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1769188283 May 16 12:59:47 PM PDT 24 May 16 01:00:26 PM PDT 24 14248661 ps
T944 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1257515813 May 16 01:00:02 PM PDT 24 May 16 01:00:47 PM PDT 24 111527299 ps
T76 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.997988368 May 16 12:59:59 PM PDT 24 May 16 01:00:40 PM PDT 24 13385530 ps
T945 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3746772907 May 16 12:59:48 PM PDT 24 May 16 01:00:28 PM PDT 24 45260751 ps
T77 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2503218217 May 16 12:59:44 PM PDT 24 May 16 01:00:23 PM PDT 24 24694751 ps
T946 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4000251300 May 16 12:59:55 PM PDT 24 May 16 01:00:39 PM PDT 24 413162162 ps
T103 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3006061459 May 16 01:00:01 PM PDT 24 May 16 01:00:44 PM PDT 24 384072593 ps
T947 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2545381167 May 16 12:59:44 PM PDT 24 May 16 01:00:22 PM PDT 24 41624489 ps
T104 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3939188909 May 16 12:59:51 PM PDT 24 May 16 01:00:31 PM PDT 24 21510459 ps
T80 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1922620332 May 16 12:59:48 PM PDT 24 May 16 01:00:26 PM PDT 24 19118042 ps
T948 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1388123799 May 16 12:59:48 PM PDT 24 May 16 01:00:28 PM PDT 24 147606916 ps
T949 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.791183413 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 78107557 ps
T950 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.715557099 May 16 12:59:54 PM PDT 24 May 16 01:00:38 PM PDT 24 76866255 ps
T951 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2989425559 May 16 12:59:45 PM PDT 24 May 16 01:00:25 PM PDT 24 102421056 ps
T952 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1593462527 May 16 12:59:46 PM PDT 24 May 16 01:00:26 PM PDT 24 206074179 ps
T81 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.211603918 May 16 12:59:50 PM PDT 24 May 16 01:00:31 PM PDT 24 912406343 ps
T953 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1517025254 May 16 12:59:57 PM PDT 24 May 16 01:00:41 PM PDT 24 1540766324 ps
T954 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1502886711 May 16 12:59:47 PM PDT 24 May 16 01:00:27 PM PDT 24 270451409 ps
T82 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2925864970 May 16 12:59:47 PM PDT 24 May 16 01:00:27 PM PDT 24 813539417 ps
T955 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1266072252 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 26359840 ps
T956 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.905351587 May 16 12:59:53 PM PDT 24 May 16 01:00:36 PM PDT 24 40011416 ps
T957 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2943522373 May 16 12:59:52 PM PDT 24 May 16 01:00:33 PM PDT 24 55180970 ps
T83 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1129606643 May 16 12:59:54 PM PDT 24 May 16 01:00:37 PM PDT 24 59211032 ps
T958 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.915408889 May 16 12:59:56 PM PDT 24 May 16 01:00:38 PM PDT 24 57337162 ps
T142 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.117340795 May 16 12:59:48 PM PDT 24 May 16 01:00:28 PM PDT 24 391729112 ps
T959 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2101225517 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 27874245 ps
T84 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3898247212 May 16 01:00:03 PM PDT 24 May 16 01:00:45 PM PDT 24 30449874 ps
T93 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3175492340 May 16 12:59:58 PM PDT 24 May 16 01:00:39 PM PDT 24 14713135 ps
T138 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2460528140 May 16 12:59:54 PM PDT 24 May 16 01:00:38 PM PDT 24 807696254 ps
T960 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3154663303 May 16 12:59:51 PM PDT 24 May 16 01:00:35 PM PDT 24 174223941 ps
T961 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1177019168 May 16 12:59:53 PM PDT 24 May 16 01:00:35 PM PDT 24 77170847 ps
T962 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2837045953 May 16 12:59:53 PM PDT 24 May 16 01:00:34 PM PDT 24 80621181 ps
T140 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3321222199 May 16 12:59:56 PM PDT 24 May 16 01:00:41 PM PDT 24 375888871 ps
T132 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2381437216 May 16 12:59:56 PM PDT 24 May 16 01:00:40 PM PDT 24 762421942 ps
T963 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1886299747 May 16 12:59:53 PM PDT 24 May 16 01:00:35 PM PDT 24 19917727 ps
T94 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2580122802 May 16 12:59:56 PM PDT 24 May 16 01:00:41 PM PDT 24 5199997322 ps
T964 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3198280675 May 16 12:59:56 PM PDT 24 May 16 01:00:38 PM PDT 24 24322322 ps
T965 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2798723494 May 16 12:59:57 PM PDT 24 May 16 01:00:40 PM PDT 24 110172262 ps
T99 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1079521134 May 16 12:59:51 PM PDT 24 May 16 01:00:31 PM PDT 24 38461893 ps
T136 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2724125943 May 16 12:59:52 PM PDT 24 May 16 01:00:34 PM PDT 24 304963736 ps
T966 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.955332789 May 16 12:59:55 PM PDT 24 May 16 01:00:40 PM PDT 24 334693040 ps
T967 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1044923165 May 16 12:59:53 PM PDT 24 May 16 01:00:34 PM PDT 24 16325019 ps
T968 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3428931782 May 16 12:59:57 PM PDT 24 May 16 01:00:39 PM PDT 24 99499601 ps
T137 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2521112229 May 16 12:59:55 PM PDT 24 May 16 01:00:39 PM PDT 24 216159937 ps
T969 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1897009063 May 16 12:59:47 PM PDT 24 May 16 01:00:28 PM PDT 24 261576264 ps
T970 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.272653356 May 16 12:59:53 PM PDT 24 May 16 01:00:37 PM PDT 24 386075454 ps
T971 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3872195714 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 27586894 ps
T972 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1951227935 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 14773632 ps
T973 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2179815650 May 16 12:59:51 PM PDT 24 May 16 01:00:33 PM PDT 24 29683564 ps
T100 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.211185714 May 16 12:59:56 PM PDT 24 May 16 01:00:39 PM PDT 24 877700929 ps
T974 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4197043977 May 16 12:59:54 PM PDT 24 May 16 01:00:37 PM PDT 24 70538236 ps
T975 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.508682360 May 16 12:59:59 PM PDT 24 May 16 01:00:40 PM PDT 24 22150057 ps
T976 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.23838910 May 16 12:59:49 PM PDT 24 May 16 01:00:29 PM PDT 24 18610351 ps
T143 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4077318287 May 16 12:59:46 PM PDT 24 May 16 01:00:27 PM PDT 24 596661030 ps
T95 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.701733444 May 16 01:00:03 PM PDT 24 May 16 01:00:48 PM PDT 24 765195499 ps
T977 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1223735225 May 16 01:00:05 PM PDT 24 May 16 01:00:50 PM PDT 24 383033054 ps
T978 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3946540025 May 16 12:59:52 PM PDT 24 May 16 01:00:33 PM PDT 24 285318519 ps
T979 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4074080641 May 16 12:59:53 PM PDT 24 May 16 01:00:34 PM PDT 24 22174497 ps
T96 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2681638800 May 16 12:59:55 PM PDT 24 May 16 01:00:39 PM PDT 24 403993782 ps
T980 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2042504385 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 13250502 ps
T981 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1187224980 May 16 01:00:04 PM PDT 24 May 16 01:00:47 PM PDT 24 103612633 ps
T92 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2419120896 May 16 12:59:46 PM PDT 24 May 16 01:00:26 PM PDT 24 21262102 ps
T982 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3366322196 May 16 12:59:59 PM PDT 24 May 16 01:00:40 PM PDT 24 257154674 ps
T983 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3248429539 May 16 12:59:46 PM PDT 24 May 16 01:00:26 PM PDT 24 14293015 ps
T984 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1705963419 May 16 01:00:03 PM PDT 24 May 16 01:00:45 PM PDT 24 18025733 ps
T985 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3057563177 May 16 12:59:50 PM PDT 24 May 16 01:00:29 PM PDT 24 21639974 ps
T986 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3526637345 May 16 12:59:46 PM PDT 24 May 16 01:00:26 PM PDT 24 94941968 ps
T987 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.861160816 May 16 12:59:56 PM PDT 24 May 16 01:00:40 PM PDT 24 76881944 ps
T988 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3112209906 May 16 12:59:54 PM PDT 24 May 16 01:00:38 PM PDT 24 411023459 ps
T135 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.285535509 May 16 12:59:45 PM PDT 24 May 16 01:00:26 PM PDT 24 497763971 ps
T989 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.548019348 May 16 01:00:02 PM PDT 24 May 16 01:00:46 PM PDT 24 67880077 ps
T990 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2367262762 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 36611040 ps
T991 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.309631263 May 16 12:59:47 PM PDT 24 May 16 01:00:27 PM PDT 24 84165282 ps
T992 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3958889789 May 16 12:59:56 PM PDT 24 May 16 01:00:41 PM PDT 24 213966986 ps
T993 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2313597387 May 16 12:59:47 PM PDT 24 May 16 01:00:26 PM PDT 24 18781326 ps
T994 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2682294001 May 16 12:59:51 PM PDT 24 May 16 01:00:33 PM PDT 24 168344763 ps
T995 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2291750475 May 16 12:59:55 PM PDT 24 May 16 01:00:40 PM PDT 24 263748973 ps
T996 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3930936312 May 16 12:59:53 PM PDT 24 May 16 01:00:36 PM PDT 24 41527888 ps
T997 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3106953819 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 104165960 ps
T97 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1982512057 May 16 12:59:59 PM PDT 24 May 16 01:00:43 PM PDT 24 1714085936 ps
T998 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.992070622 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 42598038 ps
T98 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1527374578 May 16 12:59:45 PM PDT 24 May 16 01:00:26 PM PDT 24 1556484908 ps
T139 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1245063277 May 16 12:59:51 PM PDT 24 May 16 01:00:33 PM PDT 24 922302238 ps
T999 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1850195812 May 16 12:59:46 PM PDT 24 May 16 01:00:25 PM PDT 24 11456508 ps
T1000 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3363187260 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 21603820 ps
T1001 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3599564911 May 16 12:59:55 PM PDT 24 May 16 01:00:37 PM PDT 24 30190662 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%