Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14237427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59523185

1

T1

861

T2

360062

T3

103815

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36774701	1			T1	452		T2	198156		T3	57088
values[0x0]	17070116	1			T1	226		T2	95473		T3	27532
values[0x1]	19915795	1			T1	183		T2	102424		T3	29481

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7094279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66666333

1

T1

861

T2

378223

T3

108958

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	243192	1			T1	5		T2	1569		T3	447
valid_sources[0x01]	291757	1			T1	3		T2	1564		T3	445
valid_sources[0x02]	258818	1			T1	3		T2	1596		T3	458
valid_sources[0x03]	294549	1			T1	3		T2	1483		T3	532
valid_sources[0x04]	257597	1			T1	6		T2	1572		T3	425
valid_sources[0x05]	320106	1			T1	4		T2	1444		T3	344
valid_sources[0x06]	310532	1			T1	4		T2	1526		T3	429
valid_sources[0x07]	247949	1			T1	5		T2	1523		T3	460
valid_sources[0x08]	272071	1			T1	1		T2	1475		T3	472
valid_sources[0x09]	243719	1			T1	2		T2	1534		T3	458
valid_sources[0x0a]	288490	1			T1	2		T2	1549		T3	448
valid_sources[0x0b]	281869	1			T1	7		T2	1522		T3	481
valid_sources[0x0c]	337440	1			T1	5		T2	1579		T3	391
valid_sources[0x0d]	251115	1			T1	4		T2	1541		T3	431
valid_sources[0x0e]	273986	1			T2	1511		T3	393		T5	632
valid_sources[0x0f]	245821	1			T1	9		T2	1588		T3	483
valid_sources[0x10]	250461	1			T1	3		T2	1469		T3	398
valid_sources[0x11]	256794	1			T1	5		T2	1552		T3	415
valid_sources[0x12]	279848	1			T1	7		T2	1452		T3	438
valid_sources[0x13]	268319	1			T1	6		T2	1591		T3	413
valid_sources[0x14]	263584	1			T1	3		T2	1518		T3	521
valid_sources[0x15]	277444	1			T1	2		T2	1585		T3	478
valid_sources[0x16]	240482	1			T1	2		T2	1539		T3	462
valid_sources[0x17]	268988	1			T1	3		T2	1655		T3	437
valid_sources[0x18]	268188	1			T1	7		T2	1501		T3	391
valid_sources[0x19]	329751	1			T1	6		T2	1537		T3	401
valid_sources[0x1a]	266312	1			T1	3		T2	1507		T3	393
valid_sources[0x1b]	310679	1			T1	6		T2	1608		T3	477
valid_sources[0x1c]	274739	1			T1	4		T2	1605		T3	478
valid_sources[0x1d]	295254	1			T1	7		T2	1578		T3	389
valid_sources[0x1e]	339377	1			T1	7		T2	1563		T3	436
valid_sources[0x1f]	284882	1			T1	6		T2	1565		T3	485
valid_sources[0x20]	253845	1			T1	1		T2	1483		T3	377
valid_sources[0x21]	287046	1			T1	2		T2	1539		T3	436
valid_sources[0x22]	324870	1			T1	4		T2	1643		T3	442
valid_sources[0x23]	340831	1			T1	2		T2	1496		T3	406
valid_sources[0x24]	394734	1			T1	4		T2	1527		T3	467
valid_sources[0x25]	293542	1			T1	4		T2	1526		T3	426
valid_sources[0x26]	301650	1			T1	3		T2	1597		T3	414
valid_sources[0x27]	275148	1			T1	5		T2	1562		T3	454
valid_sources[0x28]	261651	1			T1	3		T2	1489		T3	443
valid_sources[0x29]	289428	1			T1	1		T2	1544		T3	484
valid_sources[0x2a]	235115	1			T1	6		T2	1542		T3	365
valid_sources[0x2b]	284609	1			T1	2		T2	1536		T3	432
valid_sources[0x2c]	269805	1			T1	2		T2	1587		T3	462
valid_sources[0x2d]	268180	1			T1	1		T2	1585		T3	495
valid_sources[0x2e]	278810	1			T1	2		T2	1513		T3	405
valid_sources[0x2f]	235742	1			T1	3		T2	1508		T3	450
valid_sources[0x30]	372987	1			T1	4		T2	1543		T3	467
valid_sources[0x31]	309707	1			T1	7		T2	1564		T3	402
valid_sources[0x32]	271886	1			T1	1		T2	1595		T3	488
valid_sources[0x33]	268859	1			T1	5		T2	1606		T3	409
valid_sources[0x34]	295639	1			T1	5		T2	1584		T3	447
valid_sources[0x35]	248434	1			T1	2		T2	1541		T3	540
valid_sources[0x36]	275993	1			T1	3		T2	1505		T3	465
valid_sources[0x37]	282430	1			T1	7		T2	1510		T3	439
valid_sources[0x38]	274299	1			T1	6		T2	1513		T3	442
valid_sources[0x39]	275664	1			T1	4		T2	1621		T3	513
valid_sources[0x3a]	318406	1			T1	1		T2	1601		T3	448
valid_sources[0x3b]	270285	1			T1	1		T2	1450		T3	431
valid_sources[0x3c]	292815	1			T1	2		T2	1603		T3	479
valid_sources[0x3d]	297001	1			T1	4		T2	1535		T3	483
valid_sources[0x3e]	301119	1			T1	4		T2	1568		T3	431
valid_sources[0x3f]	282767	1			T1	5		T2	1521		T3	418
valid_sources[0x40]	255317	1			T1	6		T2	1557		T3	461
valid_sources[0x41]	279224	1			T1	2		T2	1511		T3	461
valid_sources[0x42]	306475	1			T1	3		T2	1611		T3	380
valid_sources[0x43]	261312	1			T1	3		T2	1682		T3	470
valid_sources[0x44]	276381	1			T1	4		T2	1562		T3	499
valid_sources[0x45]	262186	1			T1	2		T2	1507		T3	424
valid_sources[0x46]	261687	1			T2	1506		T3	503		T5	633
valid_sources[0x47]	273871	1			T1	5		T2	1563		T3	417
valid_sources[0x48]	356874	1			T1	7		T2	1551		T3	444
valid_sources[0x49]	244167	1			T2	1477		T3	474		T5	609
valid_sources[0x4a]	272933	1			T1	2		T2	1460		T3	501
valid_sources[0x4b]	251357	1			T1	2		T2	1591		T3	475
valid_sources[0x4c]	246685	1			T1	11		T2	1498		T3	464
valid_sources[0x4d]	341612	1			T1	5		T2	1455		T3	473
valid_sources[0x4e]	346430	1			T1	2		T2	1543		T3	461
valid_sources[0x4f]	268496	1			T1	2		T2	1479		T3	407
valid_sources[0x50]	294730	1			T1	4		T2	1564		T3	446
valid_sources[0x51]	275235	1			T1	8		T2	1635		T3	423
valid_sources[0x52]	322069	1			T1	2		T2	1557		T3	515
valid_sources[0x53]	256744	1			T1	7		T2	1619		T3	406
valid_sources[0x54]	299242	1			T1	2		T2	1539		T3	453
valid_sources[0x55]	242230	1			T1	1		T2	1593		T3	423
valid_sources[0x56]	336299	1			T1	7		T2	1542		T3	482
valid_sources[0x57]	312355	1			T1	10		T2	1518		T3	549
valid_sources[0x58]	316631	1			T1	3		T2	1588		T3	423
valid_sources[0x59]	264271	1			T1	2		T2	1539		T3	416
valid_sources[0x5a]	247749	1			T1	1		T2	1551		T3	474
valid_sources[0x5b]	285263	1			T1	6		T2	1602		T3	473
valid_sources[0x5c]	239606	1			T1	3		T2	1564		T3	429
valid_sources[0x5d]	414413	1			T1	6		T2	1589		T3	402
valid_sources[0x5e]	255879	1			T1	6		T2	1553		T3	484
valid_sources[0x5f]	344245	1			T1	2		T2	1544		T3	467
valid_sources[0x60]	244116	1			T1	2		T2	1582		T3	465
valid_sources[0x61]	254037	1			T1	5		T2	1561		T3	484
valid_sources[0x62]	315518	1			T1	6		T2	1555		T3	485
valid_sources[0x63]	298672	1			T1	7		T2	1497		T3	392
valid_sources[0x64]	350214	1			T1	4		T2	1483		T3	437
valid_sources[0x65]	299490	1			T1	1		T2	1560		T3	451
valid_sources[0x66]	246806	1			T1	3		T2	1601		T3	486
valid_sources[0x67]	275818	1			T1	1		T2	1537		T3	383
valid_sources[0x68]	360910	1			T1	8		T2	1599		T3	419
valid_sources[0x69]	293846	1			T1	5		T2	1501		T3	382
valid_sources[0x6a]	340762	1			T1	1		T2	1520		T3	371
valid_sources[0x6b]	311782	1			T1	3		T2	1646		T3	478
valid_sources[0x6c]	473664	1			T1	2		T2	1648		T3	484
valid_sources[0x6d]	304783	1			T1	4		T2	1543		T3	464
valid_sources[0x6e]	241418	1			T1	6		T2	1531		T3	420
valid_sources[0x6f]	421814	1			T1	3		T2	1534		T3	486
valid_sources[0x70]	305578	1			T1	2		T2	1543		T3	427
valid_sources[0x71]	324864	1			T1	2		T2	1565		T3	511
valid_sources[0x72]	273177	1			T1	3		T2	1521		T3	488
valid_sources[0x73]	267117	1			T1	3		T2	1563		T3	388
valid_sources[0x74]	259659	1			T1	1		T2	1510		T3	425
valid_sources[0x75]	254617	1			T1	2		T2	1700		T3	431
valid_sources[0x76]	298025	1			T1	2		T2	1513		T3	413
valid_sources[0x77]	267786	1			T1	6		T2	1500		T3	504
valid_sources[0x78]	245119	1			T1	1		T2	1556		T3	472
valid_sources[0x79]	381873	1			T1	3		T2	1526		T3	453
valid_sources[0x7a]	300421	1			T1	6		T2	1560		T3	466
valid_sources[0x7b]	321789	1			T1	3		T2	1490		T3	410
valid_sources[0x7c]	279717	1			T2	1590		T3	452		T5	643
valid_sources[0x7d]	270019	1			T1	4		T2	1649		T3	454
valid_sources[0x7e]	267860	1			T1	2		T2	1529		T3	420
valid_sources[0x7f]	266367	1			T1	1		T2	1485		T3	518
valid_sources[0x80]	282653	1			T1	4		T2	1617		T3	424

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29661717

1

T1

452

T2

180147

T3

51865

values[0x0]

all_enables

biggest_size

14932747

1

T1

226

T2

90186

T3

25983

values[0x1]

all_enables

biggest_size

14928721

1

T1

183

T2

89729

T3

25967

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

133383

1

T2

3

T3

1

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48010	1			T17	20		T25	5		T7	16
values[0x0]	57618	1			T2	4		T3	3		T4	3
values[0x1]	60445	1			T1	2		T2	3		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140930

1

T2

3

T3

1

T4

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	485	1			T29	11		T31	1		T137	1
valid_sources[0x01]	585	1			T29	17		T31	48		T137	1
valid_sources[0x02]	632	1			T29	26		T31	42		T137	1
valid_sources[0x03]	868	1			T7	1		T49	1		T29	14
valid_sources[0x04]	471	1			T16	1		T29	18		T31	7
valid_sources[0x05]	538	1			T21	1		T83	3		T29	26
valid_sources[0x06]	561	1			T17	1		T29	18		T30	1
valid_sources[0x07]	868	1			T17	1		T29	27		T47	1
valid_sources[0x08]	979	1			T29	18		T31	67		T137	1
valid_sources[0x09]	842	1			T16	1		T29	26		T31	2
valid_sources[0x0a]	670	1			T29	16		T8	12		T137	1
valid_sources[0x0b]	480	1			T7	1		T26	1		T29	25
valid_sources[0x0c]	673	1			T16	1		T103	1		T29	18
valid_sources[0x0d]	576	1			T17	1		T66	1		T49	4
valid_sources[0x0e]	700	1			T29	36		T140	1		T137	1
valid_sources[0x0f]	429	1			T13	1		T23	1		T29	8
valid_sources[0x10]	816	1			T13	1		T29	32		T60	1
valid_sources[0x11]	545	1			T29	21		T30	1		T31	2
valid_sources[0x12]	480	1			T29	12		T30	1		T31	2
valid_sources[0x13]	524	1			T29	25		T31	16		T137	1
valid_sources[0x14]	535	1			T29	28		T28	1		T142	3
valid_sources[0x15]	570	1			T29	26		T31	20		T137	1
valid_sources[0x16]	499	1			T50	1		T29	25		T31	48
valid_sources[0x17]	563	1			T29	16		T30	4		T31	30
valid_sources[0x18]	652	1			T29	34		T31	8		T137	2
valid_sources[0x19]	1080	1			T29	13		T60	1		T63	3
valid_sources[0x1a]	1123	1			T15	2		T29	34		T30	2
valid_sources[0x1b]	624	1			T26	1		T29	12		T62	1
valid_sources[0x1c]	559	1			T50	1		T29	17		T60	1
valid_sources[0x1d]	583	1			T29	28		T30	1		T31	17
valid_sources[0x1e]	577	1			T29	14		T30	1		T31	12
valid_sources[0x1f]	602	1			T29	9		T30	1		T31	1
valid_sources[0x20]	540	1			T17	2		T29	10		T30	1
valid_sources[0x21]	540	1			T16	1		T26	1		T29	29
valid_sources[0x22]	429	1			T17	3		T29	9		T31	10
valid_sources[0x23]	484	1			T12	2		T29	14		T31	32
valid_sources[0x24]	916	1			T5	3		T29	34		T62	6
valid_sources[0x25]	446	1			T29	24		T31	6		T137	1
valid_sources[0x26]	775	1			T26	1		T29	23		T31	78
valid_sources[0x27]	790	1			T16	1		T29	37		T31	3
valid_sources[0x28]	456	1			T104	1		T29	17		T31	20
valid_sources[0x29]	463	1			T23	1		T143	2		T65	1
valid_sources[0x2a]	783	1			T26	3		T29	24		T31	7
valid_sources[0x2b]	563	1			T26	1		T29	17		T30	1
valid_sources[0x2c]	659	1			T29	38		T31	25		T32	1
valid_sources[0x2d]	571	1			T21	1		T7	2		T26	1
valid_sources[0x2e]	730	1			T29	19		T30	2		T31	11
valid_sources[0x2f]	467	1			T12	1		T67	10		T29	18
valid_sources[0x30]	447	1			T26	1		T29	12		T31	7
valid_sources[0x31]	632	1			T29	22		T31	14		T144	1
valid_sources[0x32]	724	1			T67	11		T29	13		T31	4
valid_sources[0x33]	623	1			T26	1		T29	35		T31	26
valid_sources[0x34]	524	1			T29	22		T31	16		T93	24
valid_sources[0x35]	669	1			T13	1		T29	26		T60	1
valid_sources[0x36]	444	1			T17	1		T23	1		T29	30
valid_sources[0x37]	517	1			T29	20		T30	1		T31	56
valid_sources[0x38]	496	1			T2	7		T26	2		T145	1
valid_sources[0x39]	606	1			T49	2		T65	2		T29	24
valid_sources[0x3a]	488	1			T21	1		T29	13		T31	3
valid_sources[0x3b]	645	1			T23	1		T29	16		T31	1
valid_sources[0x3c]	648	1			T29	27		T40	4		T51	33
valid_sources[0x3d]	640	1			T10	1		T29	10		T31	1
valid_sources[0x3e]	431	1			T16	1		T29	24		T31	1
valid_sources[0x3f]	453	1			T29	22		T30	1		T8	2
valid_sources[0x40]	524	1			T14	1		T104	1		T29	20
valid_sources[0x41]	540	1			T29	24		T47	1		T31	8
valid_sources[0x42]	639	1			T1	1		T16	2		T29	31
valid_sources[0x43]	650	1			T29	22		T30	1		T31	67
valid_sources[0x44]	676	1			T26	2		T104	1		T29	18
valid_sources[0x45]	597	1			T13	1		T29	27		T30	3
valid_sources[0x46]	557	1			T16	1		T26	1		T29	13
valid_sources[0x47]	1006	1			T29	44		T137	2		T32	3
valid_sources[0x48]	725	1			T26	1		T29	9		T60	1
valid_sources[0x49]	605	1			T29	12		T63	1		T31	6
valid_sources[0x4a]	441	1			T16	1		T29	32		T47	3
valid_sources[0x4b]	788	1			T7	2		T26	1		T29	8
valid_sources[0x4c]	596	1			T29	13		T31	1		T52	2
valid_sources[0x4d]	732	1			T26	1		T29	15		T63	3
valid_sources[0x4e]	636	1			T13	1		T29	13		T30	2
valid_sources[0x4f]	636	1			T17	4		T26	1		T29	11
valid_sources[0x50]	828	1			T29	28		T31	58		T51	23
valid_sources[0x51]	732	1			T29	29		T31	19		T137	2
valid_sources[0x52]	573	1			T29	18		T32	3		T51	3
valid_sources[0x53]	592	1			T65	2		T29	24		T31	2
valid_sources[0x54]	654	1			T17	12		T29	16		T30	1
valid_sources[0x55]	630	1			T13	1		T17	1		T7	2
valid_sources[0x56]	842	1			T13	2		T26	2		T29	12
valid_sources[0x57]	541	1			T69	1		T29	19		T31	8
valid_sources[0x58]	523	1			T29	20		T61	30		T31	21
valid_sources[0x59]	904	1			T17	1		T7	2		T29	29
valid_sources[0x5a]	724	1			T13	1		T16	1		T29	22
valid_sources[0x5b]	795	1			T17	6		T26	1		T139	14
valid_sources[0x5c]	509	1			T26	1		T29	29		T137	1
valid_sources[0x5d]	775	1			T16	1		T29	32		T31	49
valid_sources[0x5e]	650	1			T5	9		T29	15		T30	1
valid_sources[0x5f]	861	1			T7	2		T29	27		T30	1
valid_sources[0x60]	546	1			T85	2		T29	27		T137	1
valid_sources[0x61]	533	1			T13	2		T29	10		T31	29
valid_sources[0x62]	653	1			T26	1		T29	24		T31	35
valid_sources[0x63]	894	1			T16	1		T67	7		T29	17
valid_sources[0x64]	752	1			T26	1		T65	4		T29	17
valid_sources[0x65]	433	1			T65	1		T29	20		T137	1
valid_sources[0x66]	745	1			T29	11		T30	1		T31	2
valid_sources[0x67]	484	1			T86	4		T65	1		T29	8
valid_sources[0x68]	690	1			T29	21		T31	21		T18	1
valid_sources[0x69]	796	1			T17	1		T29	31		T31	28
valid_sources[0x6a]	754	1			T26	1		T29	18		T31	46
valid_sources[0x6b]	853	1			T7	1		T49	1		T29	14
valid_sources[0x6c]	514	1			T1	1		T5	1		T29	13
valid_sources[0x6d]	612	1			T17	7		T7	3		T29	19
valid_sources[0x6e]	665	1			T21	1		T49	1		T29	23
valid_sources[0x6f]	475	1			T49	2		T26	1		T29	26
valid_sources[0x70]	742	1			T10	1		T29	9		T30	1
valid_sources[0x71]	658	1			T29	26		T31	21		T41	1
valid_sources[0x72]	803	1			T66	1		T26	1		T33	1
valid_sources[0x73]	589	1			T13	1		T29	13		T31	46
valid_sources[0x74]	828	1			T16	1		T7	1		T29	16
valid_sources[0x75]	791	1			T26	1		T29	20		T31	8
valid_sources[0x76]	519	1			T13	1		T102	4		T29	13
valid_sources[0x77]	847	1			T29	18		T31	44		T40	1
valid_sources[0x78]	1158	1			T50	1		T29	18		T31	1
valid_sources[0x79]	627	1			T16	2		T17	3		T29	18
valid_sources[0x7a]	540	1			T5	5		T26	1		T29	34
valid_sources[0x7b]	538	1			T29	30		T31	27		T28	3
valid_sources[0x7c]	511	1			T29	14		T30	1		T31	53
valid_sources[0x7d]	634	1			T17	1		T29	22		T60	1
valid_sources[0x7e]	659	1			T26	1		T29	35		T31	19
valid_sources[0x7f]	1223	1			T29	15		T31	53		T32	2
valid_sources[0x80]	770	1			T16	1		T29	20		T47	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36312

1

T17

10

T25

2

T7

7

values[0x0]

all_enables

biggest_size

49850

1

T2

3

T3

1

T4

2

values[0x1]

all_enables

biggest_size

47221

1

T4

1

T5

2

T13

3