Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13929308

1

T2

35991

T3

10286

T4

6332

full_word

54545364

1

T1

861

T2

360062

T3

103815

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68474362	1			T1	861		T2	396053		T3	114101
auto[TlIntgErrCmd]	90	1			T106	3		T107	5		T108	1
auto[TlIntgErrData]	116	1			T106	3		T107	7		T108	5
auto[TlIntgErrBoth]	104	1			T106	4		T107	8		T108	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31406475

1

T1

452

T2

198156

T3

57088

auto[1]

37068197

1

T1

409

T2

197897

T3

57013

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6660375	1			T2	18009		T3	5223		T4	3183
auto[TlIntgErrNone]	partial	auto[1]	7268641	1			T2	17982		T3	5063		T4	3149
auto[TlIntgErrNone]	full_word	auto[0]	24745979	1			T1	452		T2	180147		T3	51865
auto[TlIntgErrNone]	full_word	auto[1]	29799367	1			T1	409		T2	179915		T3	51950
auto[TlIntgErrCmd]	partial	auto[0]	23	1			T123	1		T124	1		T127	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T106	3		T107	5		T108	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T131	1		T132	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T133	1		T132	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T106	2		T107	2		T108	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T106	1		T107	5		T108	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T130	1		T134	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T128	1		T130	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T107	3		T123	1		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T106	4		T107	5		T108	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T123	1		T124	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T124	1		T130	1		T126	1