Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	569300	1			T5	694		T6	905		T14	62
auto[1]	10507339	1			T1	451		T2	165245		T3	48046
auto[2]	483799	1			T5	467		T6	769		T14	29
auto[3]	10440262	1			T1	408		T2	164934		T3	47913

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14329721	1			T1	859		T2	275317		T3	79607
auto[1]	2114051	1			T2	26262		T3	7661		T4	311
auto[2]	2117535	1			T2	26049		T3	7976		T4	294
auto[3]	3439393	1			T2	2551		T3	715		T4	45

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9132559

1

T1

857

T2

41

T4

2210

auto[1]

12868141

1

T1

2

T2

330138

T3

95959

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	320467	1			T5	567		T6	717		T7	10
auto[0]	auto[0]	auto[1]	33097	1			T5	63		T6	93		T71	3
auto[0]	auto[0]	auto[2]	33085	1			T5	59		T6	88		T71	3
auto[0]	auto[0]	auto[3]	9801	1			T5	5		T6	6		T14	60
auto[0]	auto[1]	auto[0]	3442599	1			T1	451		T2	17		T4	790
auto[0]	auto[1]	auto[1]	363150	1			T4	234		T5	76		T6	60
auto[0]	auto[1]	auto[2]	347505	1			T2	1		T4	77		T5	37
auto[0]	auto[1]	auto[3]	67004	1			T4	24		T5	8		T6	5
auto[0]	auto[2]	auto[0]	279361	1			T5	364		T6	656		T7	10
auto[0]	auto[2]	auto[1]	28995	1			T5	37		T6	60		T14	2
auto[0]	auto[2]	auto[2]	26901	1			T5	57		T6	44		T71	2
auto[0]	auto[2]	auto[3]	7908	1			T5	9		T6	6		T14	27
auto[0]	auto[3]	auto[0]	3400141	1			T1	406		T2	17		T4	771
auto[0]	auto[3]	auto[1]	343502	1			T2	3		T4	76		T5	20
auto[0]	auto[3]	auto[2]	359066	1			T2	3		T4	217		T5	82
auto[0]	auto[3]	auto[3]	69977	1			T4	21		T5	5		T6	8
auto[1]	auto[0]	auto[0]	6046	1			T6	1		T49	1		T83	477
auto[1]	auto[0]	auto[1]	25839	1			T49	1		T83	2052		T58	2288
auto[1]	auto[0]	auto[2]	25635	1			T83	2000		T139	1		T58	2340
auto[1]	auto[0]	auto[3]	115330	1			T14	2		T71	1		T83	9143
auto[1]	auto[1]	auto[0]	3436643	1			T2	137680		T3	39841		T4	2
auto[1]	auto[1]	auto[1]	658733	1			T2	12525		T3	3812		T4	1
auto[1]	auto[1]	auto[2]	647580	1			T2	13738		T3	4039		T11	1
auto[1]	auto[1]	auto[3]	1544125	1			T2	1284		T3	354		T10	3
auto[1]	auto[2]	auto[0]	4413	1			T6	3		T49	1		T83	387
auto[1]	auto[2]	auto[1]	19028	1			T49	1		T83	1794		T139	1
auto[1]	auto[2]	auto[2]	21384	1			T83	1423		T50	1		T58	2197
auto[1]	auto[2]	auto[3]	95809	1			T83	5953		T58	9912		T140	9899
auto[1]	auto[3]	auto[0]	3440051	1			T1	2		T2	137603		T3	39766
auto[1]	auto[3]	auto[1]	641707	1			T2	13734		T3	3849		T10	1
auto[1]	auto[3]	auto[2]	656379	1			T2	12307		T3	3937		T10	1
auto[1]	auto[3]	auto[3]	1529439	1			T2	1267		T3	361		T10	2