Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	319649452	130259	0	0
ctrl_regwen_rd_A	319649452	7554	0	0
exec_rd_A	319649452	6930	0	0
exec_regwen_rd_A	319649452	7168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319649452	130259	0	0
T27	123548	0	0	0
T29	188079	6477	0	0
T30	930954	0	0	0
T31	0	5532	0	0
T32	0	2568	0	0
T47	401361	0	0	0
T51	0	1499	0	0
T52	0	1220	0	0
T53	0	544	0	0
T54	0	1549	0	0
T55	0	3837	0	0
T56	0	3156	0	0
T57	0	1887	0	0
T58	183723	0	0	0
T59	306822	0	0	0
T60	832753	0	0	0
T61	716872	0	0	0
T62	355799	0	0	0
T63	124946	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319649452	7554	0	0
T32	131567	640	0	0
T35	2762	0	0	0
T51	0	177	0	0
T53	0	79	0	0
T54	0	528	0	0
T55	0	755	0	0
T110	0	644	0	0
T111	0	772	0	0
T112	0	189	0	0
T113	0	510	0	0
T114	0	368	0	0
T115	83926	0	0	0
T116	32839	0	0	0
T117	317671	0	0	0
T118	12305	0	0	0
T119	1735	0	0	0
T120	4000	0	0	0
T121	32754	0	0	0
T122	230193	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319649452	6930	0	0
T32	131567	546	0	0
T35	2762	0	0	0
T51	0	147	0	0
T53	0	93	0	0
T54	0	402	0	0
T55	0	681	0	0
T110	0	506	0	0
T111	0	738	0	0
T112	0	214	0	0
T113	0	437	0	0
T114	0	418	0	0
T115	83926	0	0	0
T116	32839	0	0	0
T117	317671	0	0	0
T118	12305	0	0	0
T119	1735	0	0	0
T120	4000	0	0	0
T121	32754	0	0	0
T122	230193	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	319649452	7168	0	0
T32	131567	583	0	0
T35	2762	0	0	0
T51	0	111	0	0
T53	0	108	0	0
T54	0	520	0	0
T55	0	796	0	0
T110	0	570	0	0
T111	0	650	0	0
T112	0	207	0	0
T113	0	391	0	0
T114	0	358	0	0
T115	83926	0	0	0
T116	32839	0	0	0
T117	317671	0	0	0
T118	12305	0	0	0
T119	1735	0	0	0
T120	4000	0	0	0
T121	32754	0	0	0
T122	230193	0	0	0