Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13820770	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57401943

1

T1

7299

T2

93604

T4

93

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35503410	1			T1	3966		T2	51646		T4	865
values[0x0]	16479872	1			T1	2020		T2	24715		T4	323
values[0x1]	19239431	1			T1	2007		T2	26656		T4	754

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6888524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64334189

1

T1

7648

T2

98327

T4

888

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	325491	1			T1	44		T2	396		T4	1
valid_sources[0x01]	251442	1			T1	33		T2	373		T4	11
valid_sources[0x02]	252092	1			T1	30		T2	367		T4	12
valid_sources[0x03]	319250	1			T1	26		T2	435		T4	2
valid_sources[0x04]	251669	1			T1	23		T2	370		T4	9
valid_sources[0x05]	303589	1			T1	33		T2	401		T4	11
valid_sources[0x06]	249219	1			T1	31		T2	385		T4	8
valid_sources[0x07]	339034	1			T1	19		T2	369		T4	5
valid_sources[0x08]	307859	1			T1	31		T2	370		T4	19
valid_sources[0x09]	309747	1			T1	26		T2	383		T4	8
valid_sources[0x0a]	260683	1			T1	25		T2	395		T4	12
valid_sources[0x0b]	282657	1			T1	38		T2	406		T4	15
valid_sources[0x0c]	325114	1			T1	29		T2	494		T4	5
valid_sources[0x0d]	267919	1			T1	23		T2	394		T4	13
valid_sources[0x0e]	293606	1			T1	28		T2	380		T4	4
valid_sources[0x0f]	259171	1			T1	25		T2	449		T4	3
valid_sources[0x10]	263083	1			T1	34		T2	376		T4	5
valid_sources[0x11]	246686	1			T1	31		T2	405		T4	2
valid_sources[0x12]	282351	1			T1	28		T2	403		T4	11
valid_sources[0x13]	255494	1			T1	36		T2	412		T4	11
valid_sources[0x14]	329480	1			T1	27		T2	397		T4	14
valid_sources[0x15]	325786	1			T1	30		T2	425		T5	1124
valid_sources[0x16]	269151	1			T1	25		T2	352		T4	17
valid_sources[0x17]	351532	1			T1	43		T2	378		T4	8
valid_sources[0x18]	288609	1			T1	24		T2	405		T4	11
valid_sources[0x19]	247198	1			T1	32		T2	431		T4	6
valid_sources[0x1a]	248828	1			T1	25		T2	391		T4	3
valid_sources[0x1b]	298038	1			T1	31		T2	290		T4	2
valid_sources[0x1c]	287686	1			T1	31		T2	365		T4	6
valid_sources[0x1d]	270510	1			T1	29		T2	412		T4	4
valid_sources[0x1e]	243156	1			T1	29		T2	453		T4	10
valid_sources[0x1f]	248214	1			T1	32		T2	387		T4	13
valid_sources[0x20]	265422	1			T1	26		T2	452		T5	1097
valid_sources[0x21]	253149	1			T1	36		T2	397		T4	5
valid_sources[0x22]	261079	1			T1	31		T2	404		T5	1031
valid_sources[0x23]	296320	1			T1	30		T2	401		T4	1
valid_sources[0x24]	272184	1			T1	33		T2	451		T4	1
valid_sources[0x25]	253906	1			T1	20		T2	433		T4	7
valid_sources[0x26]	234507	1			T1	36		T2	397		T4	12
valid_sources[0x27]	282551	1			T1	39		T2	393		T4	15
valid_sources[0x28]	257053	1			T1	38		T2	452		T4	6
valid_sources[0x29]	247435	1			T1	24		T2	441		T4	6
valid_sources[0x2a]	290159	1			T1	39		T2	394		T4	17
valid_sources[0x2b]	247282	1			T1	41		T2	358		T4	1
valid_sources[0x2c]	241910	1			T1	31		T2	407		T4	5
valid_sources[0x2d]	245711	1			T1	29		T2	448		T4	12
valid_sources[0x2e]	292651	1			T1	26		T2	410		T4	1
valid_sources[0x2f]	297185	1			T1	27		T2	427		T4	5
valid_sources[0x30]	281003	1			T1	32		T2	501		T4	15
valid_sources[0x31]	288967	1			T1	26		T2	415		T4	2
valid_sources[0x32]	287575	1			T1	30		T2	403		T4	1
valid_sources[0x33]	285501	1			T1	29		T2	376		T4	7
valid_sources[0x34]	293202	1			T1	39		T2	377		T4	13
valid_sources[0x35]	267106	1			T1	36		T2	407		T4	1
valid_sources[0x36]	244587	1			T1	34		T2	448		T4	9
valid_sources[0x37]	261353	1			T1	30		T2	381		T4	8
valid_sources[0x38]	265738	1			T1	31		T2	389		T4	8
valid_sources[0x39]	276516	1			T1	38		T2	403		T4	6
valid_sources[0x3a]	288657	1			T1	30		T2	453		T4	1
valid_sources[0x3b]	328073	1			T1	21		T2	444		T4	2
valid_sources[0x3c]	236541	1			T1	28		T2	434		T4	7
valid_sources[0x3d]	259448	1			T1	35		T2	395		T4	18
valid_sources[0x3e]	283852	1			T1	40		T2	375		T4	1
valid_sources[0x3f]	295857	1			T1	34		T2	446		T4	21
valid_sources[0x40]	256654	1			T1	33		T2	373		T4	2
valid_sources[0x41]	271825	1			T1	31		T2	440		T4	7
valid_sources[0x42]	263127	1			T1	38		T2	484		T4	1
valid_sources[0x43]	308293	1			T1	31		T2	347		T4	9
valid_sources[0x44]	244880	1			T1	35		T2	430		T4	2
valid_sources[0x45]	254364	1			T1	41		T2	420		T4	9
valid_sources[0x46]	281021	1			T1	32		T2	376		T4	10
valid_sources[0x47]	276844	1			T1	20		T2	329		T4	5
valid_sources[0x48]	245090	1			T1	26		T2	399		T4	12
valid_sources[0x49]	293212	1			T1	38		T2	413		T4	4
valid_sources[0x4a]	290343	1			T1	31		T2	426		T4	11
valid_sources[0x4b]	280817	1			T1	47		T2	387		T4	7
valid_sources[0x4c]	245169	1			T1	26		T2	380		T4	3
valid_sources[0x4d]	261938	1			T1	44		T2	424		T4	7
valid_sources[0x4e]	245474	1			T1	36		T2	388		T4	7
valid_sources[0x4f]	245719	1			T1	33		T2	387		T4	10
valid_sources[0x50]	263760	1			T1	28		T2	331		T4	18
valid_sources[0x51]	266293	1			T1	36		T2	375		T4	4
valid_sources[0x52]	259504	1			T1	30		T2	414		T4	6
valid_sources[0x53]	270102	1			T1	39		T2	447		T4	4
valid_sources[0x54]	256604	1			T1	28		T2	406		T5	1034
valid_sources[0x55]	238229	1			T1	36		T2	367		T4	4
valid_sources[0x56]	347868	1			T1	43		T2	395		T4	12
valid_sources[0x57]	252932	1			T1	27		T2	433		T4	2
valid_sources[0x58]	251028	1			T1	26		T2	421		T4	5
valid_sources[0x59]	246920	1			T1	25		T2	370		T4	9
valid_sources[0x5a]	297927	1			T1	29		T2	366		T4	5
valid_sources[0x5b]	265795	1			T1	29		T2	391		T4	9
valid_sources[0x5c]	314931	1			T1	33		T2	433		T4	7
valid_sources[0x5d]	346974	1			T1	21		T2	358		T4	8
valid_sources[0x5e]	288428	1			T1	36		T2	374		T4	3
valid_sources[0x5f]	272701	1			T1	33		T2	350		T4	11
valid_sources[0x60]	254394	1			T1	29		T2	409		T4	9
valid_sources[0x61]	336340	1			T1	26		T2	468		T4	24
valid_sources[0x62]	293141	1			T1	55		T2	432		T4	14
valid_sources[0x63]	352414	1			T1	21		T2	410		T4	8
valid_sources[0x64]	236052	1			T1	23		T2	362		T4	4
valid_sources[0x65]	321005	1			T1	36		T2	362		T4	4
valid_sources[0x66]	252237	1			T1	36		T2	388		T4	9
valid_sources[0x67]	394757	1			T1	29		T2	430		T4	11
valid_sources[0x68]	242676	1			T1	24		T2	444		T4	6
valid_sources[0x69]	296349	1			T1	37		T2	406		T4	5
valid_sources[0x6a]	315755	1			T1	26		T2	357		T4	4
valid_sources[0x6b]	257738	1			T1	37		T2	383		T4	9
valid_sources[0x6c]	334992	1			T1	35		T2	408		T4	8
valid_sources[0x6d]	261325	1			T1	29		T2	411		T4	11
valid_sources[0x6e]	286821	1			T1	37		T2	419		T4	9
valid_sources[0x6f]	316726	1			T1	28		T2	404		T4	11
valid_sources[0x70]	283035	1			T1	27		T2	401		T4	12
valid_sources[0x71]	296712	1			T1	37		T2	407		T4	5
valid_sources[0x72]	248482	1			T1	35		T2	395		T4	3
valid_sources[0x73]	280099	1			T1	23		T2	386		T4	9
valid_sources[0x74]	255095	1			T1	49		T2	384		T4	17
valid_sources[0x75]	251898	1			T1	32		T2	370		T4	12
valid_sources[0x76]	255802	1			T1	28		T2	430		T4	3
valid_sources[0x77]	240077	1			T1	30		T2	389		T4	3
valid_sources[0x78]	263958	1			T1	38		T2	419		T4	12
valid_sources[0x79]	274921	1			T1	29		T2	442		T4	6
valid_sources[0x7a]	303058	1			T1	26		T2	360		T4	13
valid_sources[0x7b]	239324	1			T1	26		T2	432		T4	4
valid_sources[0x7c]	260325	1			T1	25		T2	382		T4	8
valid_sources[0x7d]	272481	1			T1	23		T2	343		T4	3
valid_sources[0x7e]	317745	1			T1	27		T2	364		T4	6
valid_sources[0x7f]	277404	1			T1	33		T2	412		T4	2
valid_sources[0x80]	249272	1			T1	43		T2	357		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28596029

1

T1

3600

T2

46946

T4

7

values[0x0]

all_enables

biggest_size

14403167

1

T1

1918

T2

23266

T4

32

values[0x1]

all_enables

biggest_size

14402747

1

T1

1781

T2

23392

T4

54

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

133095

1

T2

7

T5

13

T10

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	47759	1			T16	19		T31	421		T7	37
values[0x0]	56980	1			T2	11		T4	1		T5	22
values[0x1]	60729	1			T1	1		T2	5		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140693

1

T2

7

T5

19

T10

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	780	1			T18	1		T25	2		T31	5
valid_sources[0x01]	538	1			T5	1		T31	3		T27	30
valid_sources[0x02]	539	1			T31	4		T27	27		T132	14
valid_sources[0x03]	546	1			T10	1		T45	1		T31	4
valid_sources[0x04]	870	1			T8	188		T27	16		T64	1
valid_sources[0x05]	517	1			T31	2		T27	24		T32	3
valid_sources[0x06]	564	1			T31	6		T26	2		T27	26
valid_sources[0x07]	665	1			T45	1		T26	1		T139	2
valid_sources[0x08]	581	1			T45	1		T31	10		T27	29
valid_sources[0x09]	673	1			T31	1		T26	2		T27	25
valid_sources[0x0a]	788	1			T31	4		T22	1		T26	1
valid_sources[0x0b]	776	1			T5	1		T31	3		T27	17
valid_sources[0x0c]	860	1			T27	26		T32	6		T48	38
valid_sources[0x0d]	609	1			T31	8		T27	28		T63	16
valid_sources[0x0e]	544	1			T18	1		T45	2		T31	15
valid_sources[0x0f]	666	1			T31	5		T27	24		T64	1
valid_sources[0x10]	558	1			T31	5		T27	22		T64	1
valid_sources[0x11]	539	1			T5	1		T18	1		T31	7
valid_sources[0x12]	569	1			T31	2		T46	2		T27	24
valid_sources[0x13]	829	1			T31	12		T26	1		T140	4
valid_sources[0x14]	730	1			T31	9		T98	4		T27	23
valid_sources[0x15]	698	1			T5	1		T31	7		T27	22
valid_sources[0x16]	591	1			T31	7		T141	2		T27	22
valid_sources[0x17]	497	1			T5	1		T31	3		T46	2
valid_sources[0x18]	713	1			T31	1		T27	29		T64	1
valid_sources[0x19]	647	1			T31	10		T26	3		T46	2
valid_sources[0x1a]	588	1			T5	1		T45	1		T31	1
valid_sources[0x1b]	618	1			T5	1		T142	1		T31	6
valid_sources[0x1c]	670	1			T5	1		T31	2		T60	1
valid_sources[0x1d]	620	1			T5	1		T31	4		T26	2
valid_sources[0x1e]	786	1			T31	1		T27	24		T64	1
valid_sources[0x1f]	576	1			T45	1		T31	7		T59	1
valid_sources[0x20]	472	1			T31	1		T26	3		T27	32
valid_sources[0x21]	605	1			T31	4		T22	1		T27	13
valid_sources[0x22]	708	1			T66	1		T27	18		T9	3
valid_sources[0x23]	587	1			T10	2		T18	1		T31	14
valid_sources[0x24]	504	1			T31	7		T62	2		T27	22
valid_sources[0x25]	1024	1			T31	5		T26	1		T27	27
valid_sources[0x26]	709	1			T4	1		T31	6		T26	1
valid_sources[0x27]	685	1			T10	1		T31	9		T26	3
valid_sources[0x28]	576	1			T10	1		T31	5		T26	5
valid_sources[0x29]	718	1			T31	14		T27	25		T32	5
valid_sources[0x2a]	621	1			T5	2		T18	1		T31	7
valid_sources[0x2b]	591	1			T5	1		T17	1		T45	2
valid_sources[0x2c]	508	1			T15	2		T31	4		T26	1
valid_sources[0x2d]	653	1			T5	1		T62	2		T27	26
valid_sources[0x2e]	817	1			T31	4		T26	2		T46	3
valid_sources[0x2f]	758	1			T16	3		T31	4		T46	2
valid_sources[0x30]	771	1			T31	2		T27	25		T64	1
valid_sources[0x31]	680	1			T5	2		T31	2		T26	3
valid_sources[0x32]	485	1			T13	1		T16	3		T31	8
valid_sources[0x33]	610	1			T31	8		T27	27		T64	1
valid_sources[0x34]	567	1			T31	4		T27	31		T143	1
valid_sources[0x35]	603	1			T31	3		T27	21		T64	1
valid_sources[0x36]	449	1			T31	10		T27	13		T64	1
valid_sources[0x37]	632	1			T18	1		T31	13		T46	1
valid_sources[0x38]	1095	1			T100	2		T31	4		T144	1
valid_sources[0x39]	682	1			T31	2		T144	2		T27	25
valid_sources[0x3a]	528	1			T25	1		T31	5		T26	1
valid_sources[0x3b]	576	1			T31	3		T27	29		T32	2
valid_sources[0x3c]	726	1			T5	1		T18	2		T31	1
valid_sources[0x3d]	567	1			T31	7		T26	2		T46	1
valid_sources[0x3e]	548	1			T5	1		T31	4		T46	2
valid_sources[0x3f]	524	1			T31	11		T27	19		T32	12
valid_sources[0x40]	520	1			T5	1		T31	2		T27	27
valid_sources[0x41]	593	1			T31	1		T27	24		T64	1
valid_sources[0x42]	570	1			T31	1		T27	22		T32	2
valid_sources[0x43]	734	1			T10	1		T31	3		T46	1
valid_sources[0x44]	493	1			T31	7		T62	12		T27	26
valid_sources[0x45]	701	1			T45	1		T31	5		T26	1
valid_sources[0x46]	493	1			T3	1		T31	15		T27	23
valid_sources[0x47]	570	1			T31	3		T26	5		T27	24
valid_sources[0x48]	732	1			T31	2		T27	23		T32	2
valid_sources[0x49]	549	1			T14	6		T45	1		T31	1
valid_sources[0x4a]	741	1			T31	4		T7	80		T26	3
valid_sources[0x4b]	634	1			T31	7		T27	31		T32	9
valid_sources[0x4c]	570	1			T5	1		T45	1		T31	13
valid_sources[0x4d]	574	1			T5	2		T31	4		T62	5
valid_sources[0x4e]	772	1			T18	1		T31	25		T26	1
valid_sources[0x4f]	452	1			T16	5		T22	1		T27	26
valid_sources[0x50]	622	1			T18	1		T31	2		T27	29
valid_sources[0x51]	487	1			T145	9		T27	25		T32	1
valid_sources[0x52]	649	1			T45	1		T31	12		T26	5
valid_sources[0x53]	490	1			T25	2		T45	1		T31	1
valid_sources[0x54]	983	1			T5	1		T45	1		T31	3
valid_sources[0x55]	601	1			T10	1		T16	15		T31	1
valid_sources[0x56]	589	1			T31	4		T27	27		T32	12
valid_sources[0x57]	498	1			T31	9		T27	34		T32	7
valid_sources[0x58]	965	1			T5	1		T10	1		T45	1
valid_sources[0x59]	533	1			T31	6		T26	2		T27	26
valid_sources[0x5a]	575	1			T18	1		T31	5		T46	1
valid_sources[0x5b]	1043	1			T66	1		T45	1		T31	1
valid_sources[0x5c]	710	1			T31	11		T27	31		T143	1
valid_sources[0x5d]	527	1			T31	6		T46	2		T27	26
valid_sources[0x5e]	553	1			T18	2		T27	25		T32	1
valid_sources[0x5f]	577	1			T26	1		T27	25		T32	16
valid_sources[0x60]	631	1			T31	8		T27	28		T146	8
valid_sources[0x61]	484	1			T45	1		T31	2		T26	4
valid_sources[0x62]	685	1			T31	16		T26	1		T27	30
valid_sources[0x63]	531	1			T31	16		T27	37		T32	16
valid_sources[0x64]	642	1			T147	1		T27	28		T32	11
valid_sources[0x65]	680	1			T31	14		T27	20		T64	1
valid_sources[0x66]	592	1			T10	1		T31	3		T26	4
valid_sources[0x67]	746	1			T18	1		T31	9		T26	1
valid_sources[0x68]	849	1			T16	4		T18	1		T45	1
valid_sources[0x69]	604	1			T31	7		T27	21		T148	44
valid_sources[0x6a]	836	1			T18	1		T31	1		T26	1
valid_sources[0x6b]	508	1			T5	1		T66	1		T31	10
valid_sources[0x6c]	727	1			T25	1		T31	27		T147	1
valid_sources[0x6d]	615	1			T31	3		T26	2		T85	1
valid_sources[0x6e]	481	1			T31	11		T27	28		T32	2
valid_sources[0x6f]	501	1			T31	14		T27	27		T65	1
valid_sources[0x70]	504	1			T31	2		T27	23		T64	2
valid_sources[0x71]	665	1			T66	1		T31	8		T27	27
valid_sources[0x72]	1014	1			T31	6		T27	26		T64	1
valid_sources[0x73]	552	1			T31	7		T27	25		T32	15
valid_sources[0x74]	564	1			T13	1		T31	12		T140	2
valid_sources[0x75]	605	1			T31	3		T26	1		T140	1
valid_sources[0x76]	614	1			T10	1		T18	1		T31	3
valid_sources[0x77]	859	1			T10	1		T31	4		T147	1
valid_sources[0x78]	636	1			T10	1		T27	23		T64	1
valid_sources[0x79]	577	1			T18	1		T31	7		T27	25
valid_sources[0x7a]	493	1			T31	4		T22	1		T46	1
valid_sources[0x7b]	942	1			T31	4		T26	1		T27	24
valid_sources[0x7c]	658	1			T31	15		T26	2		T27	21
valid_sources[0x7d]	757	1			T2	16		T5	1		T18	1
valid_sources[0x7e]	547	1			T31	2		T26	1		T27	20
valid_sources[0x7f]	724	1			T18	1		T31	3		T26	1
valid_sources[0x80]	776	1			T10	1		T31	5		T149	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36441

1

T16

11

T31

373

T7

19

values[0x0]

all_enables

biggest_size

49085

1

T2

4

T5

7

T10

4

values[0x1]

all_enables

biggest_size

47569

1

T2

3

T5

6

T10

1