Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13514265

1

T1

694

T2

7507

T4

1849

full_word

52528861

1

T1

7299

T2

74837

T4

93

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66042856	1			T1	7993		T2	82344		T4	1942
auto[TlIntgErrCmd]	86	1			T101	5		T102	4		T103	11
auto[TlIntgErrData]	100	1			T101	8		T102	5		T103	6
auto[TlIntgErrBoth]	84	1			T101	7		T102	1		T103	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30254763

1

T1

3966

T2

30973

T4

865

auto[1]

35788363

1

T1

4027

T2

51371

T4

1077

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6463315	1			T1	366		T2	2794		T4	858
auto[TlIntgErrNone]	partial	auto[1]	7050706	1			T1	328		T2	4713		T4	991
auto[TlIntgErrNone]	full_word	auto[0]	23791328	1			T1	3600		T2	28179		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	28737507	1			T1	3699		T2	46658		T4	86
auto[TlIntgErrCmd]	partial	auto[0]	27	1			T101	1		T102	1		T103	4
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T101	2		T102	2		T103	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T101	2		T103	2		T128	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T102	1		T129	2		T130	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T101	4		T102	3		T103	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T101	4		T103	3		T122	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T102	1		T122	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T102	1		T103	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T101	3		T102	1		T103	2
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T101	3		T103	1		T122	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T101	1		T123	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T131	1		-	-		-	-