Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	534485	1			T2	921		T14	923		T15	23227
auto[1]	10387870	1			T1	3966		T2	224		T4	781
auto[2]	449850	1			T2	868		T14	822		T15	19679
auto[3]	10319535	1			T1	4025		T2	150		T4	987

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14003632	1			T1	6717		T2	1681		T4	8
auto[1]	2099227	1			T1	581		T2	224		T4	84
auto[2]	2090849	1			T1	638		T2	237		T4	144
auto[3]	3498032	1			T1	55		T2	21		T4	1532

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7524479

1

T1

7986

T2

2163

T4

1766

auto[1]

14167261

1

T1

5

T4

2

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	247759	1			T2	770		T14	769		T31	2
auto[0]	auto[0]	auto[1]	25377	1			T2	75		T14	74		T47	209
auto[0]	auto[0]	auto[2]	25102	1			T2	72		T14	73		T47	209
auto[0]	auto[0]	auto[3]	6425	1			T2	4		T14	7		T47	15
auto[0]	auto[1]	auto[0]	2837981	1			T1	3321		T2	125		T4	2
auto[0]	auto[1]	auto[1]	303747	1			T1	276		T2	82		T4	4
auto[0]	auto[1]	auto[2]	287179	1			T1	333		T2	15		T4	72
auto[0]	auto[1]	auto[3]	61726	1			T1	33		T2	2		T4	702
auto[0]	auto[2]	auto[0]	219145	1			T2	730		T14	696		T31	6
auto[0]	auto[2]	auto[1]	22511	1			T2	65		T14	63		T47	183
auto[0]	auto[2]	auto[2]	19705	1			T2	66		T14	55		T47	136
auto[0]	auto[2]	auto[3]	5092	1			T2	7		T14	7		T47	9
auto[0]	auto[3]	auto[0]	2811749	1			T1	3391		T2	56		T4	6
auto[0]	auto[3]	auto[1]	284244	1			T1	305		T2	2		T4	80
auto[0]	auto[3]	auto[2]	301406	1			T1	305		T2	84		T4	72
auto[0]	auto[3]	auto[3]	65331	1			T1	22		T2	8		T4	828
auto[1]	auto[0]	auto[0]	7795	1			T15	732		T47	1		T57	1
auto[1]	auto[0]	auto[1]	34023	1			T15	3390		T134	901		T135	2815
auto[1]	auto[0]	auto[2]	34119	1			T15	3470		T47	1		T61	1
auto[1]	auto[0]	auto[3]	153885	1			T15	15635		T134	4200		T86	1
auto[1]	auto[1]	auto[0]	3935182	1			T1	3		T12	88478		T13	42313
auto[1]	auto[1]	auto[1]	712383	1			T12	8448		T13	3755		T17	18562
auto[1]	auto[1]	auto[2]	691582	1			T12	8921		T13	4224		T16	1
auto[1]	auto[1]	auto[3]	1558090	1			T4	1		T12	852		T13	378
auto[1]	auto[2]	auto[0]	6920	1			T14	1		T15	705		T47	1
auto[1]	auto[2]	auto[1]	29869	1			T15	3137		T136	2		T134	536
auto[1]	auto[2]	auto[2]	26580	1			T15	2918		T136	1		T134	1039
auto[1]	auto[2]	auto[3]	120028	1			T15	12919		T134	4725		T117	1
auto[1]	auto[3]	auto[0]	3937101	1			T1	2		T5	1		T12	88179
auto[1]	auto[3]	auto[1]	687073	1			T12	8821		T13	4189		T17	18188
auto[1]	auto[3]	auto[2]	705176	1			T12	8737		T13	3726		T16	1
auto[1]	auto[3]	auto[3]	1527455	1			T4	1		T12	869		T13	369