Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.39	100.00	94.62	100.00		100.00	92.31	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	307670715	118440	0	0
ctrl_regwen_rd_A	307670715	6638	0	0
exec_rd_A	307670715	5880	0	0
exec_regwen_rd_A	307670715	6283	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307670715	118440	0	0
T7	78499	0	0	0
T22	1197	0	0	0
T27	0	6346	0	0
T31	30936	1113	0	0
T32	0	1303	0	0
T47	218118	0	0	0
T48	0	6655	0	0
T49	0	3035	0	0
T50	0	3050	0	0
T51	0	1050	0	0
T52	0	1781	0	0
T53	0	3252	0	0
T54	0	2129	0	0
T55	2170	0	0	0
T56	13522	0	0	0
T57	44336	0	0	0
T58	64953	0	0	0
T59	647229	0	0	0
T60	15424	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307670715	6638	0	0
T32	69408	364	0	0
T51	0	290	0	0
T65	408086	0	0	0
T88	35914	0	0	0
T104	0	255	0	0
T105	0	267	0	0
T106	0	121	0	0
T107	0	427	0	0
T108	0	120	0	0
T109	0	1572	0	0
T110	0	305	0	0
T111	0	292	0	0
T112	364942	0	0	0
T113	2119	0	0	0
T114	188885	0	0	0
T115	1917	0	0	0
T116	165904	0	0	0
T117	127122	0	0	0
T118	140821	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307670715	5880	0	0
T32	69408	393	0	0
T51	0	280	0	0
T65	408086	0	0	0
T88	35914	0	0	0
T104	0	196	0	0
T105	0	214	0	0
T106	0	153	0	0
T107	0	315	0	0
T108	0	122	0	0
T109	0	1235	0	0
T110	0	318	0	0
T111	0	223	0	0
T112	364942	0	0	0
T113	2119	0	0	0
T114	188885	0	0	0
T115	1917	0	0	0
T116	165904	0	0	0
T117	127122	0	0	0
T118	140821	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	307670715	6283	0	0
T32	69408	428	0	0
T51	0	274	0	0
T65	408086	0	0	0
T88	35914	0	0	0
T104	0	277	0	0
T105	0	199	0	0
T106	0	190	0	0
T107	0	410	0	0
T108	0	153	0	0
T109	0	1272	0	0
T110	0	374	0	0
T111	0	328	0	0
T112	364942	0	0	0
T113	2119	0	0	0
T114	188885	0	0	0
T115	1917	0	0	0
T116	165904	0	0	0
T117	127122	0	0	0
T118	140821	0	0	0