Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11881442	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33769052

1

T1

5257

T2

6642

T3

8182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22773204	1			T1	2617		T2	3700		T3	5074
values[0x0]	10250072	1			T1	1327		T2	1732		T3	2296
values[0x1]	12627218	1			T1	1313		T2	1856		T3	2630

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5918861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39731633

1

T1

5257

T2

6960

T3

9125

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	167254	1			T1	48		T2	30		T3	62
valid_sources[0x01]	206313	1			T2	35		T3	19		T5	1
valid_sources[0x02]	189611	1			T2	37		T3	58		T5	2
valid_sources[0x03]	178755	1			T1	4		T2	30		T3	21
valid_sources[0x04]	162764	1			T1	12		T2	28		T3	33
valid_sources[0x05]	169116	1			T2	39		T3	52		T5	1
valid_sources[0x06]	154136	1			T1	100		T2	15		T3	31
valid_sources[0x07]	178392	1			T1	2		T2	37		T3	19
valid_sources[0x08]	180312	1			T1	25		T2	22		T3	36
valid_sources[0x09]	155487	1			T2	27		T3	44		T5	5
valid_sources[0x0a]	160194	1			T2	12		T3	65		T5	16
valid_sources[0x0b]	171732	1			T2	34		T3	33		T5	1
valid_sources[0x0c]	205144	1			T2	24		T3	56		T5	6
valid_sources[0x0d]	167651	1			T1	22		T2	19		T3	25
valid_sources[0x0e]	202722	1			T2	29		T3	31		T5	8
valid_sources[0x0f]	158913	1			T2	19		T3	27		T5	5
valid_sources[0x10]	196286	1			T2	24		T3	22		T5	4
valid_sources[0x11]	174690	1			T1	1		T2	25		T3	39
valid_sources[0x12]	162879	1			T1	46		T2	25		T3	31
valid_sources[0x13]	174744	1			T1	75		T2	32		T3	14
valid_sources[0x14]	191755	1			T2	18		T3	19		T5	2
valid_sources[0x15]	193598	1			T2	29		T3	43		T5	3
valid_sources[0x16]	177083	1			T2	21		T3	62		T5	5
valid_sources[0x17]	155424	1			T2	21		T3	36		T5	1
valid_sources[0x18]	163629	1			T2	26		T3	37		T5	1
valid_sources[0x19]	188555	1			T2	28		T3	20		T5	3
valid_sources[0x1a]	232162	1			T2	25		T3	17		T5	5
valid_sources[0x1b]	160085	1			T2	33		T3	23		T5	1
valid_sources[0x1c]	233979	1			T1	31		T2	21		T3	27
valid_sources[0x1d]	169863	1			T1	48		T2	21		T3	54
valid_sources[0x1e]	153473	1			T1	29		T2	20		T3	38
valid_sources[0x1f]	156630	1			T1	20		T2	36		T3	34
valid_sources[0x20]	158177	1			T2	29		T3	75		T5	4
valid_sources[0x21]	163471	1			T2	55		T3	30		T5	2
valid_sources[0x22]	154043	1			T2	26		T3	24		T5	1
valid_sources[0x23]	170869	1			T1	28		T2	29		T3	55
valid_sources[0x24]	158275	1			T1	131		T2	36		T3	30
valid_sources[0x25]	154767	1			T1	50		T2	25		T3	31
valid_sources[0x26]	212405	1			T1	3		T2	21		T3	39
valid_sources[0x27]	163824	1			T1	31		T2	38		T3	34
valid_sources[0x28]	155418	1			T2	29		T3	22		T5	7
valid_sources[0x29]	168984	1			T1	37		T2	22		T3	47
valid_sources[0x2a]	172806	1			T2	34		T3	66		T5	2
valid_sources[0x2b]	158069	1			T2	25		T3	43		T5	8
valid_sources[0x2c]	302912	1			T2	29		T3	36		T5	6
valid_sources[0x2d]	172645	1			T1	2		T2	36		T3	42
valid_sources[0x2e]	267260	1			T2	35		T3	30		T5	4
valid_sources[0x2f]	157959	1			T2	41		T3	50		T5	3
valid_sources[0x30]	169822	1			T1	8		T2	21		T3	62
valid_sources[0x31]	153456	1			T2	17		T3	64		T5	7
valid_sources[0x32]	156084	1			T2	25		T3	47		T5	2
valid_sources[0x33]	184554	1			T1	15		T2	32		T3	42
valid_sources[0x34]	159002	1			T2	35		T3	38		T5	13
valid_sources[0x35]	181105	1			T1	2		T2	22		T3	41
valid_sources[0x36]	198713	1			T1	46		T2	35		T3	33
valid_sources[0x37]	162872	1			T2	30		T3	40		T5	9
valid_sources[0x38]	169753	1			T1	5		T2	24		T3	61
valid_sources[0x39]	167260	1			T2	21		T3	23		T5	8
valid_sources[0x3a]	179595	1			T1	220		T2	12		T3	46
valid_sources[0x3b]	153566	1			T1	111		T2	34		T3	21
valid_sources[0x3c]	167840	1			T2	31		T3	47		T5	8
valid_sources[0x3d]	174903	1			T1	37		T2	24		T3	66
valid_sources[0x3e]	169878	1			T1	48		T2	28		T3	26
valid_sources[0x3f]	155163	1			T1	5		T2	27		T3	42
valid_sources[0x40]	165393	1			T1	73		T2	23		T3	12
valid_sources[0x41]	154816	1			T2	25		T3	24		T5	4
valid_sources[0x42]	163176	1			T1	36		T2	42		T3	35
valid_sources[0x43]	157523	1			T2	21		T3	48		T5	4
valid_sources[0x44]	167527	1			T2	40		T3	42		T5	2
valid_sources[0x45]	158289	1			T2	20		T3	16		T5	3
valid_sources[0x46]	177467	1			T1	18		T2	31		T3	40
valid_sources[0x47]	152353	1			T1	153		T2	26		T3	45
valid_sources[0x48]	161470	1			T2	36		T3	28		T5	3
valid_sources[0x49]	299567	1			T2	33		T3	45		T5	6
valid_sources[0x4a]	187412	1			T2	24		T3	37		T5	3
valid_sources[0x4b]	156985	1			T2	45		T3	10		T5	4
valid_sources[0x4c]	198163	1			T2	20		T3	30		T5	3
valid_sources[0x4d]	186237	1			T1	98		T2	30		T3	37
valid_sources[0x4e]	160596	1			T1	18		T2	33		T3	20
valid_sources[0x4f]	188801	1			T1	46		T2	28		T3	25
valid_sources[0x50]	190515	1			T2	27		T3	40		T5	3
valid_sources[0x51]	224451	1			T1	10		T2	31		T3	65
valid_sources[0x52]	173244	1			T2	27		T3	71		T5	6
valid_sources[0x53]	162084	1			T1	13		T2	12		T3	64
valid_sources[0x54]	154034	1			T1	14		T2	32		T3	18
valid_sources[0x55]	154523	1			T2	14		T3	44		T5	4
valid_sources[0x56]	194754	1			T1	47		T2	39		T3	45
valid_sources[0x57]	162164	1			T1	32		T2	19		T3	51
valid_sources[0x58]	156083	1			T1	38		T2	42		T3	29
valid_sources[0x59]	159154	1			T1	68		T2	35		T3	44
valid_sources[0x5a]	163779	1			T1	66		T2	30		T3	34
valid_sources[0x5b]	253908	1			T2	23		T3	19		T5	8
valid_sources[0x5c]	181140	1			T2	39		T3	66		T5	6
valid_sources[0x5d]	183788	1			T1	61		T2	22		T3	63
valid_sources[0x5e]	176411	1			T1	79		T2	32		T3	36
valid_sources[0x5f]	213809	1			T1	88		T2	31		T3	44
valid_sources[0x60]	198887	1			T2	25		T3	11		T5	9
valid_sources[0x61]	159336	1			T1	33		T2	37		T3	31
valid_sources[0x62]	194272	1			T2	33		T3	31		T5	4
valid_sources[0x63]	161132	1			T2	15		T3	35		T5	9
valid_sources[0x64]	155985	1			T1	54		T2	25		T3	36
valid_sources[0x65]	166289	1			T1	32		T2	26		T3	52
valid_sources[0x66]	177147	1			T1	66		T2	32		T3	20
valid_sources[0x67]	210837	1			T1	17		T2	29		T3	46
valid_sources[0x68]	171792	1			T1	10		T2	27		T3	46
valid_sources[0x69]	165356	1			T1	26		T2	36		T3	26
valid_sources[0x6a]	182043	1			T1	30		T2	32		T3	39
valid_sources[0x6b]	156841	1			T2	32		T3	58		T5	13
valid_sources[0x6c]	154388	1			T1	18		T2	46		T3	43
valid_sources[0x6d]	161668	1			T1	2		T2	14		T3	31
valid_sources[0x6e]	154496	1			T2	36		T3	20		T5	3
valid_sources[0x6f]	156167	1			T1	39		T2	14		T3	39
valid_sources[0x70]	189573	1			T1	8		T2	11		T3	25
valid_sources[0x71]	185562	1			T1	21		T2	22		T3	53
valid_sources[0x72]	213680	1			T2	23		T3	28		T5	5
valid_sources[0x73]	167296	1			T1	66		T2	16		T3	37
valid_sources[0x74]	159543	1			T2	29		T3	39		T5	3
valid_sources[0x75]	204572	1			T1	60		T2	28		T3	18
valid_sources[0x76]	169307	1			T2	16		T3	32		T5	5
valid_sources[0x77]	159632	1			T2	30		T3	78		T5	4
valid_sources[0x78]	171389	1			T1	2		T2	44		T3	49
valid_sources[0x79]	153731	1			T1	50		T2	26		T3	39
valid_sources[0x7a]	203942	1			T2	40		T3	46		T5	3
valid_sources[0x7b]	210383	1			T2	33		T3	56		T5	6
valid_sources[0x7c]	153308	1			T1	10		T2	24		T3	37
valid_sources[0x7d]	189011	1			T1	60		T2	29		T3	38
valid_sources[0x7e]	163013	1			T2	29		T3	30		T5	6
valid_sources[0x7f]	168217	1			T1	7		T2	40		T3	16
valid_sources[0x80]	168734	1			T2	28		T3	43		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16839508

1

T1

2617

T2

3347

T3

4170

values[0x0]

all_enables

biggest_size

8464949

1

T1

1327

T2

1633

T3

2051

values[0x1]

all_enables

biggest_size

8464595

1

T1

1313

T2

1662

T3

1961

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36268

1

T4

8

T6

70

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17039	1			T6	22		T7	29		T8	19
values[0x0]	32418	1			T1	1		T2	1		T3	1
values[0x1]	33129	1			T1	1		T2	3		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43171

1

T4

11

T6

95

T10

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	396	1			T6	1		T29	10		T14	2
valid_sources[0x01]	462	1			T6	1		T48	1		T8	3
valid_sources[0x02]	263	1			T48	2		T29	4		T32	1
valid_sources[0x03]	213	1			T48	1		T29	5		T24	2
valid_sources[0x04]	348	1			T6	1		T7	1		T8	4
valid_sources[0x05]	245	1			T6	2		T29	5		T114	1
valid_sources[0x06]	261	1			T6	7		T8	1		T29	5
valid_sources[0x07]	336	1			T6	1		T29	5		T66	1
valid_sources[0x08]	522	1			T29	10		T114	3		T122	1
valid_sources[0x09]	430	1			T48	10		T29	8		T65	1
valid_sources[0x0a]	385	1			T29	6		T32	1		T24	1
valid_sources[0x0b]	252	1			T6	2		T7	4		T49	1
valid_sources[0x0c]	330	1			T6	2		T29	9		T24	1
valid_sources[0x0d]	283	1			T6	2		T29	8		T32	2
valid_sources[0x0e]	285	1			T29	10		T32	1		T114	4
valid_sources[0x0f]	362	1			T6	2		T29	8		T24	1
valid_sources[0x10]	337	1			T29	8		T32	1		T33	14
valid_sources[0x11]	389	1			T29	10		T114	4		T122	3
valid_sources[0x12]	322	1			T6	3		T29	4		T66	1
valid_sources[0x13]	284	1			T29	2		T118	9		T148	1
valid_sources[0x14]	350	1			T6	2		T29	5		T66	1
valid_sources[0x15]	260	1			T6	3		T7	1		T29	4
valid_sources[0x16]	242	1			T6	2		T29	5		T18	1
valid_sources[0x17]	265	1			T7	1		T8	5		T29	8
valid_sources[0x18]	220	1			T29	3		T24	1		T114	1
valid_sources[0x19]	536	1			T48	4		T29	8		T19	1
valid_sources[0x1a]	340	1			T6	1		T29	5		T66	1
valid_sources[0x1b]	298	1			T17	4		T48	4		T8	1
valid_sources[0x1c]	252	1			T6	2		T29	1		T66	5
valid_sources[0x1d]	275	1			T7	1		T48	3		T29	5
valid_sources[0x1e]	300	1			T7	1		T17	1		T48	1
valid_sources[0x1f]	323	1			T7	1		T8	6		T29	1
valid_sources[0x20]	294	1			T2	2		T6	3		T29	6
valid_sources[0x21]	273	1			T1	2		T6	1		T29	6
valid_sources[0x22]	296	1			T6	3		T17	5		T29	8
valid_sources[0x23]	410	1			T6	2		T48	2		T29	4
valid_sources[0x24]	288	1			T6	1		T29	10		T24	1
valid_sources[0x25]	290	1			T7	1		T8	2		T29	3
valid_sources[0x26]	243	1			T29	4		T24	1		T25	1
valid_sources[0x27]	424	1			T7	1		T17	1		T29	5
valid_sources[0x28]	404	1			T6	2		T7	1		T29	5
valid_sources[0x29]	363	1			T6	2		T7	2		T29	6
valid_sources[0x2a]	278	1			T12	1		T29	4		T24	1
valid_sources[0x2b]	277	1			T6	3		T29	14		T66	2
valid_sources[0x2c]	282	1			T6	1		T48	2		T29	6
valid_sources[0x2d]	311	1			T6	1		T48	2		T29	7
valid_sources[0x2e]	369	1			T6	1		T29	7		T19	1
valid_sources[0x2f]	421	1			T6	2		T29	3		T20	3
valid_sources[0x30]	263	1			T6	2		T7	1		T29	2
valid_sources[0x31]	353	1			T6	3		T29	7		T163	1
valid_sources[0x32]	275	1			T6	1		T29	10		T66	4
valid_sources[0x33]	279	1			T6	1		T48	4		T49	1
valid_sources[0x34]	296	1			T6	3		T29	8		T114	1
valid_sources[0x35]	306	1			T6	1		T7	2		T29	4
valid_sources[0x36]	596	1			T6	1		T7	2		T29	7
valid_sources[0x37]	222	1			T6	1		T48	5		T29	10
valid_sources[0x38]	201	1			T6	1		T48	1		T29	4
valid_sources[0x39]	288	1			T6	1		T29	6		T24	1
valid_sources[0x3a]	345	1			T6	2		T29	1		T66	1
valid_sources[0x3b]	319	1			T6	2		T7	1		T29	7
valid_sources[0x3c]	280	1			T6	1		T48	1		T29	3
valid_sources[0x3d]	341	1			T6	1		T7	1		T29	8
valid_sources[0x3e]	257	1			T7	1		T29	10		T18	1
valid_sources[0x3f]	302	1			T6	1		T29	3		T152	3
valid_sources[0x40]	227	1			T6	1		T29	1		T18	1
valid_sources[0x41]	631	1			T7	1		T48	8		T29	5
valid_sources[0x42]	281	1			T6	3		T49	2		T29	4
valid_sources[0x43]	220	1			T6	1		T29	4		T24	1
valid_sources[0x44]	336	1			T6	2		T29	3		T32	1
valid_sources[0x45]	263	1			T29	9		T122	1		T116	1
valid_sources[0x46]	230	1			T7	1		T17	4		T29	4
valid_sources[0x47]	447	1			T7	1		T8	1		T29	8
valid_sources[0x48]	229	1			T6	2		T8	5		T29	4
valid_sources[0x49]	700	1			T6	2		T29	5		T18	2
valid_sources[0x4a]	231	1			T48	4		T8	1		T29	2
valid_sources[0x4b]	269	1			T6	1		T7	1		T29	5
valid_sources[0x4c]	286	1			T6	1		T29	11		T24	2
valid_sources[0x4d]	298	1			T17	4		T29	12		T19	1
valid_sources[0x4e]	256	1			T7	1		T29	10		T32	1
valid_sources[0x4f]	324	1			T6	2		T7	2		T29	3
valid_sources[0x50]	350	1			T7	1		T48	5		T29	6
valid_sources[0x51]	401	1			T6	2		T29	4		T32	1
valid_sources[0x52]	359	1			T6	1		T29	5		T19	1
valid_sources[0x53]	427	1			T6	2		T29	4		T66	1
valid_sources[0x54]	217	1			T29	2		T24	3		T122	2
valid_sources[0x55]	341	1			T6	2		T48	2		T29	3
valid_sources[0x56]	302	1			T6	3		T8	2		T29	4
valid_sources[0x57]	316	1			T29	2		T33	27		T24	1
valid_sources[0x58]	272	1			T48	4		T29	5		T122	2
valid_sources[0x59]	266	1			T29	9		T164	2		T24	1
valid_sources[0x5a]	257	1			T6	2		T48	9		T29	2
valid_sources[0x5b]	236	1			T17	4		T29	1		T66	1
valid_sources[0x5c]	285	1			T6	4		T48	6		T29	3
valid_sources[0x5d]	274	1			T48	2		T29	4		T24	1
valid_sources[0x5e]	314	1			T7	1		T29	3		T51	1
valid_sources[0x5f]	251	1			T6	2		T12	1		T48	1
valid_sources[0x60]	263	1			T6	2		T17	2		T8	3
valid_sources[0x61]	226	1			T6	2		T29	3		T72	1
valid_sources[0x62]	255	1			T6	4		T7	1		T48	2
valid_sources[0x63]	225	1			T6	3		T48	3		T29	3
valid_sources[0x64]	502	1			T29	1		T163	1		T73	1
valid_sources[0x65]	268	1			T6	1		T48	2		T29	5
valid_sources[0x66]	318	1			T6	1		T29	4		T66	1
valid_sources[0x67]	309	1			T6	2		T29	8		T32	1
valid_sources[0x68]	235	1			T6	2		T29	4		T32	1
valid_sources[0x69]	270	1			T6	1		T7	1		T29	6
valid_sources[0x6a]	274	1			T17	1		T29	4		T32	2
valid_sources[0x6b]	320	1			T6	2		T29	7		T24	1
valid_sources[0x6c]	295	1			T6	1		T48	1		T29	7
valid_sources[0x6d]	373	1			T7	1		T29	5		T66	2
valid_sources[0x6e]	276	1			T6	1		T29	6		T66	1
valid_sources[0x6f]	354	1			T6	2		T29	6		T24	3
valid_sources[0x70]	342	1			T8	3		T29	7		T24	1
valid_sources[0x71]	252	1			T17	3		T29	4		T24	1
valid_sources[0x72]	342	1			T6	1		T29	9		T32	2
valid_sources[0x73]	312	1			T6	1		T29	6		T24	1
valid_sources[0x74]	283	1			T6	2		T8	2		T29	5
valid_sources[0x75]	286	1			T6	1		T29	4		T24	1
valid_sources[0x76]	288	1			T6	1		T29	1		T24	1
valid_sources[0x77]	277	1			T29	6		T114	2		T118	2
valid_sources[0x78]	387	1			T29	5		T82	2		T58	4
valid_sources[0x79]	336	1			T6	2		T29	7		T24	1
valid_sources[0x7a]	308	1			T6	3		T29	9		T66	1
valid_sources[0x7b]	373	1			T6	2		T29	6		T32	1
valid_sources[0x7c]	206	1			T7	1		T29	6		T32	1
valid_sources[0x7d]	410	1			T6	1		T7	2		T48	3
valid_sources[0x7e]	335	1			T6	1		T7	2		T29	10
valid_sources[0x7f]	263	1			T7	1		T29	5		T24	2
valid_sources[0x80]	239	1			T48	1		T29	5		T66	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9020

1

T6

6

T7

12

T8

7

values[0x0]

all_enables

biggest_size

15775

1

T4

4

T6

43

T11

17

values[0x1]

all_enables

biggest_size

11473

1

T4

4

T6

21

T10

1