Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11647388

1

T2

646

T3

1818

T4

875

full_word

31191949

1

T1

5257

T2

6642

T3

8182

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	42839117	1			T1	5257		T2	7288		T3	10000
auto[TlIntgErrCmd]	70	1			T52	2		T53	3		T54	4
auto[TlIntgErrData]	78	1			T52	3		T53	8		T54	9
auto[TlIntgErrBoth]	72	1			T52	5		T53	9		T54	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20002373

1

T1

2617

T2

3700

T3

5074

auto[1]

22836964

1

T1

2640

T2

3588

T3

4926

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5686385	1			T2	353		T3	904		T4	426
auto[TlIntgErrNone]	partial	auto[1]	5960807	1			T2	293		T3	914		T4	449
auto[TlIntgErrNone]	full_word	auto[0]	14315883	1			T1	2617		T2	3347		T3	4170
auto[TlIntgErrNone]	full_word	auto[1]	16876042	1			T1	2640		T2	3295		T3	4012
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T53	1		T54	1		T141	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1			T52	2		T53	2		T54	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T144	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T54	1		T146	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T52	1		T53	5		T54	5
auto[TlIntgErrData]	partial	auto[1]	34	1			T52	2		T53	1		T54	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T53	2		T54	1		T146	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T54	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T52	2		T53	3		T54	4
auto[TlIntgErrBoth]	partial	auto[1]	37	1			T52	2		T53	5		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T52	1		T53	1		T54	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T141	2		T147	1		T143	1