Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	209334	1			T6	335		T7	13		T14	35
auto[1]	3833199	1			T1	2617		T2	3671		T3	5074
auto[2]	175717	1			T6	240		T7	26		T14	34
auto[3]	3802098	1			T1	2639		T2	3550		T3	4925

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4970630	1			T1	5256		T2	6113		T3	6647
auto[1]	774756	1			T2	498		T3	1534		T6	84
auto[2]	772693	1			T2	561		T3	1444		T6	110
auto[3]	1502269	1			T2	49		T3	374		T6	7

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1744072

1

T1

5252

T2

7215

T3

9993

auto[1]

6276276

1

T1

4

T2

6

T3

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	64686	1			T6	271		T7	11		T14	32
auto[0]	auto[0]	auto[1]	6971	1			T6	25		T7	1		T14	1
auto[0]	auto[0]	auto[2]	6960	1			T6	38		T7	1		T14	1
auto[0]	auto[0]	auto[3]	3930	1			T6	1		T14	1		T24	5
auto[0]	auto[1]	auto[0]	643967	1			T1	2615		T2	3088		T3	3384
auto[0]	auto[1]	auto[1]	67887	1			T2	229		T3	783		T6	21
auto[0]	auto[1]	auto[2]	62934	1			T2	325		T3	691		T6	10
auto[0]	auto[1]	auto[3]	24244	1			T2	28		T3	212		T6	1
auto[0]	auto[2]	auto[0]	56726	1			T6	175		T7	20		T14	26
auto[0]	auto[2]	auto[1]	6151	1			T6	30		T7	4		T14	5
auto[0]	auto[2]	auto[2]	5699	1			T6	32		T7	1		T14	1
auto[0]	auto[2]	auto[3]	3115	1			T6	3		T7	1		T14	2
auto[0]	auto[3]	auto[0]	635557	1			T1	2637		T2	3020		T3	3260
auto[0]	auto[3]	auto[1]	62138	1			T2	269		T3	751		T6	8
auto[0]	auto[3]	auto[2]	67789	1			T2	235		T3	750		T6	30
auto[0]	auto[3]	auto[3]	25318	1			T2	21		T3	162		T6	2
auto[1]	auto[0]	auto[0]	4255	1			T157	816		T158	309		T159	583
auto[1]	auto[0]	auto[1]	18956	1			T157	3608		T158	1382		T159	2707
auto[1]	auto[0]	auto[2]	18925	1			T157	3526		T158	1438		T159	2676
auto[1]	auto[0]	auto[3]	84651	1			T157	15799		T95	2		T158	6301
auto[1]	auto[1]	auto[0]	1781624	1			T1	2		T2	1		T3	3
auto[1]	auto[1]	auto[1]	308301	1			T17	1		T50	939		T32	2
auto[1]	auto[1]	auto[2]	290593	1			T3	1		T10	1		T17	1
auto[1]	auto[1]	auto[3]	653649	1			T50	4361		T114	5229		T115	4254
auto[1]	auto[2]	auto[0]	3747	1			T157	722		T158	304		T159	551
auto[1]	auto[2]	auto[1]	16841	1			T157	3287		T158	1269		T159	2558
auto[1]	auto[2]	auto[2]	15083	1			T157	2982		T158	1187		T159	1905
auto[1]	auto[2]	auto[3]	68355	1			T157	13325		T158	5338		T159	8667
auto[1]	auto[3]	auto[0]	1780068	1			T1	2		T2	4		T5	1
auto[1]	auto[3]	auto[1]	287511	1			T17	1		T8	1		T50	349
auto[1]	auto[3]	auto[2]	304710	1			T2	1		T3	2		T50	957
auto[1]	auto[3]	auto[3]	639007	1			T50	4326		T71	1		T114	5281