Unified Coverage Report :: Module :: prim_ram_1p_scr

Module : prim_ram_1p_scr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55	98.18	92.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_ram_1p_scr	98.00	100.00	92.00			100.00	100.00

---

Module Instance : tb.dut.u_prim_ram_1p_scr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.00	100.00	92.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.49	100.00	92.45	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.68	100.00	92.71	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_addr_scr.u_prim_subst_perm	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_dec	100.00	100.00
gen_diffuse_data[0].u_prim_subst_perm_enc	100.00	100.00
gen_par_scr[0].u_prim_prince	100.00			100.00
u_intg_error	100.00	100.00
u_prim_ram_1p_adv	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		55	54	98.18
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	327	10	9	90.00
ALWAYS	355	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
116	1	1
118	1	1
119	1	1
125	1	1
135	1	1
138	1	1
141	1	1
145	1	1
149	1	1
157	1	1
162	1	1
183	1	1
196	1	1
225	1	1
231	1	1
257	1	1
287	1	1
312	1	1
321	1	1
327	1	1
328	1	1
330	1	1
331	1	1
334	1	1
335	1	1
336	1	1
337	1	1
339	0	1
345	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
374	1	1
375	1	1
			MISSING_ELSE
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
			MISSING_ELSE
383	1	1
384	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_ram_1p_scr

	Total	Covered	Percent
Conditions	50	46	92.00
Logical	50	46	92.00
Non-Logical	0	0
Event	0	0

 LINE       116
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T11
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T5

 LINE       138
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (macro_write | write_en_d)
             -----1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	17	100.00
TERNARY	157	2	2	100.00
TERNARY	312	3	3	100.00
TERNARY	321	2	2	100.00
IF	330	3	3	100.00
IF	355	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	157	(read_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	(macro_write) ? 
-2-:	312	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if (((!intg_error_r_q) && rvalid_q))
-2-:	334	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	374	if (read_en)
-3-:	377	if (write_en_d)
-4-:	383	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3
0	-	1	-	Covered	T1,T2,T3
0	-	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1p_scr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	761	761	0	0
DiffWidthMinimum_A	761	761	0	0
DiffWidthWithParity_A	761	761	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DiffWidthMinimum_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DiffWidthWithParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
TOTAL		54	54	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
ALWAYS	327	9	9	100.00
ALWAYS	355	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
116	1	1
118	1	1
119	1	1
125	1	1
135	1	1
138	1	1
141	1	1
145	1	1
149	1	1
157	1	1
162	1	1
183	1	1
196	1	1
225	1	1
231	1	1
257	1	1
287	1	1
312	1	1
321	1	1
327	1	1
328	1	1
330	1	1
331	1	1
334	1	1
335	1	1
336	1	1
337	1	1
339		excluded
			Exclude Annotation: VC_COV_UNR
345	1	1
			MISSING_ELSE
355	1	1
356	1	1
357	1	1
358	1	1
359	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
374	1	1
375	1	1
			MISSING_ELSE
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
			MISSING_ELSE
383	1	1
384	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Total	Covered	Percent
Conditions	50	46	92.00
Logical	50	46	92.00
Non-Logical	0	0
Event	0	0

 LINE       116
 EXPRESSION (req_i & key_valid_i)
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (gnt_o & ((~write_i)))
             --1--   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       119
 EXPRESSION (gnt_o & write_i)
             --1--   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION (read_en & (write_en_q | write_pending_q) & (addr_scr == waddr_scr_q))
             ---1---   ---------------2--------------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T11
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (addr_scr == waddr_scr_q)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (((~intg_error_w_q)) & ((~intg_error_buf)) & (read_en | write_en_q | write_pending_q))
             ---------1---------   ---------2---------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (read_en | write_en_q | write_pending_q)
                 ---1---   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T3,T5

 LINE       138
 EXPRESSION ((write_en_q | write_pending_q) & ((~read_en)) & ((~intg_error_w_q)))
             ---------------1--------------   ------2-----   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 SUB-EXPRESSION (write_en_q | write_pending_q)
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (write_en_q & read_en)
             -----1----   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (macro_write | write_en_d)
             -----1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (read_en ? addr_scr : waddr_scr_q)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 EXPRESSION (macro_write ? 1'b0 : (rw_collision ? 1'b1 : write_pending_q))
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       312
 SUB-EXPRESSION (rw_collision ? 1'b1 : write_pending_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION (write_pending_q ? wdata_scr_q : wdata_scr_d)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (((!intg_error_r_q)) && rvalid_q)
             ---------1---------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Line No.	Total	Covered	Percent
Branches		17	17	100.00
TERNARY	157	2	2	100.00
TERNARY	312	3	3	100.00
TERNARY	321	2	2	100.00
IF	330	3	3	100.00
IF	355	7	7	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv' or '../src/lowrisc_prim_ram_1p_scr_0.1/rtl/prim_ram_1p_scr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	157	(read_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	312	(macro_write) ? 
-2-:	312	(rw_collision) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	(write_pending_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if (((!intg_error_r_q) && rvalid_q))
-2-:	334	if (addr_collision_q)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	374	if (read_en)
-3-:	377	if (write_en_d)
-4-:	383	if (rw_collision)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	-	-	Covered	T1,T2,T3
0	-	1	-	Covered	T1,T2,T3
0	-	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

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Assert Coverage for Instance : tb.dut.u_prim_ram_1p_scr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DepthPow2Check_A	761	761	0	0
DiffWidthMinimum_A	761	761	0	0
DiffWidthWithParity_A	761	761	0	0

DepthPow2Check_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DiffWidthMinimum_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

DiffWidthWithParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761	761	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0