Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.68	100.00	92.71	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	208117534	23661	0	0
ctrl_regwen_rd_A	208117534	2116	0	0
exec_rd_A	208117534	2041	0	0
exec_regwen_rd_A	208117534	2110	0	0
readback_rd_A	208117534	604	0	0
readback_regwen_rd_A	208117534	403	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	23661	0	0
T18	1234	0	0	0
T29	18952	1359	0	0
T30	0	1257	0	0
T31	0	1867	0	0
T34	1939	0	0	0
T35	1957	0	0	0
T36	2909	0	0	0
T52	0	2	0	0
T53	0	11	0	0
T55	0	1226	0	0
T59	0	1592	0	0
T60	0	842	0	0
T61	0	1171	0	0
T62	0	619	0	0
T64	4899	0	0	0
T65	29236	0	0	0
T66	356659	0	0	0
T67	10621	0	0	0
T68	1955	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	2116	0	0
T30	28085	115	0	0
T31	0	152	0	0
T55	0	91	0	0
T62	0	35	0	0
T63	0	32	0	0
T84	0	65	0	0
T85	0	32	0	0
T89	0	52	0	0
T99	8928	0	0	0
T100	16000	0	0	0
T123	0	54	0	0
T124	0	28	0	0
T125	17611	0	0	0
T126	194077	0	0	0
T127	740	0	0	0
T128	443325	0	0	0
T129	1344	0	0	0
T130	504308	0	0	0
T131	199211	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	2041	0	0
T30	28085	148	0	0
T31	0	159	0	0
T55	0	102	0	0
T62	0	13	0	0
T63	0	20	0	0
T84	0	73	0	0
T85	0	26	0	0
T89	0	16	0	0
T99	8928	0	0	0
T100	16000	0	0	0
T123	0	45	0	0
T124	0	5	0	0
T125	17611	0	0	0
T126	194077	0	0	0
T127	740	0	0	0
T128	443325	0	0	0
T129	1344	0	0	0
T130	504308	0	0	0
T131	199211	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	2110	0	0
T30	28085	96	0	0
T31	0	161	0	0
T55	0	147	0	0
T62	0	45	0	0
T63	0	13	0	0
T84	0	55	0	0
T85	0	24	0	0
T89	0	20	0	0
T99	8928	0	0	0
T100	16000	0	0	0
T123	0	91	0	0
T124	0	17	0	0
T125	17611	0	0	0
T126	194077	0	0	0
T127	740	0	0	0
T128	443325	0	0	0
T129	1344	0	0	0
T130	504308	0	0	0
T131	199211	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	604	0	0
T30	28085	100	0	0
T31	0	127	0	0
T55	0	103	0	0
T62	0	27	0	0
T99	8928	0	0	0
T100	16000	0	0	0
T123	0	102	0	0
T124	0	5	0	0
T125	17611	0	0	0
T126	194077	0	0	0
T127	740	0	0	0
T128	443325	0	0	0
T129	1344	0	0	0
T130	504308	0	0	0
T131	199211	0	0	0
T132	0	9	0	0
T133	0	20	0	0
T134	0	37	0	0
T135	0	25	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208117534	403	0	0
T30	28085	82	0	0
T31	0	96	0	0
T55	0	41	0	0
T62	0	19	0	0
T63	0	4	0	0
T99	8928	0	0	0
T100	16000	0	0	0
T123	0	50	0	0
T125	17611	0	0	0
T126	194077	0	0	0
T127	740	0	0	0
T128	443325	0	0	0
T129	1344	0	0	0
T130	504308	0	0	0
T131	199211	0	0	0
T132	0	2	0	0
T133	0	22	0	0
T134	0	27	0	0
T136	0	4	0	0