Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11465334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33098688

1

T1

9103

T2

1153

T3

10000

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22228015	1			T1	4917		T2	619		T3	5002
values[0x0]	10018210	1			T1	2462		T2	329		T3	2502
values[0x1]	12317797	1			T1	2651		T2	317		T3	2496

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5713233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38850789

1

T1

9540

T2

1210

T3

10000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	157246	1			T1	38		T2	9		T10	12
valid_sources[0x01]	185364	1			T1	35		T10	8		T4	704
valid_sources[0x02]	153533	1			T1	38		T2	13		T10	6
valid_sources[0x03]	163471	1			T1	41		T2	15		T10	9
valid_sources[0x04]	195853	1			T1	32		T2	5		T10	9
valid_sources[0x05]	151630	1			T1	52		T2	8		T10	3
valid_sources[0x06]	180408	1			T1	20		T2	7		T10	2
valid_sources[0x07]	163387	1			T1	49		T10	5		T4	651
valid_sources[0x08]	233898	1			T1	54		T2	10		T10	5
valid_sources[0x09]	178565	1			T1	25		T2	13		T10	2
valid_sources[0x0a]	167605	1			T1	50		T2	1		T10	10
valid_sources[0x0b]	185030	1			T1	43		T2	3		T10	5
valid_sources[0x0c]	175123	1			T1	30		T2	5		T10	4
valid_sources[0x0d]	171774	1			T1	42		T2	7		T10	6
valid_sources[0x0e]	164207	1			T1	34		T2	3		T10	1
valid_sources[0x0f]	191349	1			T1	39		T2	9		T10	2
valid_sources[0x10]	157817	1			T1	39		T10	5		T4	616
valid_sources[0x11]	159489	1			T1	38		T2	4		T10	11
valid_sources[0x12]	173631	1			T1	32		T10	6		T4	730
valid_sources[0x13]	161185	1			T1	45		T2	10		T10	11
valid_sources[0x14]	157758	1			T1	41		T10	6		T4	625
valid_sources[0x15]	220200	1			T1	37		T2	7		T10	5
valid_sources[0x16]	173224	1			T1	37		T2	3		T10	4
valid_sources[0x17]	153154	1			T1	37		T10	3		T4	681
valid_sources[0x18]	162375	1			T1	33		T2	2		T10	6
valid_sources[0x19]	171425	1			T1	40		T2	9		T4	702
valid_sources[0x1a]	151914	1			T1	41		T2	11		T10	5
valid_sources[0x1b]	167784	1			T1	46		T2	3		T10	7
valid_sources[0x1c]	165662	1			T1	46		T2	11		T10	2
valid_sources[0x1d]	171850	1			T1	43		T2	5		T10	10
valid_sources[0x1e]	158268	1			T1	36		T10	5		T4	582
valid_sources[0x1f]	200561	1			T1	40		T2	6		T10	5
valid_sources[0x20]	160687	1			T1	29		T2	6		T10	1
valid_sources[0x21]	228000	1			T1	34		T2	10		T10	2
valid_sources[0x22]	192745	1			T1	40		T2	11		T10	3
valid_sources[0x23]	165791	1			T1	41		T2	1		T10	7
valid_sources[0x24]	188535	1			T1	38		T2	4		T10	3
valid_sources[0x25]	151367	1			T1	45		T2	9		T10	1
valid_sources[0x26]	168975	1			T1	35		T2	9		T10	8
valid_sources[0x27]	155997	1			T1	39		T2	5		T10	5
valid_sources[0x28]	171201	1			T1	51		T10	7		T4	663
valid_sources[0x29]	155425	1			T1	37		T2	7		T10	4
valid_sources[0x2a]	163612	1			T1	47		T2	6		T10	5
valid_sources[0x2b]	154367	1			T1	38		T2	12		T10	2
valid_sources[0x2c]	164693	1			T1	29		T2	4		T10	8
valid_sources[0x2d]	193139	1			T1	38		T2	7		T10	3
valid_sources[0x2e]	189624	1			T1	37		T2	3		T10	2
valid_sources[0x2f]	160296	1			T1	45		T2	10		T10	5
valid_sources[0x30]	152846	1			T1	40		T2	8		T10	7
valid_sources[0x31]	152413	1			T1	46		T2	8		T10	4
valid_sources[0x32]	156116	1			T1	33		T2	9		T10	5
valid_sources[0x33]	151933	1			T1	30		T2	2		T10	4
valid_sources[0x34]	155447	1			T1	43		T10	4		T4	623
valid_sources[0x35]	175153	1			T1	39		T2	1		T10	5
valid_sources[0x36]	197928	1			T1	37		T2	1		T10	4
valid_sources[0x37]	159298	1			T1	43		T2	2		T10	1
valid_sources[0x38]	159428	1			T1	39		T2	3		T10	5
valid_sources[0x39]	152021	1			T1	36		T2	17		T10	4
valid_sources[0x3a]	154341	1			T1	29		T2	1		T10	4
valid_sources[0x3b]	161882	1			T1	31		T2	7		T10	5
valid_sources[0x3c]	166182	1			T1	44		T10	7		T4	627
valid_sources[0x3d]	155132	1			T1	34		T2	8		T10	7
valid_sources[0x3e]	153413	1			T1	18		T2	6		T10	2
valid_sources[0x3f]	165216	1			T1	46		T2	12		T10	4
valid_sources[0x40]	168511	1			T1	46		T2	7		T10	8
valid_sources[0x41]	152896	1			T1	34		T10	5		T4	745
valid_sources[0x42]	183828	1			T1	32		T2	6		T3	5000
valid_sources[0x43]	152866	1			T1	41		T2	7		T10	7
valid_sources[0x44]	274101	1			T1	32		T2	4		T10	5
valid_sources[0x45]	196745	1			T1	33		T2	2		T10	11
valid_sources[0x46]	152734	1			T1	56		T10	2		T4	674
valid_sources[0x47]	175917	1			T1	36		T2	3		T10	1
valid_sources[0x48]	202189	1			T1	35		T2	3		T10	5
valid_sources[0x49]	190464	1			T1	42		T2	1		T10	7
valid_sources[0x4a]	205453	1			T1	34		T2	5		T10	3
valid_sources[0x4b]	178016	1			T1	49		T2	2		T10	6
valid_sources[0x4c]	204907	1			T1	39		T2	9		T10	2
valid_sources[0x4d]	155936	1			T1	37		T10	4		T4	640
valid_sources[0x4e]	175244	1			T1	48		T2	11		T10	2
valid_sources[0x4f]	187522	1			T1	43		T2	1		T10	3
valid_sources[0x50]	175422	1			T1	46		T2	2		T10	4
valid_sources[0x51]	199711	1			T1	41		T2	6		T10	4
valid_sources[0x52]	158855	1			T1	46		T10	2		T4	702
valid_sources[0x53]	185787	1			T1	44		T10	4		T4	635
valid_sources[0x54]	173307	1			T1	40		T2	6		T10	7
valid_sources[0x55]	158983	1			T1	47		T2	1		T10	2
valid_sources[0x56]	155350	1			T1	24		T10	3		T4	711
valid_sources[0x57]	152059	1			T1	49		T2	8		T10	3
valid_sources[0x58]	155094	1			T1	46		T10	6		T4	708
valid_sources[0x59]	157111	1			T1	30		T2	11		T10	6
valid_sources[0x5a]	153105	1			T1	45		T2	12		T10	9
valid_sources[0x5b]	159082	1			T1	51		T2	8		T10	7
valid_sources[0x5c]	163597	1			T1	50		T10	10		T4	593
valid_sources[0x5d]	162842	1			T1	49		T2	8		T10	8
valid_sources[0x5e]	152626	1			T1	35		T2	1		T10	5
valid_sources[0x5f]	198232	1			T1	44		T10	9		T4	686
valid_sources[0x60]	164444	1			T1	55		T10	4		T4	734
valid_sources[0x61]	195515	1			T1	37		T10	2		T4	610
valid_sources[0x62]	236296	1			T1	36		T2	3		T10	6
valid_sources[0x63]	194739	1			T1	46		T2	2		T10	3
valid_sources[0x64]	184725	1			T1	35		T2	4		T10	6
valid_sources[0x65]	230806	1			T1	34		T2	2		T10	7
valid_sources[0x66]	178990	1			T1	54		T10	3		T4	700
valid_sources[0x67]	237354	1			T1	56		T2	4		T10	1
valid_sources[0x68]	207260	1			T1	38		T2	2		T10	8
valid_sources[0x69]	187761	1			T1	45		T2	3		T10	6
valid_sources[0x6a]	158594	1			T1	44		T2	3		T10	9
valid_sources[0x6b]	215995	1			T1	37		T2	1		T10	5
valid_sources[0x6c]	162878	1			T1	42		T10	4		T4	677
valid_sources[0x6d]	244469	1			T1	44		T2	1		T10	6
valid_sources[0x6e]	207928	1			T1	41		T2	18		T10	4
valid_sources[0x6f]	154933	1			T1	32		T2	5		T10	7
valid_sources[0x70]	174516	1			T1	37		T2	7		T10	3
valid_sources[0x71]	153901	1			T1	44		T2	4		T10	7
valid_sources[0x72]	165738	1			T1	32		T2	7		T10	4
valid_sources[0x73]	204742	1			T1	44		T10	3		T4	627
valid_sources[0x74]	173784	1			T1	37		T2	34		T10	9
valid_sources[0x75]	157946	1			T1	34		T10	4		T4	619
valid_sources[0x76]	174552	1			T1	34		T2	1		T10	8
valid_sources[0x77]	151099	1			T1	30		T2	9		T10	8
valid_sources[0x78]	166271	1			T1	45		T10	5		T4	652
valid_sources[0x79]	152313	1			T1	33		T2	8		T10	6
valid_sources[0x7a]	236403	1			T1	35		T2	11		T10	1
valid_sources[0x7b]	161035	1			T1	35		T2	4		T10	5
valid_sources[0x7c]	162998	1			T1	32		T2	7		T10	4
valid_sources[0x7d]	218277	1			T1	47		T2	1		T10	2
valid_sources[0x7e]	175778	1			T1	45		T2	10		T10	4
valid_sources[0x7f]	161449	1			T1	48		T2	9		T10	5
valid_sources[0x80]	156214	1			T1	40		T10	2		T4	648

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16500011

1

T1

4471

T2

560

T3

5002

values[0x0]

all_enables

biggest_size

8297819

1

T1

2312

T2

312

T3

2502

values[0x1]

all_enables

biggest_size

8300858

1

T1

2320

T2

281

T3

2496

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34276

1

T1

2

T4

28

T5

54

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16059	1			T27	11		T7	28		T41	24
values[0x0]	32023	1			T1	2		T10	1		T4	51
values[0x1]	32827	1			T1	1		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39803	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41106

1

T1

2

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	267	1			T27	1		T80	1		T66	1
valid_sources[0x01]	322	1			T1	1		T4	2		T66	1
valid_sources[0x02]	317	1			T169	4		T175	2		T98	2
valid_sources[0x03]	301	1			T4	2		T97	1		T27	1
valid_sources[0x04]	325	1			T37	2		T16	20		T176	3
valid_sources[0x05]	286	1			T4	1		T42	1		T97	6
valid_sources[0x06]	262	1			T13	8		T132	1		T31	3
valid_sources[0x07]	288	1			T4	1		T42	2		T16	1
valid_sources[0x08]	324	1			T6	1		T16	2		T7	2
valid_sources[0x09]	231	1			T4	1		T6	1		T36	2
valid_sources[0x0a]	432	1			T4	1		T97	4		T27	1
valid_sources[0x0b]	283	1			T4	1		T97	1		T27	1
valid_sources[0x0c]	302	1			T4	3		T97	1		T132	4
valid_sources[0x0d]	322	1			T6	1		T132	3		T74	1
valid_sources[0x0e]	276	1			T16	5		T97	1		T66	1
valid_sources[0x0f]	298	1			T27	2		T169	2		T74	1
valid_sources[0x10]	353	1			T17	3		T97	1		T78	1
valid_sources[0x11]	455	1			T4	1		T27	1		T7	1
valid_sources[0x12]	220	1			T16	1		T97	1		T27	2
valid_sources[0x13]	248	1			T16	14		T97	2		T27	2
valid_sources[0x14]	504	1			T4	1		T97	3		T41	7
valid_sources[0x15]	252	1			T36	1		T77	2		T177	1
valid_sources[0x16]	261	1			T17	9		T7	1		T66	1
valid_sources[0x17]	256	1			T97	1		T30	1		T133	6
valid_sources[0x18]	215	1			T12	2		T97	1		T27	1
valid_sources[0x19]	251	1			T65	1		T132	1		T178	1
valid_sources[0x1a]	302	1			T97	3		T7	1		T179	12
valid_sources[0x1b]	339	1			T36	3		T132	2		T169	8
valid_sources[0x1c]	557	1			T4	1		T16	3		T66	2
valid_sources[0x1d]	411	1			T4	1		T15	2		T16	5
valid_sources[0x1e]	373	1			T6	1		T97	2		T66	4
valid_sources[0x1f]	243	1			T73	1		T96	5		T97	3
valid_sources[0x20]	275	1			T16	1		T97	1		T66	1
valid_sources[0x21]	274	1			T6	2		T36	5		T97	1
valid_sources[0x22]	239	1			T42	1		T16	1		T97	16
valid_sources[0x23]	326	1			T4	1		T16	2		T97	1
valid_sources[0x24]	205	1			T4	2		T36	1		T169	3
valid_sources[0x25]	338	1			T4	1		T17	3		T36	1
valid_sources[0x26]	301	1			T97	1		T67	1		T114	3
valid_sources[0x27]	445	1			T18	1		T16	2		T41	6
valid_sources[0x28]	227	1			T4	1		T30	3		T98	2
valid_sources[0x29]	263	1			T4	1		T17	3		T76	2
valid_sources[0x2a]	383	1			T97	1		T7	1		T41	5
valid_sources[0x2b]	283	1			T16	2		T97	1		T80	1
valid_sources[0x2c]	415	1			T16	1		T97	1		T7	1
valid_sources[0x2d]	264	1			T97	2		T7	2		T175	1
valid_sources[0x2e]	277	1			T4	2		T36	1		T8	2
valid_sources[0x2f]	326	1			T16	4		T97	5		T132	1
valid_sources[0x30]	382	1			T6	1		T97	2		T27	2
valid_sources[0x31]	285	1			T4	1		T16	1		T180	1
valid_sources[0x32]	448	1			T16	1		T97	1		T80	1
valid_sources[0x33]	450	1			T16	2		T27	1		T132	3
valid_sources[0x34]	244	1			T16	4		T66	1		T175	2
valid_sources[0x35]	336	1			T4	1		T36	2		T16	4
valid_sources[0x36]	367	1			T12	2		T7	1		T175	1
valid_sources[0x37]	415	1			T42	1		T97	1		T132	1
valid_sources[0x38]	249	1			T97	1		T80	1		T7	1
valid_sources[0x39]	392	1			T97	1		T27	1		T132	6
valid_sources[0x3a]	279	1			T133	5		T74	2		T31	2
valid_sources[0x3b]	252	1			T97	3		T169	4		T175	1
valid_sources[0x3c]	282	1			T17	6		T7	1		T169	1
valid_sources[0x3d]	296	1			T97	5		T78	1		T169	1
valid_sources[0x3e]	299	1			T17	2		T36	2		T97	4
valid_sources[0x3f]	319	1			T4	1		T18	1		T36	1
valid_sources[0x40]	258	1			T97	3		T30	1		T74	2
valid_sources[0x41]	181	1			T59	1		T97	1		T80	1
valid_sources[0x42]	279	1			T20	10		T7	2		T169	3
valid_sources[0x43]	249	1			T16	2		T97	1		T169	5
valid_sources[0x44]	191	1			T4	1		T80	1		T31	1
valid_sources[0x45]	336	1			T16	8		T66	2		T30	1
valid_sources[0x46]	259	1			T17	1		T97	2		T27	2
valid_sources[0x47]	362	1			T1	1		T5	15		T169	1
valid_sources[0x48]	331	1			T41	1		T169	2		T133	2
valid_sources[0x49]	246	1			T27	1		T31	1		T173	5
valid_sources[0x4a]	227	1			T16	2		T132	1		T178	1
valid_sources[0x4b]	291	1			T4	1		T176	2		T181	1
valid_sources[0x4c]	288	1			T7	1		T169	4		T74	1
valid_sources[0x4d]	297	1			T42	2		T16	4		T179	23
valid_sources[0x4e]	366	1			T97	2		T27	1		T169	6
valid_sources[0x4f]	271	1			T6	1		T63	2		T16	1
valid_sources[0x50]	298	1			T27	1		T78	1		T7	2
valid_sources[0x51]	336	1			T97	5		T176	2		T133	8
valid_sources[0x52]	298	1			T4	1		T97	3		T7	1
valid_sources[0x53]	301	1			T17	4		T97	1		T75	1
valid_sources[0x54]	235	1			T16	2		T97	2		T176	4
valid_sources[0x55]	234	1			T65	1		T9	2		T75	3
valid_sources[0x56]	401	1			T7	2		T44	1		T181	1
valid_sources[0x57]	295	1			T36	3		T97	2		T27	1
valid_sources[0x58]	329	1			T97	3		T27	1		T80	1
valid_sources[0x59]	268	1			T97	1		T27	1		T169	4
valid_sources[0x5a]	369	1			T3	1		T16	3		T97	3
valid_sources[0x5b]	236	1			T132	1		T169	2		T175	1
valid_sources[0x5c]	279	1			T4	1		T132	6		T7	1
valid_sources[0x5d]	241	1			T36	2		T42	1		T16	3
valid_sources[0x5e]	376	1			T97	1		T78	1		T66	1
valid_sources[0x5f]	294	1			T42	1		T96	3		T97	1
valid_sources[0x60]	260	1			T16	2		T27	1		T80	1
valid_sources[0x61]	240	1			T19	1		T16	6		T97	2
valid_sources[0x62]	274	1			T17	1		T42	2		T98	2
valid_sources[0x63]	299	1			T4	1		T5	52		T36	7
valid_sources[0x64]	313	1			T96	1		T97	2		T66	1
valid_sources[0x65]	216	1			T13	2		T97	2		T27	1
valid_sources[0x66]	266	1			T4	1		T16	5		T132	1
valid_sources[0x67]	298	1			T5	68		T176	14		T98	1
valid_sources[0x68]	307	1			T4	1		T97	10		T80	1
valid_sources[0x69]	347	1			T4	1		T16	5		T27	4
valid_sources[0x6a]	283	1			T16	4		T97	3		T21	7
valid_sources[0x6b]	309	1			T97	2		T27	3		T7	1
valid_sources[0x6c]	331	1			T4	1		T6	1		T80	1
valid_sources[0x6d]	375	1			T4	1		T17	2		T97	1
valid_sources[0x6e]	271	1			T97	4		T27	2		T78	1
valid_sources[0x6f]	455	1			T3	1		T27	2		T68	3
valid_sources[0x70]	287	1			T42	1		T182	1		T30	2
valid_sources[0x71]	270	1			T1	1		T6	1		T97	5
valid_sources[0x72]	359	1			T17	2		T27	1		T7	1
valid_sources[0x73]	315	1			T80	1		T7	1		T30	1
valid_sources[0x74]	242	1			T2	1		T97	1		T169	1
valid_sources[0x75]	276	1			T97	2		T132	2		T66	4
valid_sources[0x76]	256	1			T183	5		T41	1		T169	2
valid_sources[0x77]	324	1			T97	5		T74	1		T31	2
valid_sources[0x78]	205	1			T41	6		T169	6		T98	1
valid_sources[0x79]	232	1			T4	2		T97	1		T27	1
valid_sources[0x7a]	398	1			T4	1		T80	1		T7	1
valid_sources[0x7b]	235	1			T4	1		T12	1		T97	1
valid_sources[0x7c]	349	1			T42	1		T74	1		T181	1
valid_sources[0x7d]	297	1			T80	1		T21	3		T98	1
valid_sources[0x7e]	276	1			T4	1		T16	2		T66	1
valid_sources[0x7f]	292	1			T80	1		T132	3		T7	1
valid_sources[0x80]	684	1			T6	1		T28	11		T66	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8435

1

T27

8

T7

15

T41

14

values[0x0]

all_enables

biggest_size

15033

1

T1

2

T4

18

T5

39

values[0x1]

all_enables

biggest_size

10808

1

T4

10

T5

15

T6

2