Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11230835

1

T1

927

T2

112

T4

137080

full_word

30489553

1

T1

9103

T2

1153

T3

10000

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	41720198	1			T1	10030		T2	1265		T3	10000
auto[TlIntgErrCmd]	68	1			T60	8		T61	4		T62	8
auto[TlIntgErrData]	59	1			T60	9		T61	5		T158	8
auto[TlIntgErrBoth]	63	1			T60	3		T61	1		T62	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19418363

1

T1

4917

T2

619

T3

5002

auto[1]

22302025

1

T1

5113

T2

646

T3

4998

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5477332	1			T1	446		T2	59		T4	68832
auto[TlIntgErrNone]	partial	auto[1]	5753328	1			T1	481		T2	53		T4	68248
auto[TlIntgErrNone]	full_word	auto[0]	13940947	1			T1	4471		T2	560		T3	5002
auto[TlIntgErrNone]	full_word	auto[1]	16548591	1			T1	4632		T2	593		T3	4998
auto[TlIntgErrCmd]	partial	auto[0]	23	1			T60	2		T62	3		T159	1
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T60	4		T61	3		T62	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T159	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T60	2		T61	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	27	1			T60	4		T61	2		T158	4
auto[TlIntgErrData]	partial	auto[1]	26	1			T60	4		T61	1		T158	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T61	1		T161	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T60	1		T61	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T60	1		T62	1		T158	2
auto[TlIntgErrBoth]	partial	auto[1]	30	1			T60	2		T61	1		T62	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T161	2		T163	1		-	-