Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	267621	1			T5	216		T14	40		T16	564
auto[1]	3620220	1			T1	274		T2	612		T3	5000
auto[2]	222898	1			T5	215		T14	59		T16	397
auto[3]	3580089	1			T1	295		T2	644		T3	4997

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4789798	1			T1	406		T2	1048		T3	9997
auto[1]	741646	1			T1	83		T2	96		T4	7340
auto[2]	741701	1			T1	68		T2	98		T4	7265
auto[3]	1417683	1			T1	12		T2	14		T4	32434

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1721053

1

T1

569

T2

1255

T3

9984

auto[1]

5969775

1

T2

1

T3

13

T4

48608

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	69609	1			T5	183		T16	471		T31	1139
auto[0]	auto[0]	auto[1]	7025	1			T5	16		T16	40		T115	3
auto[0]	auto[0]	auto[2]	7094	1			T5	15		T16	46		T115	1
auto[0]	auto[0]	auto[3]	1966	1			T5	2		T14	40		T16	7
auto[0]	auto[1]	auto[0]	624371	1			T1	187		T2	501		T3	4994
auto[0]	auto[1]	auto[1]	70117	1			T1	67		T2	51		T4	3
auto[0]	auto[1]	auto[2]	64186	1			T1	15		T2	52		T4	5
auto[0]	auto[1]	auto[3]	28333	1			T1	5		T2	7		T4	13
auto[0]	auto[2]	auto[0]	58641	1			T5	184		T16	317		T31	990
auto[0]	auto[2]	auto[1]	5955	1			T5	14		T14	2		T16	28
auto[0]	auto[2]	auto[2]	6202	1			T5	16		T16	49		T115	1
auto[0]	auto[2]	auto[3]	1621	1			T5	1		T14	57		T16	3
auto[0]	auto[3]	auto[0]	612642	1			T1	219		T2	546		T3	4990
auto[0]	auto[3]	auto[1]	62917	1			T1	16		T2	45		T4	1
auto[0]	auto[3]	auto[2]	69700	1			T1	53		T2	46		T4	1
auto[0]	auto[3]	auto[3]	30674	1			T1	7		T2	7		T4	17
auto[1]	auto[0]	auto[0]	6150	1			T169	303		T170	581		T171	240
auto[1]	auto[0]	auto[1]	27252	1			T169	1463		T170	2540		T31	1
auto[1]	auto[0]	auto[2]	27032	1			T169	1403		T170	2514		T171	1042
auto[1]	auto[0]	auto[3]	121493	1			T115	1		T169	6453		T170	11179
auto[1]	auto[1]	auto[0]	1705792	1			T2	1		T3	6		T4	831
auto[1]	auto[1]	auto[1]	284097	1			T4	3737		T17	4333		T19	2
auto[1]	auto[1]	auto[2]	265531	1			T4	3653		T17	4889		T37	1
auto[1]	auto[1]	auto[3]	577793	1			T4	16305		T17	19984		T19	5
auto[1]	auto[2]	auto[0]	5219	1			T169	198		T170	517		T171	140
auto[1]	auto[2]	auto[1]	23062	1			T169	877		T170	2273		T31	1
auto[1]	auto[2]	auto[2]	22395	1			T169	1561		T170	2047		T171	1150
auto[1]	auto[2]	auto[3]	99803	1			T169	7018		T170	9217		T171	4927
auto[1]	auto[3]	auto[0]	1707374	1			T3	7		T4	778		T11	5
auto[1]	auto[3]	auto[1]	261221	1			T4	3599		T17	4910		T19	1
auto[1]	auto[3]	auto[2]	279561	1			T4	3606		T17	4353		T19	1
auto[1]	auto[3]	auto[3]	556000	1			T4	16099		T17	19583		T19	1