Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	210917255	26642	0	0
ctrl_regwen_rd_A	210917255	1289	0	0
exec_rd_A	210917255	1303	0	0
exec_regwen_rd_A	210917255	1342	0	0
readback_rd_A	210917255	158	0	0
readback_regwen_rd_A	210917255	167	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	26642	0	0
T38	13053	1142	0	0
T39	0	1049	0	0
T40	0	1600	0	0
T69	0	2620	0	0
T81	0	3028	0	0
T82	0	1005	0	0
T83	0	4588	0	0
T84	0	229	0	0
T85	0	427	0	0
T86	0	42	0	0
T87	14511	0	0	0
T88	251555	0	0	0
T89	7165	0	0	0
T90	1033	0	0	0
T91	88130	0	0	0
T92	174229	0	0	0
T93	8853	0	0	0
T94	268694	0	0	0
T95	531020	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	1289	0	0
T61	0	39	0	0
T70	0	8	0	0
T82	27144	34	0	0
T107	0	93	0	0
T129	0	54	0	0
T136	0	212	0	0
T137	0	9	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	41	0	0
T141	56140	0	0	0
T142	8677	0	0	0
T143	16897	0	0	0
T144	840301	0	0	0
T145	7123	0	0	0
T146	4998	0	0	0
T147	89906	0	0	0
T148	303819	0	0	0
T149	2518	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	1303	0	0
T61	0	38	0	0
T70	0	8	0	0
T82	27144	69	0	0
T107	0	91	0	0
T127	0	45	0	0
T129	0	32	0	0
T136	0	248	0	0
T137	0	9	0	0
T138	0	8	0	0
T141	56140	0	0	0
T142	8677	0	0	0
T143	16897	0	0	0
T144	840301	0	0	0
T145	7123	0	0	0
T146	4998	0	0	0
T147	89906	0	0	0
T148	303819	0	0	0
T149	2518	0	0	0
T150	0	21	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	1342	0	0
T61	0	36	0	0
T70	0	11	0	0
T82	27144	67	0	0
T107	0	81	0	0
T127	0	14	0	0
T129	0	70	0	0
T136	0	206	0	0
T137	0	7	0	0
T138	0	14	0	0
T141	56140	0	0	0
T142	8677	0	0	0
T143	16897	0	0	0
T144	840301	0	0	0
T145	7123	0	0	0
T146	4998	0	0	0
T147	89906	0	0	0
T148	303819	0	0	0
T149	2518	0	0	0
T150	0	7	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	158	0	0
T82	27144	22	0	0
T139	0	27	0	0
T141	56140	0	0	0
T142	8677	0	0	0
T143	16897	0	0	0
T144	840301	0	0	0
T145	7123	0	0	0
T146	4998	0	0	0
T147	89906	0	0	0
T148	303819	0	0	0
T149	2518	0	0	0
T151	0	22	0	0
T152	0	32	0	0
T153	0	23	0	0
T154	0	6	0	0
T155	0	12	0	0
T156	0	7	0	0
T157	0	7	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210917255	167	0	0
T82	27144	37	0	0
T137	0	8	0	0
T139	0	28	0	0
T141	56140	0	0	0
T142	8677	0	0	0
T143	16897	0	0	0
T144	840301	0	0	0
T145	7123	0	0	0
T146	4998	0	0	0
T147	89906	0	0	0
T148	303819	0	0	0
T149	2518	0	0	0
T150	0	4	0	0
T151	0	10	0	0
T152	0	27	0	0
T153	0	10	0	0
T155	0	16	0	0
T156	0	15	0	0
T158	0	3	0	0