Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11749973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34415636

1

T1

43008

T2

43008

T3

3071

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23037700	1			T1	21504		T2	21504		T3	1024
values[0x0]	10387987	1			T1	10774		T2	10700		T3	1026
values[0x1]	12739922	1			T1	10730		T2	10804		T3	1021

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5855494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40310115

1

T1

43008

T2

43008

T3

3071

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	184199	1			T1	105		T3	33		T4	22
valid_sources[0x01]	183042	1			T1	113		T3	14		T4	3
valid_sources[0x02]	176574	1			T1	186		T3	13		T4	12
valid_sources[0x03]	172750	1			T1	150		T3	5		T4	6
valid_sources[0x04]	177295	1			T1	192		T3	7		T4	7
valid_sources[0x05]	169437	1			T1	158		T3	12		T4	3
valid_sources[0x06]	167542	1			T1	141		T3	11		T4	13
valid_sources[0x07]	162396	1			T1	214		T3	10		T4	8
valid_sources[0x08]	213519	1			T1	197		T3	12		T4	4
valid_sources[0x09]	208864	1			T1	173		T3	10		T4	7
valid_sources[0x0a]	157966	1			T1	173		T3	2		T4	2
valid_sources[0x0b]	184480	1			T1	173		T3	11		T4	8
valid_sources[0x0c]	158315	1			T1	152		T3	4		T4	3
valid_sources[0x0d]	173493	1			T1	139		T3	10		T4	11
valid_sources[0x0e]	177271	1			T1	159		T3	29		T4	11
valid_sources[0x0f]	179936	1			T1	137		T3	14		T4	2
valid_sources[0x10]	201177	1			T1	188		T3	20		T4	4
valid_sources[0x11]	173237	1			T1	178		T3	2		T4	3
valid_sources[0x12]	157786	1			T1	154		T3	11		T4	14
valid_sources[0x13]	215631	1			T1	146		T3	18		T4	5
valid_sources[0x14]	191678	1			T1	141		T3	13		T4	7
valid_sources[0x15]	187401	1			T1	158		T3	8		T4	6
valid_sources[0x16]	190100	1			T1	128		T3	12		T4	3
valid_sources[0x17]	174032	1			T1	184		T3	14		T4	12
valid_sources[0x18]	199577	1			T1	138		T3	19		T4	12
valid_sources[0x19]	210998	1			T1	171		T3	4		T4	3
valid_sources[0x1a]	160786	1			T1	131		T3	3		T4	8
valid_sources[0x1b]	158068	1			T1	134		T3	17		T4	6
valid_sources[0x1c]	169964	1			T1	190		T3	8		T4	10
valid_sources[0x1d]	216876	1			T1	160		T3	7		T4	8
valid_sources[0x1e]	157334	1			T1	180		T3	18		T4	6
valid_sources[0x1f]	176507	1			T1	184		T3	15		T4	10
valid_sources[0x20]	181873	1			T1	205		T3	9		T9	1838
valid_sources[0x21]	211946	1			T1	161		T3	9		T4	3
valid_sources[0x22]	187845	1			T1	180		T3	9		T4	9
valid_sources[0x23]	164090	1			T1	108		T3	8		T4	11
valid_sources[0x24]	189868	1			T1	255		T3	11		T4	7
valid_sources[0x25]	187583	1			T1	158		T3	4		T4	3
valid_sources[0x26]	190332	1			T1	154		T3	7		T4	1
valid_sources[0x27]	169944	1			T1	238		T3	18		T4	3
valid_sources[0x28]	157987	1			T1	185		T3	12		T4	6
valid_sources[0x29]	181365	1			T1	213		T3	24		T4	7
valid_sources[0x2a]	159048	1			T1	200		T3	19		T4	13
valid_sources[0x2b]	170753	1			T1	173		T3	13		T4	10
valid_sources[0x2c]	174510	1			T1	230		T3	9		T4	8
valid_sources[0x2d]	178892	1			T1	221		T3	8		T4	9
valid_sources[0x2e]	163584	1			T1	134		T3	10		T4	2
valid_sources[0x2f]	155618	1			T1	151		T3	15		T4	9
valid_sources[0x30]	168741	1			T1	145		T3	19		T4	10
valid_sources[0x31]	254629	1			T1	236		T3	15		T4	2
valid_sources[0x32]	255705	1			T1	175		T3	10		T4	7
valid_sources[0x33]	157518	1			T1	110		T3	24		T4	8
valid_sources[0x34]	159041	1			T1	134		T3	10		T4	6
valid_sources[0x35]	160491	1			T1	108		T3	9		T4	5
valid_sources[0x36]	166705	1			T1	191		T3	11		T4	6
valid_sources[0x37]	166844	1			T1	253		T3	19		T4	3
valid_sources[0x38]	171330	1			T1	177		T3	10		T4	4
valid_sources[0x39]	176088	1			T1	154		T3	10		T4	6
valid_sources[0x3a]	184409	1			T1	202		T3	9		T4	12
valid_sources[0x3b]	195375	1			T1	158		T3	10		T4	8
valid_sources[0x3c]	192169	1			T1	140		T3	11		T4	7
valid_sources[0x3d]	191847	1			T1	168		T3	13		T4	15
valid_sources[0x3e]	157813	1			T1	206		T3	12		T4	11
valid_sources[0x3f]	192902	1			T1	231		T3	11		T4	7
valid_sources[0x40]	162618	1			T1	161		T3	6		T4	10
valid_sources[0x41]	179115	1			T1	194		T3	12		T4	7
valid_sources[0x42]	254765	1			T1	198		T3	4		T4	4
valid_sources[0x43]	196507	1			T1	140		T3	8		T4	7
valid_sources[0x44]	184303	1			T1	150		T3	11		T4	1
valid_sources[0x45]	159549	1			T1	207		T3	7		T4	13
valid_sources[0x46]	167946	1			T1	171		T3	8		T4	8
valid_sources[0x47]	158568	1			T1	150		T3	17		T4	23
valid_sources[0x48]	197185	1			T1	143		T3	11		T4	15
valid_sources[0x49]	166386	1			T1	176		T3	6		T4	7
valid_sources[0x4a]	180244	1			T1	186		T3	10		T4	9
valid_sources[0x4b]	192531	1			T1	156		T3	9		T4	14
valid_sources[0x4c]	155297	1			T1	194		T3	7		T4	4
valid_sources[0x4d]	185534	1			T1	203		T3	12		T4	10
valid_sources[0x4e]	169939	1			T1	215		T3	15		T4	8
valid_sources[0x4f]	161972	1			T1	125		T3	9		T4	9
valid_sources[0x50]	219509	1			T1	116		T2	43008		T3	9
valid_sources[0x51]	166217	1			T1	227		T3	23		T4	4
valid_sources[0x52]	155599	1			T1	147		T3	10		T4	3
valid_sources[0x53]	211851	1			T1	108		T3	15		T4	9
valid_sources[0x54]	164384	1			T1	125		T3	7		T4	7
valid_sources[0x55]	158997	1			T1	172		T3	10		T4	6
valid_sources[0x56]	178109	1			T1	220		T3	21		T4	9
valid_sources[0x57]	182955	1			T1	98		T3	12		T4	22
valid_sources[0x58]	156696	1			T1	170		T3	8		T4	4
valid_sources[0x59]	253046	1			T1	126		T3	8		T4	7
valid_sources[0x5a]	156962	1			T1	151		T3	11		T4	5
valid_sources[0x5b]	188415	1			T1	204		T3	11		T4	10
valid_sources[0x5c]	203511	1			T1	142		T3	8		T4	13
valid_sources[0x5d]	172732	1			T1	220		T3	10		T4	9
valid_sources[0x5e]	172185	1			T1	136		T3	17		T4	5
valid_sources[0x5f]	161455	1			T1	155		T3	16		T4	9
valid_sources[0x60]	197955	1			T1	119		T3	19		T4	7
valid_sources[0x61]	231725	1			T1	173		T3	5		T4	6
valid_sources[0x62]	230534	1			T1	136		T3	17		T4	6
valid_sources[0x63]	180180	1			T1	201		T3	8		T4	6
valid_sources[0x64]	186581	1			T1	197		T3	9		T4	16
valid_sources[0x65]	159875	1			T1	183		T3	23		T4	4
valid_sources[0x66]	161186	1			T1	144		T3	17		T4	4
valid_sources[0x67]	195458	1			T1	205		T3	1		T4	4
valid_sources[0x68]	175886	1			T1	138		T3	10		T4	7
valid_sources[0x69]	161628	1			T1	160		T3	19		T4	10
valid_sources[0x6a]	158153	1			T1	147		T3	5		T4	6
valid_sources[0x6b]	172835	1			T1	176		T3	16		T4	7
valid_sources[0x6c]	181922	1			T1	115		T3	5		T4	11
valid_sources[0x6d]	195172	1			T1	128		T3	9		T4	16
valid_sources[0x6e]	174205	1			T1	120		T3	12		T9	12
valid_sources[0x6f]	158962	1			T1	141		T3	5		T4	6
valid_sources[0x70]	160524	1			T1	100		T3	5		T4	9
valid_sources[0x71]	189462	1			T1	125		T3	23		T4	6
valid_sources[0x72]	190895	1			T1	144		T3	12		T4	8
valid_sources[0x73]	223371	1			T1	157		T3	22		T4	3
valid_sources[0x74]	172882	1			T1	128		T3	11		T4	9
valid_sources[0x75]	160353	1			T1	183		T3	22		T4	18
valid_sources[0x76]	172170	1			T1	212		T3	15		T4	16
valid_sources[0x77]	166059	1			T1	156		T3	5		T4	10
valid_sources[0x78]	198812	1			T1	182		T3	22		T4	17
valid_sources[0x79]	199079	1			T1	191		T3	7		T4	14
valid_sources[0x7a]	164224	1			T1	181		T3	11		T4	8
valid_sources[0x7b]	182094	1			T1	236		T3	11		T4	14
valid_sources[0x7c]	166592	1			T1	216		T3	25		T4	7
valid_sources[0x7d]	158393	1			T1	156		T3	13		T4	10
valid_sources[0x7e]	201828	1			T1	165		T3	9		T4	7
valid_sources[0x7f]	168844	1			T1	157		T3	10		T4	9
valid_sources[0x80]	206758	1			T1	144		T3	8		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17164762

1

T1

21504

T2

21504

T3

1024

values[0x0]

all_enables

biggest_size

8625142

1

T1

10774

T2

10700

T3

1026

values[0x1]

all_enables

biggest_size

8625732

1

T1

10730

T2

10804

T3

1021

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34955

1

T1

11

T2

25

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17029	1			T4	21		T7	25		T22	9
values[0x0]	32657	1			T1	12		T2	34		T3	2
values[0x1]	33529	1			T1	28		T2	49		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41984

1

T1

20

T2

31

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	299	1			T15	1		T85	1		T148	1
valid_sources[0x01]	320	1			T13	4		T157	1		T23	1
valid_sources[0x02]	324	1			T13	1		T51	2		T157	2
valid_sources[0x03]	248	1			T13	1		T113	1		T157	1
valid_sources[0x04]	296	1			T10	2		T13	5		T148	2
valid_sources[0x05]	203	1			T13	2		T113	1		T157	2
valid_sources[0x06]	218	1			T148	2		T51	3		T113	2
valid_sources[0x07]	341	1			T13	1		T113	1		T116	1
valid_sources[0x08]	277	1			T148	3		T113	2		T23	1
valid_sources[0x09]	312	1			T148	1		T157	1		T116	1
valid_sources[0x0a]	248	1			T15	4		T13	1		T148	3
valid_sources[0x0b]	360	1			T148	1		T51	1		T113	4
valid_sources[0x0c]	381	1			T2	1		T15	1		T51	2
valid_sources[0x0d]	253	1			T12	2		T44	2		T148	1
valid_sources[0x0e]	463	1			T29	1		T120	2		T51	1
valid_sources[0x0f]	472	1			T47	66		T148	1		T51	4
valid_sources[0x10]	377	1			T148	1		T51	3		T113	1
valid_sources[0x11]	291	1			T148	3		T51	3		T157	1
valid_sources[0x12]	288	1			T15	1		T148	3		T114	1
valid_sources[0x13]	358	1			T2	1		T148	1		T113	1
valid_sources[0x14]	327	1			T15	1		T148	3		T51	3
valid_sources[0x15]	363	1			T3	1		T15	1		T55	112
valid_sources[0x16]	436	1			T13	4		T148	4		T120	1
valid_sources[0x17]	213	1			T13	6		T51	1		T157	1
valid_sources[0x18]	393	1			T2	1		T113	1		T116	1
valid_sources[0x19]	284	1			T13	3		T51	5		T76	1
valid_sources[0x1a]	330	1			T12	2		T15	1		T148	3
valid_sources[0x1b]	402	1			T13	1		T157	1		T116	1
valid_sources[0x1c]	303	1			T13	1		T148	2		T113	1
valid_sources[0x1d]	394	1			T2	4		T148	3		T51	2
valid_sources[0x1e]	509	1			T15	1		T148	1		T51	2
valid_sources[0x1f]	314	1			T1	40		T15	2		T22	2
valid_sources[0x20]	264	1			T13	1		T148	1		T113	1
valid_sources[0x21]	282	1			T148	1		T16	1		T51	1
valid_sources[0x22]	192	1			T13	4		T148	3		T119	4
valid_sources[0x23]	297	1			T9	1		T120	3		T157	1
valid_sources[0x24]	362	1			T13	11		T148	1		T76	1
valid_sources[0x25]	245	1			T2	2		T113	6		T119	4
valid_sources[0x26]	291	1			T13	2		T148	2		T23	1
valid_sources[0x27]	358	1			T46	3		T86	2		T16	1
valid_sources[0x28]	264	1			T148	1		T51	1		T113	1
valid_sources[0x29]	333	1			T15	2		T17	2		T51	1
valid_sources[0x2a]	540	1			T15	1		T148	1		T158	1
valid_sources[0x2b]	557	1			T15	2		T7	26		T120	4
valid_sources[0x2c]	229	1			T13	2		T148	1		T113	1
valid_sources[0x2d]	307	1			T2	1		T15	1		T75	1
valid_sources[0x2e]	377	1			T10	1		T13	2		T148	2
valid_sources[0x2f]	306	1			T148	1		T51	3		T23	3
valid_sources[0x30]	265	1			T2	4		T15	1		T148	3
valid_sources[0x31]	478	1			T15	2		T148	1		T51	1
valid_sources[0x32]	265	1			T148	1		T113	3		T153	1
valid_sources[0x33]	274	1			T15	1		T86	2		T148	1
valid_sources[0x34]	332	1			T13	7		T157	1		T114	1
valid_sources[0x35]	324	1			T75	1		T113	3		T153	1
valid_sources[0x36]	335	1			T2	1		T148	1		T159	1
valid_sources[0x37]	241	1			T16	1		T51	2		T117	2
valid_sources[0x38]	417	1			T148	1		T113	2		T157	1
valid_sources[0x39]	247	1			T148	4		T51	3		T157	2
valid_sources[0x3a]	405	1			T148	2		T51	1		T158	1
valid_sources[0x3b]	389	1			T2	3		T13	1		T148	1
valid_sources[0x3c]	301	1			T2	1		T15	1		T86	2
valid_sources[0x3d]	263	1			T10	1		T119	1		T160	1
valid_sources[0x3e]	364	1			T15	1		T13	4		T51	1
valid_sources[0x3f]	284	1			T120	5		T113	4		T117	3
valid_sources[0x40]	284	1			T13	3		T148	4		T157	2
valid_sources[0x41]	428	1			T13	1		T51	2		T157	3
valid_sources[0x42]	325	1			T157	1		T23	2		T114	2
valid_sources[0x43]	333	1			T22	5		T148	3		T51	2
valid_sources[0x44]	443	1			T15	1		T148	1		T157	2
valid_sources[0x45]	310	1			T114	1		T116	1		T161	2
valid_sources[0x46]	306	1			T148	2		T120	1		T157	1
valid_sources[0x47]	297	1			T15	1		T148	1		T51	3
valid_sources[0x48]	361	1			T13	3		T148	1		T51	5
valid_sources[0x49]	389	1			T148	1		T51	2		T113	1
valid_sources[0x4a]	371	1			T13	1		T148	1		T113	4
valid_sources[0x4b]	294	1			T2	4		T13	1		T148	1
valid_sources[0x4c]	464	1			T15	1		T148	1		T51	2
valid_sources[0x4d]	247	1			T2	7		T148	3		T113	1
valid_sources[0x4e]	256	1			T13	1		T148	2		T113	3
valid_sources[0x4f]	365	1			T148	2		T113	2		T160	1
valid_sources[0x50]	405	1			T86	2		T51	5		T158	1
valid_sources[0x51]	323	1			T2	1		T148	1		T51	1
valid_sources[0x52]	291	1			T15	1		T13	1		T148	1
valid_sources[0x53]	290	1			T51	1		T157	4		T114	1
valid_sources[0x54]	363	1			T9	1		T4	56		T13	2
valid_sources[0x55]	311	1			T113	1		T157	1		T162	1
valid_sources[0x56]	411	1			T15	1		T13	4		T148	1
valid_sources[0x57]	380	1			T13	1		T148	2		T51	1
valid_sources[0x58]	293	1			T15	1		T51	2		T113	1
valid_sources[0x59]	362	1			T11	1		T13	1		T86	1
valid_sources[0x5a]	259	1			T148	3		T163	4		T113	1
valid_sources[0x5b]	243	1			T148	4		T157	9		T116	1
valid_sources[0x5c]	273	1			T10	1		T22	12		T13	2
valid_sources[0x5d]	327	1			T148	2		T113	2		T23	3
valid_sources[0x5e]	351	1			T85	1		T117	1		T161	1
valid_sources[0x5f]	340	1			T13	6		T148	1		T116	1
valid_sources[0x60]	180	1			T161	3		T33	1		T37	1
valid_sources[0x61]	414	1			T13	2		T148	1		T153	1
valid_sources[0x62]	254	1			T5	2		T51	1		T113	1
valid_sources[0x63]	233	1			T148	1		T51	1		T157	2
valid_sources[0x64]	222	1			T2	5		T13	1		T120	4
valid_sources[0x65]	264	1			T15	1		T148	1		T51	2
valid_sources[0x66]	515	1			T148	1		T51	1		T164	1
valid_sources[0x67]	277	1			T148	2		T51	2		T113	1
valid_sources[0x68]	235	1			T13	1		T114	3		T117	1
valid_sources[0x69]	362	1			T13	2		T51	4		T113	1
valid_sources[0x6a]	499	1			T13	4		T148	2		T114	5
valid_sources[0x6b]	371	1			T2	3		T157	3		T115	9
valid_sources[0x6c]	296	1			T148	3		T51	3		T157	1
valid_sources[0x6d]	241	1			T13	1		T148	3		T120	1
valid_sources[0x6e]	261	1			T157	1		T153	1		T119	6
valid_sources[0x6f]	301	1			T2	1		T13	1		T148	1
valid_sources[0x70]	401	1			T13	1		T51	1		T117	5
valid_sources[0x71]	336	1			T15	1		T148	1		T16	1
valid_sources[0x72]	312	1			T7	15		T153	2		T24	1
valid_sources[0x73]	218	1			T13	1		T148	1		T51	1
valid_sources[0x74]	300	1			T148	3		T51	2		T157	3
valid_sources[0x75]	314	1			T148	4		T51	1		T113	1
valid_sources[0x76]	284	1			T148	3		T157	1		T114	1
valid_sources[0x77]	317	1			T2	1		T13	4		T113	1
valid_sources[0x78]	246	1			T10	1		T15	2		T148	1
valid_sources[0x79]	319	1			T2	3		T3	2		T148	1
valid_sources[0x7a]	325	1			T2	2		T22	1		T148	1
valid_sources[0x7b]	330	1			T42	50		T7	20		T148	1
valid_sources[0x7c]	274	1			T13	1		T51	1		T116	1
valid_sources[0x7d]	307	1			T13	3		T148	2		T113	2
valid_sources[0x7e]	618	1			T13	1		T148	1		T120	3
valid_sources[0x7f]	336	1			T148	2		T51	3		T113	2
valid_sources[0x80]	279	1			T13	1		T148	3		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8911

1

T4

13

T7

13

T22

6

values[0x0]

all_enables

biggest_size

15165

1

T1

5

T2

13

T9

1

values[0x1]

all_enables

biggest_size

10879

1

T1

6

T2

12

T3

1