Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11486623

1

T9

328

T4

69

T10

4189

full_word

31572163

1

T1

43008

T2

43008

T3

3071

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	43058606	1			T1	43008		T2	43008		T3	3071
auto[TlIntgErrCmd]	67	1			T48	6		T49	5		T50	2
auto[TlIntgErrData]	52	1			T49	1		T50	7		T63	2
auto[TlIntgErrBoth]	61	1			T48	4		T49	4		T50	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19969307

1

T1

21504

T2

21504

T3

1024

auto[1]

23089479

1

T1

21504

T2

21504

T3

2047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5596972	1			T9	180		T4	43		T10	2089
auto[TlIntgErrNone]	partial	auto[1]	5889486	1			T9	148		T4	26		T10	2100
auto[TlIntgErrNone]	full_word	auto[0]	14372243	1			T1	21504		T2	21504		T3	1024
auto[TlIntgErrNone]	full_word	auto[1]	17199905	1			T1	21504		T2	21504		T3	2047
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T48	2		T49	1		T50	1
auto[TlIntgErrCmd]	partial	auto[1]	31	1			T48	4		T49	3		T50	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T144	1		T147	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T49	1		T146	1		T143	1
auto[TlIntgErrData]	partial	auto[0]	26	1			T50	5		T64	3		T146	4
auto[TlIntgErrData]	partial	auto[1]	22	1			T50	1		T63	1		T64	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T63	1		T64	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T49	1		T50	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1			T48	3		T49	3		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	28	1			T48	1		T50	1		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T63	1		T146	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T49	1		T135	1		-	-