Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	291049	1			T7	19		T13	829		T14	936
auto[1]	3836764	1			T4	350		T5	4265		T6	4587
auto[2]	246061	1			T7	10		T13	704		T14	871
auto[3]	3792650	1			T4	341		T5	4300		T6	4552

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4869065	1			T4	593		T5	5760		T6	280
auto[1]	810214	1			T4	41		T5	1232		T6	1316
auto[2]	807822	1			T4	56		T5	1288		T6	1337
auto[3]	1679423	1			T4	1		T5	285		T6	6206

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1808532

1

T4

690

T5

8556

T6

9131

auto[1]

6357992

1

T4

1

T5

9

T6

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	71890	1			T7	18		T13	679		T14	776
auto[0]	auto[0]	auto[1]	7357	1			T13	66		T14	81		T113	1
auto[0]	auto[0]	auto[2]	7433	1			T7	1		T13	76		T14	70
auto[0]	auto[0]	auto[3]	2697	1			T13	7		T14	4		T153	3
auto[0]	auto[1]	auto[0]	634831	1			T4	293		T5	2854		T6	143
auto[0]	auto[1]	auto[1]	74331	1			T4	21		T5	596		T6	664
auto[0]	auto[1]	auto[2]	68149	1			T4	35		T5	652		T6	685
auto[0]	auto[1]	auto[3]	46470	1			T4	1		T5	161		T6	3091
auto[0]	auto[2]	auto[0]	64012	1			T7	8		T13	584		T14	740
auto[0]	auto[2]	auto[1]	6554	1			T7	1		T13	51		T14	81
auto[0]	auto[2]	auto[2]	5726	1			T13	61		T14	46		T153	61
auto[0]	auto[2]	auto[3]	2049	1			T7	1		T13	8		T14	3
auto[0]	auto[3]	auto[0]	627294	1			T4	299		T5	2901		T6	136
auto[0]	auto[3]	auto[1]	67380	1			T4	20		T5	634		T6	651
auto[0]	auto[3]	auto[2]	74091	1			T4	21		T5	634		T6	652
auto[0]	auto[3]	auto[3]	48268	1			T5	124		T6	3109		T15	12
auto[1]	auto[0]	auto[0]	6800	1			T13	1		T14	4		T113	196
auto[1]	auto[0]	auto[1]	29773	1			T14	1		T113	868		T152	2309
auto[1]	auto[0]	auto[2]	29886	1			T113	846		T152	2281		T154	2487
auto[1]	auto[0]	auto[3]	135213	1			T113	3931		T152	10166		T40	3
auto[1]	auto[1]	auto[0]	1731426	1			T5	1		T6	1		T15	1
auto[1]	auto[1]	auto[1]	305981	1			T5	1		T6	1		T42	3298
auto[1]	auto[1]	auto[2]	296677	1			T15	1		T42	3596		T45	1
auto[1]	auto[1]	auto[3]	678899	1			T6	2		T42	292		T47	393
auto[1]	auto[2]	auto[0]	5961	1			T14	1		T113	128		T153	1
auto[1]	auto[2]	auto[1]	26322	1			T113	460		T152	2056		T154	2362
auto[1]	auto[2]	auto[2]	24472	1			T113	960		T152	1713		T37	1
auto[1]	auto[2]	auto[3]	110965	1			T113	4292		T152	7290		T154	9595
auto[1]	auto[3]	auto[0]	1726851	1			T4	1		T5	4		T15	2
auto[1]	auto[3]	auto[1]	292516	1			T5	1		T42	3705		T45	1
auto[1]	auto[3]	auto[2]	301388	1			T5	2		T42	3315		T45	1
auto[1]	auto[3]	auto[3]	654862	1			T6	4		T42	338		T47	386