Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	224511916	24702	0	0
ctrl_regwen_rd_A	224511916	1299	0	0
exec_rd_A	224511916	1358	0	0
exec_regwen_rd_A	224511916	1281	0	0
readback_rd_A	224511916	280	0	0
readback_regwen_rd_A	224511916	211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	24702	0	0
T25	49338	0	0	0
T26	46629	3795	0	0
T27	0	1523	0	0
T28	0	2243	0	0
T48	0	2	0	0
T49	0	6	0	0
T50	0	3	0	0
T56	0	1886	0	0
T60	0	1275	0	0
T61	0	1474	0	0
T62	0	76	0	0
T67	127946	0	0	0
T68	9003	0	0	0
T69	1220	0	0	0
T70	91288	0	0	0
T71	33113	0	0	0
T72	10932	0	0	0
T73	14068	0	0	0
T74	2242	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	1299	0	0
T28	36489	121	0	0
T56	0	156	0	0
T62	0	5	0	0
T63	0	29	0	0
T65	0	14	0	0
T88	0	43	0	0
T89	0	25	0	0
T108	0	72	0	0
T112	0	5	0	0
T124	0	27	0	0
T125	57313	0	0	0
T126	8693	0	0	0
T127	856	0	0	0
T128	305888	0	0	0
T129	14769	0	0	0
T130	49616	0	0	0
T131	2956	0	0	0
T132	860	0	0	0
T133	275576	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	1358	0	0
T28	36489	89	0	0
T56	0	113	0	0
T62	0	21	0	0
T63	0	53	0	0
T88	0	34	0	0
T89	0	21	0	0
T90	0	37	0	0
T108	0	68	0	0
T112	0	13	0	0
T124	0	21	0	0
T125	57313	0	0	0
T126	8693	0	0	0
T127	856	0	0	0
T128	305888	0	0	0
T129	14769	0	0	0
T130	49616	0	0	0
T131	2956	0	0	0
T132	860	0	0	0
T133	275576	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	1281	0	0
T28	36489	84	0	0
T56	0	157	0	0
T62	0	9	0	0
T63	0	57	0	0
T65	0	10	0	0
T88	0	31	0	0
T89	0	14	0	0
T108	0	30	0	0
T112	0	16	0	0
T124	0	39	0	0
T125	57313	0	0	0
T126	8693	0	0	0
T127	856	0	0	0
T128	305888	0	0	0
T129	14769	0	0	0
T130	49616	0	0	0
T131	2956	0	0	0
T132	860	0	0	0
T133	275576	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	280	0	0
T28	36489	86	0	0
T56	0	109	0	0
T63	0	1	0	0
T65	0	14	0	0
T125	57313	0	0	0
T126	8693	0	0	0
T127	856	0	0	0
T128	305888	0	0	0
T129	14769	0	0	0
T130	49616	0	0	0
T131	2956	0	0	0
T132	860	0	0	0
T133	275576	0	0	0
T134	0	12	0	0
T135	0	6	0	0
T136	0	6	0	0
T137	0	5	0	0
T138	0	25	0	0
T139	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224511916	211	0	0
T28	36489	68	0	0
T56	0	84	0	0
T125	57313	0	0	0
T126	8693	0	0	0
T127	856	0	0	0
T128	305888	0	0	0
T129	14769	0	0	0
T130	49616	0	0	0
T131	2956	0	0	0
T132	860	0	0	0
T133	275576	0	0	0
T134	0	19	0	0
T135	0	3	0	0
T136	0	3	0	0
T137	0	9	0	0
T138	0	12	0	0
T139	0	3	0	0
T140	0	10	0	0