Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11460938	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31805996

1

T1

4902

T2

8650

T3

51200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21577443	1			T1	2469		T2	4322		T3	25600
values[0x0]	9702006	1			T1	1240		T2	2180		T3	12782
values[0x1]	11987485	1			T1	1193		T2	2148		T3	12818

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5712545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37554389

1

T1

4902

T2

8650

T3

51200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	150509	1			T1	22		T2	60		T3	189
valid_sources[0x01]	156095	1			T1	10		T2	50		T3	210
valid_sources[0x02]	151639	1			T1	35		T2	32		T3	185
valid_sources[0x03]	158511	1			T1	10		T2	11		T3	202
valid_sources[0x04]	175800	1			T1	20		T2	30		T3	228
valid_sources[0x05]	154895	1			T1	25		T2	32		T3	213
valid_sources[0x06]	169427	1			T1	14		T2	14		T3	206
valid_sources[0x07]	180272	1			T1	17		T2	47		T3	227
valid_sources[0x08]	225617	1			T1	21		T2	19		T3	181
valid_sources[0x09]	189062	1			T1	13		T2	52		T3	182
valid_sources[0x0a]	166009	1			T1	30		T2	29		T3	181
valid_sources[0x0b]	153902	1			T1	31		T2	32		T3	194
valid_sources[0x0c]	169675	1			T1	19		T2	51		T3	227
valid_sources[0x0d]	163439	1			T1	22		T2	42		T3	240
valid_sources[0x0e]	162965	1			T1	17		T2	28		T3	183
valid_sources[0x0f]	151193	1			T1	14		T2	58		T3	217
valid_sources[0x10]	150864	1			T1	47		T2	19		T3	220
valid_sources[0x11]	157682	1			T1	8		T2	11		T3	182
valid_sources[0x12]	209835	1			T1	9		T2	37		T3	186
valid_sources[0x13]	172803	1			T1	37		T2	48		T3	209
valid_sources[0x14]	164431	1			T1	21		T2	43		T3	217
valid_sources[0x15]	151928	1			T1	10		T2	36		T3	190
valid_sources[0x16]	309235	1			T1	23		T2	7		T3	186
valid_sources[0x17]	183952	1			T1	12		T2	27		T3	202
valid_sources[0x18]	191085	1			T1	18		T2	65		T3	203
valid_sources[0x19]	150322	1			T1	18		T2	20		T3	206
valid_sources[0x1a]	150121	1			T1	17		T2	54		T3	201
valid_sources[0x1b]	207226	1			T1	19		T2	71		T3	164
valid_sources[0x1c]	191462	1			T1	13		T2	47		T3	203
valid_sources[0x1d]	153059	1			T1	24		T2	34		T3	186
valid_sources[0x1e]	225916	1			T1	43		T2	47		T3	177
valid_sources[0x1f]	182466	1			T1	12		T2	28		T3	197
valid_sources[0x20]	165932	1			T1	17		T2	41		T3	185
valid_sources[0x21]	160089	1			T1	19		T2	33		T3	164
valid_sources[0x22]	167892	1			T1	21		T2	61		T3	185
valid_sources[0x23]	157703	1			T1	9		T2	11		T3	183
valid_sources[0x24]	163246	1			T1	17		T2	34		T3	226
valid_sources[0x25]	199268	1			T1	22		T2	12		T3	172
valid_sources[0x26]	153498	1			T1	20		T2	13		T3	192
valid_sources[0x27]	161369	1			T1	19		T2	32		T3	164
valid_sources[0x28]	205347	1			T1	15		T2	36		T3	190
valid_sources[0x29]	175758	1			T1	14		T2	13		T3	198
valid_sources[0x2a]	165703	1			T1	16		T2	46		T3	212
valid_sources[0x2b]	150008	1			T1	20		T2	25		T3	207
valid_sources[0x2c]	150632	1			T1	8		T2	69		T3	192
valid_sources[0x2d]	151762	1			T1	13		T2	20		T3	198
valid_sources[0x2e]	149719	1			T1	12		T2	31		T3	198
valid_sources[0x2f]	150172	1			T1	13		T2	42		T3	186
valid_sources[0x30]	178120	1			T1	12		T2	26		T3	216
valid_sources[0x31]	259778	1			T1	19		T2	69		T3	198
valid_sources[0x32]	156966	1			T1	19		T2	24		T3	214
valid_sources[0x33]	170661	1			T1	22		T2	22		T3	204
valid_sources[0x34]	225702	1			T1	18		T2	39		T3	209
valid_sources[0x35]	153034	1			T1	21		T2	15		T3	208
valid_sources[0x36]	178246	1			T1	16		T2	45		T3	208
valid_sources[0x37]	155512	1			T1	18		T2	27		T3	218
valid_sources[0x38]	150516	1			T1	28		T2	77		T3	170
valid_sources[0x39]	156401	1			T1	13		T2	71		T3	246
valid_sources[0x3a]	149153	1			T1	21		T2	28		T3	180
valid_sources[0x3b]	169945	1			T1	18		T2	34		T3	184
valid_sources[0x3c]	160872	1			T1	32		T2	5		T3	202
valid_sources[0x3d]	153891	1			T1	15		T2	43		T3	208
valid_sources[0x3e]	198374	1			T1	23		T2	8		T3	195
valid_sources[0x3f]	152839	1			T1	19		T2	14		T3	188
valid_sources[0x40]	159686	1			T1	8		T2	24		T3	191
valid_sources[0x41]	174551	1			T1	25		T2	16		T3	193
valid_sources[0x42]	155322	1			T1	26		T2	82		T3	198
valid_sources[0x43]	152314	1			T1	5		T2	52		T3	213
valid_sources[0x44]	161990	1			T1	17		T2	10		T3	207
valid_sources[0x45]	155739	1			T1	22		T2	22		T3	218
valid_sources[0x46]	150738	1			T1	28		T2	33		T3	226
valid_sources[0x47]	175575	1			T1	21		T2	44		T3	232
valid_sources[0x48]	156533	1			T1	14		T2	27		T3	196
valid_sources[0x49]	148747	1			T1	8		T2	23		T3	180
valid_sources[0x4a]	149936	1			T1	13		T2	21		T3	190
valid_sources[0x4b]	160941	1			T1	26		T2	2		T3	201
valid_sources[0x4c]	163287	1			T1	19		T2	14		T3	199
valid_sources[0x4d]	150171	1			T1	21		T2	31		T3	224
valid_sources[0x4e]	200414	1			T1	11		T2	18		T3	184
valid_sources[0x4f]	163949	1			T1	32		T2	22		T3	250
valid_sources[0x50]	152717	1			T1	24		T2	32		T3	201
valid_sources[0x51]	177742	1			T1	10		T2	74		T3	190
valid_sources[0x52]	185111	1			T1	35		T2	65		T3	201
valid_sources[0x53]	151587	1			T1	24		T2	83		T3	197
valid_sources[0x54]	156534	1			T1	32		T2	24		T3	194
valid_sources[0x55]	152189	1			T1	13		T2	41		T3	198
valid_sources[0x56]	184945	1			T1	19		T2	24		T3	226
valid_sources[0x57]	164077	1			T1	37		T2	21		T3	180
valid_sources[0x58]	156007	1			T1	17		T2	47		T3	199
valid_sources[0x59]	158671	1			T1	19		T2	49		T3	195
valid_sources[0x5a]	176691	1			T1	11		T2	80		T3	189
valid_sources[0x5b]	165751	1			T1	9		T2	9		T3	212
valid_sources[0x5c]	152524	1			T1	23		T2	13		T3	209
valid_sources[0x5d]	168447	1			T1	8		T2	41		T3	226
valid_sources[0x5e]	175176	1			T1	18		T2	8		T3	199
valid_sources[0x5f]	161424	1			T1	21		T2	29		T3	199
valid_sources[0x60]	149050	1			T1	8		T2	13		T3	197
valid_sources[0x61]	173918	1			T1	21		T2	25		T3	224
valid_sources[0x62]	166533	1			T1	21		T2	27		T3	224
valid_sources[0x63]	149526	1			T1	23		T2	22		T3	231
valid_sources[0x64]	164849	1			T1	13		T2	78		T3	182
valid_sources[0x65]	155186	1			T1	16		T2	20		T3	229
valid_sources[0x66]	208737	1			T1	25		T2	17		T3	207
valid_sources[0x67]	153881	1			T1	16		T2	40		T3	196
valid_sources[0x68]	158734	1			T1	21		T2	118		T3	219
valid_sources[0x69]	150302	1			T1	16		T2	17		T3	166
valid_sources[0x6a]	149207	1			T1	12		T2	47		T3	222
valid_sources[0x6b]	164103	1			T1	34		T2	14		T3	204
valid_sources[0x6c]	152187	1			T1	13		T2	4		T3	168
valid_sources[0x6d]	157356	1			T1	17		T2	57		T3	208
valid_sources[0x6e]	152934	1			T1	9		T2	70		T3	224
valid_sources[0x6f]	180625	1			T1	10		T2	43		T3	167
valid_sources[0x70]	172185	1			T1	14		T2	40		T3	192
valid_sources[0x71]	160023	1			T1	19		T2	39		T3	198
valid_sources[0x72]	158389	1			T1	20		T2	56		T3	206
valid_sources[0x73]	194242	1			T1	21		T2	44		T3	209
valid_sources[0x74]	149847	1			T1	16		T2	17		T3	188
valid_sources[0x75]	193688	1			T1	30		T2	31		T3	172
valid_sources[0x76]	159923	1			T1	27		T2	4		T3	256
valid_sources[0x77]	180860	1			T1	14		T2	20		T3	196
valid_sources[0x78]	152672	1			T1	16		T2	20		T3	214
valid_sources[0x79]	202985	1			T1	21		T2	15		T3	174
valid_sources[0x7a]	161516	1			T1	16		T2	28		T3	193
valid_sources[0x7b]	160980	1			T1	19		T2	24		T3	201
valid_sources[0x7c]	192912	1			T1	15		T2	45		T3	223
valid_sources[0x7d]	230768	1			T1	13		T2	25		T3	214
valid_sources[0x7e]	155632	1			T1	9		T2	10		T3	231
valid_sources[0x7f]	157100	1			T1	10		T2	50		T3	217
valid_sources[0x80]	150462	1			T1	15		T2	20		T3	188

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15852294

1

T1

2469

T2

4322

T3

25600

values[0x0]

all_enables

biggest_size

7979981

1

T1

1240

T2

2180

T3

12782

values[0x1]

all_enables

biggest_size

7973721

1

T1

1193

T2

2148

T3

12818

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34348

1

T3

31

T4

1

T9

597

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16886	1			T9	183		T6	32		T7	22
values[0x0]	30896	1			T2	1		T3	66		T5	1
values[0x1]	31571	1			T1	2		T2	1		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41137

1

T3

41

T4

1

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	640	1			T9	10		T116	1		T157	1
valid_sources[0x01]	209	1			T14	1		T125	1		T114	1
valid_sources[0x02]	277	1			T11	1		T157	3		T45	2
valid_sources[0x03]	425	1			T125	1		T25	2		T77	2
valid_sources[0x04]	237	1			T114	2		T30	4		T158	1
valid_sources[0x05]	220	1			T25	1		T31	1		T113	6
valid_sources[0x06]	207	1			T116	1		T25	1		T66	1
valid_sources[0x07]	338	1			T11	1		T68	1		T116	3
valid_sources[0x08]	308	1			T116	1		T25	2		T157	1
valid_sources[0x09]	248	1			T14	24		T116	1		T24	2
valid_sources[0x0a]	227	1			T25	4		T157	2		T45	1
valid_sources[0x0b]	239	1			T25	1		T157	1		T45	2
valid_sources[0x0c]	228	1			T11	1		T15	1		T14	12
valid_sources[0x0d]	254	1			T6	2		T116	1		T125	1
valid_sources[0x0e]	235	1			T7	1		T69	1		T30	3
valid_sources[0x0f]	290	1			T50	1		T14	71		T116	1
valid_sources[0x10]	318	1			T15	1		T125	1		T157	1
valid_sources[0x11]	630	1			T8	58		T25	1		T159	1
valid_sources[0x12]	372	1			T27	1		T160	1		T148	1
valid_sources[0x13]	285	1			T17	1		T116	1		T125	1
valid_sources[0x14]	413	1			T6	3		T50	1		T25	1
valid_sources[0x15]	216	1			T15	1		T50	1		T7	3
valid_sources[0x16]	291	1			T9	1		T25	2		T47	1
valid_sources[0x17]	303	1			T116	1		T157	1		T114	1
valid_sources[0x18]	250	1			T116	1		T159	3		T72	2
valid_sources[0x19]	272	1			T6	4		T25	1		T114	2
valid_sources[0x1a]	328	1			T9	1		T11	2		T24	3
valid_sources[0x1b]	225	1			T11	3		T25	4		T30	8
valid_sources[0x1c]	236	1			T15	1		T50	1		T116	2
valid_sources[0x1d]	262	1			T11	1		T50	2		T14	3
valid_sources[0x1e]	218	1			T25	1		T157	1		T114	1
valid_sources[0x1f]	331	1			T9	22		T6	6		T15	2
valid_sources[0x20]	253	1			T7	1		T125	2		T26	5
valid_sources[0x21]	236	1			T117	3		T114	3		T69	2
valid_sources[0x22]	314	1			T10	3		T25	1		T76	3
valid_sources[0x23]	240	1			T9	3		T24	3		T125	1
valid_sources[0x24]	471	1			T7	1		T114	1		T69	1
valid_sources[0x25]	261	1			T7	1		T14	8		T159	2
valid_sources[0x26]	307	1			T14	13		T24	1		T25	1
valid_sources[0x27]	307	1			T114	1		T66	4		T160	1
valid_sources[0x28]	470	1			T9	101		T24	1		T159	1
valid_sources[0x29]	273	1			T11	1		T24	3		T25	1
valid_sources[0x2a]	186	1			T7	2		T14	1		T114	1
valid_sources[0x2b]	320	1			T116	1		T157	1		T114	1
valid_sources[0x2c]	346	1			T25	2		T67	1		T30	12
valid_sources[0x2d]	402	1			T25	1		T114	6		T69	1
valid_sources[0x2e]	216	1			T15	1		T146	7		T161	2
valid_sources[0x2f]	313	1			T7	1		T125	1		T157	1
valid_sources[0x30]	265	1			T14	1		T125	1		T114	6
valid_sources[0x31]	686	1			T50	1		T14	8		T125	1
valid_sources[0x32]	239	1			T25	2		T157	1		T66	3
valid_sources[0x33]	216	1			T11	2		T15	1		T114	1
valid_sources[0x34]	258	1			T7	3		T24	3		T125	1
valid_sources[0x35]	264	1			T25	1		T157	5		T69	1
valid_sources[0x36]	175	1			T15	1		T50	1		T25	1
valid_sources[0x37]	273	1			T116	1		T24	10		T25	1
valid_sources[0x38]	292	1			T6	5		T114	3		T69	1
valid_sources[0x39]	369	1			T11	1		T25	2		T114	2
valid_sources[0x3a]	446	1			T9	3		T69	3		T67	3
valid_sources[0x3b]	242	1			T6	11		T113	10		T69	1
valid_sources[0x3c]	363	1			T10	5		T14	3		T51	3
valid_sources[0x3d]	258	1			T9	19		T7	1		T116	1
valid_sources[0x3e]	248	1			T50	1		T25	1		T157	1
valid_sources[0x3f]	270	1			T116	2		T25	1		T45	2
valid_sources[0x40]	273	1			T11	1		T24	3		T25	3
valid_sources[0x41]	333	1			T24	1		T125	1		T69	1
valid_sources[0x42]	289	1			T11	1		T7	2		T24	5
valid_sources[0x43]	515	1			T11	1		T114	2		T72	6
valid_sources[0x44]	251	1			T11	1		T6	3		T116	1
valid_sources[0x45]	305	1			T9	34		T11	1		T6	1
valid_sources[0x46]	300	1			T113	1		T114	2		T69	1
valid_sources[0x47]	251	1			T15	1		T116	1		T25	1
valid_sources[0x48]	383	1			T11	1		T50	1		T114	1
valid_sources[0x49]	210	1			T11	1		T114	1		T66	1
valid_sources[0x4a]	288	1			T9	2		T50	1		T47	1
valid_sources[0x4b]	255	1			T25	2		T157	1		T45	1
valid_sources[0x4c]	386	1			T24	3		T157	2		T77	1
valid_sources[0x4d]	361	1			T50	1		T14	109		T114	3
valid_sources[0x4e]	289	1			T9	2		T116	1		T25	1
valid_sources[0x4f]	319	1			T15	1		T50	1		T24	3
valid_sources[0x50]	289	1			T11	3		T24	3		T25	1
valid_sources[0x51]	209	1			T2	1		T15	2		T50	2
valid_sources[0x52]	221	1			T11	1		T7	1		T25	1
valid_sources[0x53]	262	1			T125	2		T159	1		T114	4
valid_sources[0x54]	218	1			T14	3		T116	1		T24	4
valid_sources[0x55]	349	1			T9	78		T6	3		T17	1
valid_sources[0x56]	544	1			T18	12		T25	2		T67	1
valid_sources[0x57]	276	1			T68	1		T25	1		T157	3
valid_sources[0x58]	256	1			T7	1		T157	1		T45	3
valid_sources[0x59]	203	1			T15	1		T25	1		T113	2
valid_sources[0x5a]	393	1			T50	1		T7	2		T25	1
valid_sources[0x5b]	228	1			T7	3		T14	2		T125	1
valid_sources[0x5c]	266	1			T24	1		T25	2		T114	1
valid_sources[0x5d]	351	1			T50	1		T25	1		T114	6
valid_sources[0x5e]	236	1			T15	2		T25	1		T114	3
valid_sources[0x5f]	226	1			T50	1		T25	2		T157	1
valid_sources[0x60]	326	1			T9	3		T15	1		T50	1
valid_sources[0x61]	181	1			T25	1		T159	1		T157	2
valid_sources[0x62]	427	1			T15	2		T48	52		T50	1
valid_sources[0x63]	287	1			T14	1		T25	1		T157	1
valid_sources[0x64]	246	1			T24	1		T113	9		T114	1
valid_sources[0x65]	252	1			T113	3		T114	1		T72	1
valid_sources[0x66]	325	1			T11	1		T124	74		T25	1
valid_sources[0x67]	464	1			T157	2		T45	2		T66	2
valid_sources[0x68]	310	1			T7	1		T157	1		T114	3
valid_sources[0x69]	239	1			T157	1		T72	1		T162	1
valid_sources[0x6a]	248	1			T50	1		T125	1		T157	1
valid_sources[0x6b]	258	1			T125	1		T25	3		T113	4
valid_sources[0x6c]	223	1			T11	2		T159	1		T72	2
valid_sources[0x6d]	391	1			T9	19		T14	4		T157	1
valid_sources[0x6e]	292	1			T16	1		T24	4		T25	3
valid_sources[0x6f]	690	1			T15	1		T50	1		T125	1
valid_sources[0x70]	225	1			T14	1		T116	1		T159	1
valid_sources[0x71]	240	1			T11	1		T50	1		T24	4
valid_sources[0x72]	265	1			T25	1		T29	7		T77	1
valid_sources[0x73]	432	1			T50	1		T25	2		T157	1
valid_sources[0x74]	304	1			T125	3		T157	1		T45	1
valid_sources[0x75]	336	1			T11	2		T24	1		T113	3
valid_sources[0x76]	509	1			T6	4		T114	2		T160	1
valid_sources[0x77]	212	1			T114	1		T77	1		T148	3
valid_sources[0x78]	349	1			T157	1		T114	2		T74	5
valid_sources[0x79]	259	1			T15	1		T24	13		T125	1
valid_sources[0x7a]	646	1			T13	2		T125	1		T69	1
valid_sources[0x7b]	231	1			T50	1		T66	5		T147	4
valid_sources[0x7c]	317	1			T157	1		T69	1		T30	4
valid_sources[0x7d]	360	1			T9	107		T15	1		T17	1
valid_sources[0x7e]	265	1			T157	3		T114	1		T69	3
valid_sources[0x7f]	558	1			T4	1		T50	2		T24	1
valid_sources[0x80]	240	1			T11	1		T24	2		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8751

1

T9

165

T6

18

T7

13

values[0x0]

all_enables

biggest_size

14894

1

T3

21

T9

198

T10

6

values[0x1]

all_enables

biggest_size

10703

1

T3

10

T4

1

T9

234