Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11243391

1

T4

1745

T5

1906

T9

1221

full_word

29357859

1

T1

4902

T2

8650

T3

51200

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	40601010	1			T1	4902		T2	8650		T3	51200
auto[TlIntgErrCmd]	86	1			T54	5		T55	3		T56	5
auto[TlIntgErrData]	72	1			T54	3		T55	9		T56	5
auto[TlIntgErrBoth]	82	1			T54	2		T55	8		T56	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18938915

1

T1

2469

T2

4322

T3

25600

auto[1]

21662335

1

T1

2433

T2

4328

T3

25600

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5490151	1			T4	865		T5	869		T9	409
auto[TlIntgErrNone]	partial	auto[1]	5753024	1			T4	880		T5	1037		T9	812
auto[TlIntgErrNone]	full_word	auto[0]	13448641	1			T1	2469		T2	4322		T3	25600
auto[TlIntgErrNone]	full_word	auto[1]	15909194	1			T1	2433		T2	4328		T3	25600
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T54	1		T55	3		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T54	3		T56	3		T134	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T134	1		T135	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T54	1		T137	2		T135	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T54	3		T55	6		T56	1
auto[TlIntgErrData]	partial	auto[1]	31	1			T55	3		T56	2		T134	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T56	2		T134	1		T138	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T55	4		T56	3		T134	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T54	2		T55	1		T56	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T55	2		T135	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T55	1		T56	1		T134	1