Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	261480	1			T5	111		T7	9		T14	6
auto[1]	3787064	1			T1	2468		T2	4322		T4	5014
auto[2]	218993	1			T5	112		T7	5		T14	4
auto[3]	3747703	1			T1	2432		T2	4327		T4	4983

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4516843	1			T1	4900		T2	8649		T4	6798
auto[1]	813919	1			T4	1454		T5	12		T9	346
auto[2]	812365	1			T4	1438		T5	32		T9	336
auto[3]	1872113	1			T4	307		T5	527		T9	33

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782530

1

T1

4895

T2

8640

T4

9991

auto[1]

6232710

1

T1

5

T2

9

T4

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	49324	1			T7	5		T14	5		T29	5
auto[0]	auto[0]	auto[1]	5296	1			T5	1		T7	2		T47	1
auto[0]	auto[0]	auto[2]	5226	1			T7	1		T14	1		T47	1
auto[0]	auto[0]	auto[3]	2270	1			T5	110		T7	1		T47	52
auto[0]	auto[1]	auto[0]	668650	1			T1	2463		T2	4320		T4	3425
auto[0]	auto[1]	auto[1]	72420	1			T4	721		T9	182		T6	46
auto[0]	auto[1]	auto[2]	67654	1			T4	706		T5	6		T9	172
auto[0]	auto[1]	auto[3]	27049	1			T4	159		T5	132		T9	18
auto[0]	auto[2]	auto[0]	43400	1			T7	5		T14	3		T29	8
auto[0]	auto[2]	auto[1]	4572	1			T5	9		T47	2		T26	31
auto[0]	auto[2]	auto[2]	4495	1			T14	1		T47	1		T26	21
auto[0]	auto[2]	auto[3]	1980	1			T5	103		T47	43		T146	8
auto[0]	auto[3]	auto[0]	662066	1			T1	2432		T2	4320		T4	3368
auto[0]	auto[3]	auto[1]	66886	1			T4	732		T5	2		T9	162
auto[0]	auto[3]	auto[2]	71711	1			T4	732		T5	26		T9	164
auto[0]	auto[3]	auto[3]	29531	1			T4	148		T5	182		T9	15
auto[1]	auto[0]	auto[0]	6576	1			T146	1		T152	11		T153	1
auto[1]	auto[0]	auto[1]	29734	1			T146	1		T152	1		T153	1
auto[1]	auto[0]	auto[2]	29427	1			T150	1783		T151	741		T44	1
auto[1]	auto[0]	auto[3]	133627	1			T154	1		T150	7880		T151	3260
auto[1]	auto[1]	auto[0]	1541122	1			T1	5		T2	2		T4	2
auto[1]	auto[1]	auto[1]	314409	1			T4	1		T9	1		T11	3666
auto[1]	auto[1]	auto[2]	300050	1			T11	3769		T15	5202		T16	1
auto[1]	auto[1]	auto[3]	795710	1			T11	16743		T15	529		T48	191
auto[1]	auto[2]	auto[0]	5677	1			T146	1		T152	9		T155	2
auto[1]	auto[2]	auto[1]	25643	1			T26	1		T150	1613		T151	439
auto[1]	auto[2]	auto[2]	24259	1			T152	2		T150	1203		T151	719
auto[1]	auto[2]	auto[3]	108967	1			T153	1		T150	5580		T151	3448
auto[1]	auto[3]	auto[0]	1540028	1			T2	7		T4	3		T9	1
auto[1]	auto[3]	auto[1]	294959	1			T9	1		T11	3587		T15	5100
auto[1]	auto[3]	auto[2]	309543	1			T11	3614		T15	5140		T16	1
auto[1]	auto[3]	auto[3]	772979	1			T11	16522		T15	501		T48	174