Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	198367697	27333	0	0
ctrl_regwen_rd_A	198367697	1773	0	0
exec_rd_A	198367697	1872	0	0
exec_regwen_rd_A	198367697	1831	0	0
readback_rd_A	198367697	214	0	0
readback_regwen_rd_A	198367697	259	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	27333	0	0
T6	38385	0	0	0
T9	16595	671	0	0
T10	102886	0	0	0
T11	404938	0	0	0
T12	56915	0	0	0
T13	9761	0	0	0
T14	0	786	0	0
T15	234591	0	0	0
T16	14679	0	0	0
T17	1500	0	0	0
T30	0	697	0	0
T48	347226	0	0	0
T52	0	4521	0	0
T53	0	1457	0	0
T61	0	816	0	0
T62	0	1177	0	0
T63	0	1000	0	0
T64	0	3281	0	0
T65	0	378	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	1773	0	0
T8	33941	0	0	0
T14	24584	106	0	0
T18	1231	0	0	0
T24	496537	0	0	0
T51	9301	0	0	0
T54	0	33	0	0
T58	0	37	0	0
T59	0	6	0	0
T61	0	42	0	0
T88	0	58	0	0
T102	0	11	0	0
T111	0	3	0	0
T116	240617	0	0	0
T117	7352	0	0	0
T121	0	11	0	0
T122	0	2	0	0
T123	9970	0	0	0
T124	346004	0	0	0
T125	115346	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	1872	0	0
T8	33941	0	0	0
T14	24584	68	0	0
T18	1231	0	0	0
T24	496537	0	0	0
T51	9301	0	0	0
T54	0	44	0	0
T58	0	61	0	0
T61	0	55	0	0
T88	0	34	0	0
T102	0	8	0	0
T111	0	7	0	0
T116	240617	0	0	0
T117	7352	0	0	0
T121	0	24	0	0
T122	0	42	0	0
T123	9970	0	0	0
T124	346004	0	0	0
T125	115346	0	0	0
T126	0	10	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	1831	0	0
T8	33941	0	0	0
T14	24584	81	0	0
T18	1231	0	0	0
T24	496537	0	0	0
T51	9301	0	0	0
T54	0	36	0	0
T58	0	47	0	0
T59	0	6	0	0
T61	0	61	0	0
T88	0	32	0	0
T102	0	15	0	0
T111	0	7	0	0
T116	240617	0	0	0
T117	7352	0	0	0
T121	0	12	0	0
T122	0	27	0	0
T123	9970	0	0	0
T124	346004	0	0	0
T125	115346	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	214	0	0
T8	33941	0	0	0
T14	24584	59	0	0
T18	1231	0	0	0
T24	496537	0	0	0
T51	9301	0	0	0
T61	0	21	0	0
T116	240617	0	0	0
T117	7352	0	0	0
T121	0	12	0	0
T122	0	13	0	0
T123	9970	0	0	0
T124	346004	0	0	0
T125	115346	0	0	0
T127	0	23	0	0
T128	0	1	0	0
T129	0	11	0	0
T130	0	8	0	0
T131	0	20	0	0
T132	0	8	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198367697	259	0	0
T8	33941	0	0	0
T14	24584	28	0	0
T18	1231	0	0	0
T24	496537	0	0	0
T51	9301	0	0	0
T61	0	84	0	0
T116	240617	0	0	0
T117	7352	0	0	0
T121	0	7	0	0
T122	0	15	0	0
T123	9970	0	0	0
T124	346004	0	0	0
T125	115346	0	0	0
T127	0	22	0	0
T128	0	5	0	0
T129	0	8	0	0
T130	0	10	0	0
T131	0	12	0	0
T133	0	2	0	0