Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11394402	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32573567

1

T1

18818

T3

22528

T4

232965

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21929370	1			T1	52063		T3	11264		T4	127838
values[0x0]	9879783	1			T1	17497		T3	5714		T4	61921
values[0x1]	12158816	1			T1	34802		T3	5550		T4	66806

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5677513	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38290456

1

T1

61958

T3

22528

T4

244741

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	165590	1			T1	432		T3	85		T4	986
valid_sources[0x01]	175984	1			T1	424		T3	92		T4	956
valid_sources[0x02]	222195	1			T1	385		T3	68		T4	966
valid_sources[0x03]	148433	1			T1	308		T3	95		T4	979
valid_sources[0x04]	198609	1			T1	495		T3	82		T4	1032
valid_sources[0x05]	159850	1			T1	450		T3	73		T4	1046
valid_sources[0x06]	152130	1			T1	379		T3	79		T4	1068
valid_sources[0x07]	202169	1			T1	420		T3	84		T4	1010
valid_sources[0x08]	167810	1			T1	396		T3	89		T4	968
valid_sources[0x09]	157860	1			T1	373		T3	88		T4	970
valid_sources[0x0a]	200335	1			T1	435		T3	69		T4	978
valid_sources[0x0b]	168056	1			T1	506		T3	78		T4	987
valid_sources[0x0c]	148897	1			T1	328		T3	69		T4	1069
valid_sources[0x0d]	156433	1			T1	374		T3	76		T4	993
valid_sources[0x0e]	181987	1			T1	500		T3	78		T4	934
valid_sources[0x0f]	198889	1			T1	399		T3	111		T4	991
valid_sources[0x10]	192737	1			T1	391		T3	85		T4	986
valid_sources[0x11]	152495	1			T1	406		T3	106		T4	1069
valid_sources[0x12]	150376	1			T1	361		T3	61		T4	952
valid_sources[0x13]	151212	1			T1	577		T3	78		T4	941
valid_sources[0x14]	152902	1			T1	487		T3	108		T4	990
valid_sources[0x15]	168749	1			T1	352		T3	64		T4	1024
valid_sources[0x16]	201430	1			T1	378		T3	87		T4	1015
valid_sources[0x17]	210084	1			T1	535		T3	78		T4	1060
valid_sources[0x18]	160065	1			T1	540		T3	87		T4	983
valid_sources[0x19]	165931	1			T1	435		T3	72		T4	1023
valid_sources[0x1a]	174731	1			T1	368		T3	75		T4	951
valid_sources[0x1b]	195501	1			T1	367		T3	121		T4	1062
valid_sources[0x1c]	149798	1			T1	443		T3	85		T4	992
valid_sources[0x1d]	153928	1			T1	493		T3	89		T4	996
valid_sources[0x1e]	149195	1			T1	339		T3	93		T4	993
valid_sources[0x1f]	155396	1			T1	448		T3	77		T4	967
valid_sources[0x20]	147696	1			T1	418		T3	127		T4	999
valid_sources[0x21]	154559	1			T1	446		T3	93		T4	999
valid_sources[0x22]	154966	1			T1	398		T3	87		T4	970
valid_sources[0x23]	152111	1			T1	516		T3	111		T4	976
valid_sources[0x24]	170720	1			T1	422		T3	98		T4	1026
valid_sources[0x25]	163872	1			T1	327		T3	76		T4	958
valid_sources[0x26]	153557	1			T1	453		T3	88		T4	1100
valid_sources[0x27]	167096	1			T1	386		T3	78		T4	1069
valid_sources[0x28]	149073	1			T1	336		T3	99		T4	961
valid_sources[0x29]	192245	1			T1	466		T3	77		T4	972
valid_sources[0x2a]	205588	1			T1	410		T3	70		T4	1031
valid_sources[0x2b]	164599	1			T1	297		T3	73		T4	1044
valid_sources[0x2c]	160278	1			T1	449		T3	74		T4	972
valid_sources[0x2d]	174892	1			T1	329		T3	76		T4	995
valid_sources[0x2e]	155834	1			T1	406		T3	80		T4	986
valid_sources[0x2f]	153494	1			T1	406		T3	96		T4	1028
valid_sources[0x30]	157372	1			T1	460		T3	109		T4	1017
valid_sources[0x31]	148100	1			T1	419		T3	69		T4	1029
valid_sources[0x32]	180627	1			T1	472		T3	69		T4	962
valid_sources[0x33]	185205	1			T1	469		T3	75		T4	982
valid_sources[0x34]	178320	1			T1	481		T3	117		T4	946
valid_sources[0x35]	202236	1			T1	365		T3	69		T4	990
valid_sources[0x36]	161942	1			T1	339		T3	79		T4	1009
valid_sources[0x37]	222229	1			T1	412		T3	88		T4	1015
valid_sources[0x38]	158510	1			T1	321		T3	84		T4	986
valid_sources[0x39]	151482	1			T1	406		T3	86		T4	999
valid_sources[0x3a]	161166	1			T1	382		T3	105		T4	1050
valid_sources[0x3b]	199007	1			T1	434		T3	65		T4	1058
valid_sources[0x3c]	176458	1			T1	316		T3	98		T4	990
valid_sources[0x3d]	154706	1			T1	426		T3	104		T4	995
valid_sources[0x3e]	190964	1			T1	473		T3	103		T4	1041
valid_sources[0x3f]	195896	1			T1	387		T3	98		T4	1052
valid_sources[0x40]	189289	1			T1	423		T3	83		T4	1008
valid_sources[0x41]	195615	1			T1	428		T3	91		T4	986
valid_sources[0x42]	149559	1			T1	470		T3	104		T4	1031
valid_sources[0x43]	176959	1			T1	446		T3	100		T4	1021
valid_sources[0x44]	150517	1			T1	466		T3	84		T4	1031
valid_sources[0x45]	148707	1			T1	344		T3	69		T4	1045
valid_sources[0x46]	174414	1			T1	416		T3	78		T4	1021
valid_sources[0x47]	195981	1			T1	395		T3	82		T4	994
valid_sources[0x48]	151919	1			T1	453		T3	103		T4	1022
valid_sources[0x49]	152515	1			T1	499		T3	115		T4	1064
valid_sources[0x4a]	182003	1			T1	471		T3	105		T4	951
valid_sources[0x4b]	171427	1			T1	316		T3	94		T4	964
valid_sources[0x4c]	196382	1			T1	414		T3	119		T4	955
valid_sources[0x4d]	178063	1			T1	388		T3	75		T4	1076
valid_sources[0x4e]	153127	1			T1	450		T3	89		T4	971
valid_sources[0x4f]	196558	1			T1	431		T3	75		T4	1063
valid_sources[0x50]	177557	1			T1	392		T3	85		T4	1046
valid_sources[0x51]	157445	1			T1	343		T3	113		T4	998
valid_sources[0x52]	149423	1			T1	364		T3	92		T4	1039
valid_sources[0x53]	147890	1			T1	509		T3	80		T4	982
valid_sources[0x54]	154165	1			T1	303		T3	90		T4	993
valid_sources[0x55]	172349	1			T1	427		T3	94		T4	967
valid_sources[0x56]	149413	1			T1	357		T3	86		T4	1007
valid_sources[0x57]	167565	1			T1	309		T3	67		T4	981
valid_sources[0x58]	150858	1			T1	445		T3	63		T4	1022
valid_sources[0x59]	179776	1			T1	390		T3	88		T4	1021
valid_sources[0x5a]	174809	1			T1	408		T3	94		T4	950
valid_sources[0x5b]	150964	1			T1	441		T3	75		T4	998
valid_sources[0x5c]	176938	1			T1	387		T3	90		T4	1001
valid_sources[0x5d]	153841	1			T1	489		T3	83		T4	982
valid_sources[0x5e]	190566	1			T1	498		T3	101		T4	985
valid_sources[0x5f]	152225	1			T1	512		T3	71		T4	954
valid_sources[0x60]	156636	1			T1	370		T3	97		T4	938
valid_sources[0x61]	154741	1			T1	367		T3	89		T4	979
valid_sources[0x62]	207488	1			T1	279		T3	91		T4	1024
valid_sources[0x63]	148552	1			T1	452		T3	123		T4	976
valid_sources[0x64]	180927	1			T1	404		T3	114		T4	1016
valid_sources[0x65]	190569	1			T1	391		T3	121		T4	1059
valid_sources[0x66]	166454	1			T1	359		T3	70		T4	1025
valid_sources[0x67]	154187	1			T1	359		T3	85		T4	942
valid_sources[0x68]	148810	1			T1	347		T3	83		T4	925
valid_sources[0x69]	160681	1			T1	438		T3	124		T4	1007
valid_sources[0x6a]	229002	1			T1	367		T3	92		T4	1086
valid_sources[0x6b]	154146	1			T1	357		T3	112		T4	1108
valid_sources[0x6c]	178186	1			T1	415		T3	53		T4	1008
valid_sources[0x6d]	204904	1			T1	443		T3	92		T4	979
valid_sources[0x6e]	153904	1			T1	458		T3	111		T4	946
valid_sources[0x6f]	190038	1			T1	367		T3	88		T4	929
valid_sources[0x70]	158632	1			T1	440		T3	104		T4	1007
valid_sources[0x71]	171455	1			T1	369		T3	80		T4	1007
valid_sources[0x72]	207303	1			T1	313		T3	95		T4	982
valid_sources[0x73]	206127	1			T1	489		T3	63		T4	1054
valid_sources[0x74]	147586	1			T1	338		T3	107		T4	1053
valid_sources[0x75]	148814	1			T1	389		T3	94		T4	986
valid_sources[0x76]	148016	1			T1	371		T3	97		T4	974
valid_sources[0x77]	187926	1			T1	422		T3	90		T4	1003
valid_sources[0x78]	154788	1			T1	447		T3	69		T4	1009
valid_sources[0x79]	149861	1			T1	423		T3	74		T4	1043
valid_sources[0x7a]	157421	1			T1	388		T3	94		T4	1049
valid_sources[0x7b]	260597	1			T1	333		T3	83		T4	931
valid_sources[0x7c]	148804	1			T1	379		T3	105		T4	951
valid_sources[0x7d]	160173	1			T1	370		T3	81		T4	1016
valid_sources[0x7e]	153531	1			T1	301		T3	60		T4	1005
valid_sources[0x7f]	160078	1			T1	454		T3	60		T4	1074
valid_sources[0x80]	148080	1			T1	416		T3	79		T4	1000

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16239584

1

T1

9366

T3

11264

T4

116011

values[0x0]

all_enables

biggest_size

8169190

1

T1

4768

T3

5714

T4

58439

values[0x1]

all_enables

biggest_size

8164793

1

T1

4684

T3

5550

T4

58515

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46203	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29446

1

T1

31

T2

2

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16104	1			T5	16		T29	14		T7	34
values[0x0]	29430	1			T1	76		T2	3		T3	28
values[0x1]	30115	1			T1	73		T2	6		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36173

1

T1

43

T2

4

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	284	1			T1	2		T10	2		T12	2
valid_sources[0x01]	310	1			T4	6		T5	1		T12	1
valid_sources[0x02]	365	1			T4	5		T12	2		T15	117
valid_sources[0x03]	180	1			T10	1		T5	6		T28	3
valid_sources[0x04]	428	1			T12	1		T13	2		T28	2
valid_sources[0x05]	284	1			T10	1		T28	2		T22	2
valid_sources[0x06]	335	1			T1	1		T5	3		T12	4
valid_sources[0x07]	317	1			T5	9		T12	4		T13	2
valid_sources[0x08]	316	1			T1	1		T4	1		T12	4
valid_sources[0x09]	211	1			T1	1		T83	1		T84	2
valid_sources[0x0a]	262	1			T83	3		T28	2		T22	2
valid_sources[0x0b]	361	1			T1	1		T5	1		T13	1
valid_sources[0x0c]	211	1			T1	2		T12	1		T83	5
valid_sources[0x0d]	176	1			T13	2		T83	1		T28	1
valid_sources[0x0e]	309	1			T1	1		T13	1		T28	2
valid_sources[0x0f]	418	1			T5	2		T51	2		T83	5
valid_sources[0x10]	209	1			T83	4		T28	4		T24	12
valid_sources[0x11]	271	1			T10	1		T12	3		T13	3
valid_sources[0x12]	251	1			T3	2		T5	1		T83	3
valid_sources[0x13]	250	1			T83	2		T84	10		T28	4
valid_sources[0x14]	205	1			T28	4		T66	1		T22	1
valid_sources[0x15]	252	1			T1	2		T5	1		T13	1
valid_sources[0x16]	441	1			T1	3		T5	2		T12	5
valid_sources[0x17]	307	1			T1	2		T85	3		T132	1
valid_sources[0x18]	264	1			T1	1		T12	3		T83	3
valid_sources[0x19]	207	1			T1	1		T5	3		T12	1
valid_sources[0x1a]	397	1			T83	2		T28	2		T66	1
valid_sources[0x1b]	141	1			T12	2		T28	1		T22	2
valid_sources[0x1c]	372	1			T13	1		T83	6		T28	3
valid_sources[0x1d]	231	1			T10	1		T83	1		T28	4
valid_sources[0x1e]	325	1			T1	2		T28	3		T162	5
valid_sources[0x1f]	299	1			T10	1		T83	2		T28	1
valid_sources[0x20]	373	1			T5	4		T12	2		T13	1
valid_sources[0x21]	463	1			T1	2		T10	1		T28	4
valid_sources[0x22]	232	1			T5	1		T83	3		T28	5
valid_sources[0x23]	218	1			T1	1		T10	3		T28	2
valid_sources[0x24]	180	1			T1	1		T5	1		T83	2
valid_sources[0x25]	337	1			T1	1		T10	1		T5	1
valid_sources[0x26]	226	1			T1	3		T12	1		T83	1
valid_sources[0x27]	278	1			T28	3		T68	2		T81	1
valid_sources[0x28]	284	1			T10	1		T83	1		T28	3
valid_sources[0x29]	196	1			T1	2		T5	2		T28	1
valid_sources[0x2a]	502	1			T1	2		T83	2		T81	2
valid_sources[0x2b]	413	1			T2	3		T5	1		T12	1
valid_sources[0x2c]	230	1			T12	3		T28	1		T22	2
valid_sources[0x2d]	222	1			T1	2		T12	3		T83	2
valid_sources[0x2e]	379	1			T1	1		T12	1		T13	1
valid_sources[0x2f]	298	1			T28	3		T66	1		T76	10
valid_sources[0x30]	356	1			T83	1		T7	5		T28	2
valid_sources[0x31]	217	1			T1	1		T4	10		T5	2
valid_sources[0x32]	277	1			T2	1		T3	6		T10	2
valid_sources[0x33]	265	1			T1	2		T12	3		T13	1
valid_sources[0x34]	265	1			T5	2		T12	2		T13	1
valid_sources[0x35]	255	1			T5	1		T13	1		T83	1
valid_sources[0x36]	221	1			T13	1		T83	2		T28	3
valid_sources[0x37]	426	1			T5	2		T83	1		T28	2
valid_sources[0x38]	303	1			T5	1		T83	1		T28	1
valid_sources[0x39]	268	1			T10	1		T16	4		T83	2
valid_sources[0x3a]	198	1			T5	1		T51	1		T83	1
valid_sources[0x3b]	312	1			T1	1		T5	1		T12	3
valid_sources[0x3c]	318	1			T5	3		T12	3		T83	2
valid_sources[0x3d]	244	1			T4	12		T83	1		T28	3
valid_sources[0x3e]	259	1			T1	1		T12	1		T83	6
valid_sources[0x3f]	228	1			T1	1		T10	1		T13	3
valid_sources[0x40]	463	1			T1	1		T5	1		T13	1
valid_sources[0x41]	485	1			T5	3		T12	1		T28	4
valid_sources[0x42]	303	1			T83	6		T47	1		T28	4
valid_sources[0x43]	291	1			T1	2		T12	2		T83	1
valid_sources[0x44]	200	1			T1	3		T163	5		T28	1
valid_sources[0x45]	376	1			T1	1		T2	2		T28	2
valid_sources[0x46]	230	1			T5	3		T83	6		T28	1
valid_sources[0x47]	399	1			T12	2		T46	4		T22	2
valid_sources[0x48]	279	1			T16	1		T83	1		T28	5
valid_sources[0x49]	336	1			T5	5		T83	2		T28	2
valid_sources[0x4a]	352	1			T5	1		T13	1		T28	3
valid_sources[0x4b]	202	1			T1	1		T12	2		T13	1
valid_sources[0x4c]	264	1			T28	4		T50	1		T132	1
valid_sources[0x4d]	690	1			T12	1		T16	1		T83	2
valid_sources[0x4e]	275	1			T2	1		T10	1		T12	3
valid_sources[0x4f]	458	1			T1	3		T52	20		T83	6
valid_sources[0x50]	233	1			T13	1		T83	5		T28	2
valid_sources[0x51]	235	1			T4	1		T12	2		T83	3
valid_sources[0x52]	445	1			T1	1		T28	1		T119	1
valid_sources[0x53]	296	1			T1	1		T5	3		T12	1
valid_sources[0x54]	304	1			T1	2		T5	2		T16	1
valid_sources[0x55]	457	1			T5	3		T12	2		T16	3
valid_sources[0x56]	239	1			T28	3		T107	1		T48	3
valid_sources[0x57]	467	1			T1	1		T5	4		T28	1
valid_sources[0x58]	289	1			T1	1		T10	2		T83	5
valid_sources[0x59]	281	1			T1	1		T4	3		T83	6
valid_sources[0x5a]	360	1			T1	1		T5	1		T11	1
valid_sources[0x5b]	209	1			T5	1		T83	1		T28	4
valid_sources[0x5c]	260	1			T5	8		T83	4		T104	3
valid_sources[0x5d]	491	1			T83	3		T28	2		T66	2
valid_sources[0x5e]	189	1			T5	2		T28	4		T22	1
valid_sources[0x5f]	231	1			T4	3		T10	1		T16	1
valid_sources[0x60]	291	1			T5	1		T28	2		T66	1
valid_sources[0x61]	234	1			T28	3		T48	1		T27	1
valid_sources[0x62]	267	1			T12	2		T83	1		T28	1
valid_sources[0x63]	273	1			T5	1		T13	4		T83	1
valid_sources[0x64]	233	1			T1	1		T5	1		T13	1
valid_sources[0x65]	286	1			T83	1		T28	4		T132	4
valid_sources[0x66]	294	1			T1	2		T5	1		T12	2
valid_sources[0x67]	263	1			T16	1		T28	4		T66	1
valid_sources[0x68]	320	1			T1	1		T13	2		T28	5
valid_sources[0x69]	176	1			T5	3		T83	2		T28	4
valid_sources[0x6a]	200	1			T5	2		T13	1		T83	1
valid_sources[0x6b]	556	1			T1	1		T28	4		T17	1
valid_sources[0x6c]	183	1			T1	1		T5	1		T13	2
valid_sources[0x6d]	398	1			T1	2		T5	3		T83	2
valid_sources[0x6e]	232	1			T1	1		T5	5		T83	2
valid_sources[0x6f]	384	1			T1	1		T13	2		T28	1
valid_sources[0x70]	247	1			T1	1		T83	1		T28	5
valid_sources[0x71]	449	1			T10	2		T12	1		T13	2
valid_sources[0x72]	397	1			T5	3		T12	2		T83	3
valid_sources[0x73]	153	1			T1	2		T12	4		T13	2
valid_sources[0x74]	383	1			T4	9		T5	4		T13	1
valid_sources[0x75]	309	1			T5	2		T12	1		T13	1
valid_sources[0x76]	206	1			T12	2		T28	3		T164	1
valid_sources[0x77]	187	1			T1	1		T83	2		T28	3
valid_sources[0x78]	317	1			T1	2		T51	2		T28	4
valid_sources[0x79]	282	1			T1	1		T5	1		T29	12
valid_sources[0x7a]	307	1			T1	4		T10	1		T83	2
valid_sources[0x7b]	413	1			T1	1		T4	1		T5	1
valid_sources[0x7c]	339	1			T1	1		T12	1		T28	2
valid_sources[0x7d]	228	1			T1	1		T83	5		T28	7
valid_sources[0x7e]	559	1			T83	1		T28	3		T22	1
valid_sources[0x7f]	280	1			T1	1		T12	3		T13	2
valid_sources[0x80]	226	1			T5	4		T12	1		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7697

1

T5

7

T29

8

T7

21

values[0x0]

all_enables

biggest_size

12879

1

T1

21

T3

8

T4

19

values[0x1]

all_enables

biggest_size

8870

1

T1

10

T2

2

T3

5