Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11154388

1

T1

85544

T4

18865

T5

10027

full_word

29994241

1

T1

18818

T3

22528

T4

186522

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	41148419	1			T1	104362		T3	22528		T4	205387
auto[TlIntgErrCmd]	70	1			T54	8		T55	9		T56	7
auto[TlIntgErrData]	79	1			T54	8		T55	6		T56	6
auto[TlIntgErrBoth]	61	1			T54	4		T55	5		T56	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19147382

1

T1

52063

T3

11264

T4

76660

auto[1]

22001247

1

T1

52299

T3

11264

T4

128727

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5439659	1			T1	42697		T4	7092		T5	3758
auto[TlIntgErrNone]	partial	auto[1]	5714540	1			T1	42847		T4	11773		T5	6269
auto[TlIntgErrNone]	full_word	auto[0]	13707621	1			T1	9366		T3	11264		T4	69568
auto[TlIntgErrNone]	full_word	auto[1]	16286599	1			T1	9452		T3	11264		T4	116954
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T54	4		T55	4		T56	4
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T54	4		T55	4		T56	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T146	1		T147	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T55	1		T147	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1			T54	4		T55	1		T56	3
auto[TlIntgErrData]	partial	auto[1]	31	1			T54	4		T55	2		T56	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T55	1		T147	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T55	2		T148	2		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1			T54	1		T55	2		T56	5
auto[TlIntgErrBoth]	partial	auto[1]	27	1			T54	2		T55	1		T56	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T55	2		T147	1		T150	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T54	1		T145	1		T147	2