Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	226470	1			T5	1165		T14	286		T15	9162
auto[1]	4037316	1			T1	3080		T4	1897		T6	2826
auto[2]	195655	1			T5	1060		T14	192		T15	8197
auto[3]	4009740	1			T1	2953		T4	1920		T6	2701

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5110282	1			T1	68		T4	3206		T6	5527
auto[1]	837194	1			T1	668		T4	289		T5	309
auto[2]	838028	1			T1	673		T4	293		T5	287
auto[3]	1683677	1			T1	4624		T4	29		T5	35

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1635732

1

T4

3815

T6

5523

T5

2658

auto[1]

6833449

1

T1

6033

T4

2

T6

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	64470	1			T5	941		T14	245		T15	7604
auto[0]	auto[0]	auto[1]	6941	1			T5	104		T14	18		T15	739
auto[0]	auto[0]	auto[2]	6998	1			T5	111		T14	21		T15	735
auto[0]	auto[0]	auto[3]	3867	1			T5	8		T14	2		T15	72
auto[0]	auto[1]	auto[0]	594937	1			T4	1579		T6	2824		T5	137
auto[0]	auto[1]	auto[1]	65728	1			T4	136		T5	101		T14	29
auto[0]	auto[1]	auto[2]	58932	1			T4	161		T5	15		T11	1
auto[0]	auto[1]	auto[3]	24967	1			T4	19		T5	9		T11	52
auto[0]	auto[2]	auto[0]	57806	1			T5	884		T14	154		T15	6924
auto[0]	auto[2]	auto[1]	6232	1			T5	96		T14	10		T15	687
auto[0]	auto[2]	auto[2]	5428	1			T5	67		T14	26		T15	531
auto[0]	auto[2]	auto[3]	3032	1			T5	11		T14	1		T15	48
auto[0]	auto[3]	auto[0]	587741	1			T4	1625		T6	2699		T5	66
auto[0]	auto[3]	auto[1]	58085	1			T4	153		T5	8		T11	7
auto[0]	auto[3]	auto[2]	64498	1			T4	132		T5	93		T11	14
auto[0]	auto[3]	auto[3]	26070	1			T4	10		T5	7		T11	96
auto[1]	auto[0]	auto[0]	4850	1			T5	1		T15	8		T155	610
auto[1]	auto[0]	auto[1]	21517	1			T155	2689		T156	1268		T158	1115
auto[1]	auto[0]	auto[2]	21321	1			T15	3		T155	2661		T156	1286
auto[1]	auto[0]	auto[3]	96506	1			T15	1		T155	11803		T156	5718
auto[1]	auto[1]	auto[0]	1898294	1			T1	40		T4	2		T6	2
auto[1]	auto[1]	auto[1]	335738	1			T1	511		T12	606		T13	4921
auto[1]	auto[1]	auto[2]	328886	1			T1	185		T12	207		T13	4804
auto[1]	auto[1]	auto[3]	729834	1			T1	2344		T12	2738		T13	22007
auto[1]	auto[2]	auto[0]	4027	1			T5	1		T14	1		T15	6
auto[1]	auto[2]	auto[1]	17732	1			T155	2390		T156	774		T159	1
auto[1]	auto[2]	auto[2]	18596	1			T5	1		T15	1		T155	1878
auto[1]	auto[2]	auto[3]	82802	1			T155	8429		T156	6243		T160	1
auto[1]	auto[3]	auto[0]	1898157	1			T1	28		T6	2		T12	48
auto[1]	auto[3]	auto[1]	325221	1			T1	157		T12	214		T13	4708
auto[1]	auto[3]	auto[2]	333369	1			T1	488		T12	617		T13	4747
auto[1]	auto[3]	auto[3]	716599	1			T1	2280		T12	2701		T13	21921