Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.12	100.00	89.90	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	205777529	18267	0	0
ctrl_regwen_rd_A	205777529	1686	0	0
exec_rd_A	205777529	1884	0	0
exec_regwen_rd_A	205777529	1766	0	0
readback_rd_A	205777529	499	0	0
readback_regwen_rd_A	205777529	384	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	18267	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	453	0	0
T30	0	895	0	0
T31	0	1722	0	0
T53	0	903	0	0
T54	0	6	0	0
T61	0	61	0	0
T62	0	514	0	0
T63	0	520	0	0
T64	0	85	0	0
T65	0	923	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	1686	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	69	0	0
T31	0	74	0	0
T53	0	65	0	0
T59	0	47	0	0
T63	0	10	0	0
T65	0	18	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0
T94	0	7	0	0
T95	0	44	0	0
T128	0	20	0	0
T134	0	1	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	1884	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	66	0	0
T31	0	144	0	0
T53	0	53	0	0
T59	0	62	0	0
T63	0	28	0	0
T65	0	59	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0
T94	0	4	0	0
T95	0	51	0	0
T128	0	1	0	0
T134	0	1	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	1766	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	33	0	0
T31	0	92	0	0
T53	0	109	0	0
T59	0	36	0	0
T63	0	21	0	0
T65	0	49	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0
T94	0	8	0	0
T95	0	46	0	0
T96	0	9	0	0
T128	0	29	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	499	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	19	0	0
T31	0	69	0	0
T53	0	82	0	0
T63	0	39	0	0
T65	0	43	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0
T73	0	31	0	0
T135	0	77	0	0
T136	0	43	0	0
T137	0	22	0	0
T138	0	46	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205777529	384	0	0
T8	55405	0	0	0
T17	836	0	0	0
T22	270257	0	0	0
T28	15038	48	0	0
T31	0	51	0	0
T53	0	27	0	0
T63	0	8	0	0
T65	0	38	0	0
T66	154776	0	0	0
T67	9334	0	0	0
T68	8930	0	0	0
T69	14494	0	0	0
T70	6583	0	0	0
T71	13476	0	0	0
T73	0	42	0	0
T135	0	23	0	0
T136	0	40	0	0
T137	0	10	0	0
T139	0	19	0	0