Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14398792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59703037

1

T1

41423

T2

485158

T3

6142

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36933865	1			T1	113748		T2	267022		T3	2048
values[0x0]	17140696	1			T1	38376		T2	128209		T3	2097
values[0x1]	20027268	1			T1	75741		T2	138444		T3	1997

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7173875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66927954

1

T1

135064

T2

509394

T3

6142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	320546	1			T1	883		T2	2087		T3	32
valid_sources[0x01]	247292	1			T1	1059		T2	1787		T3	23
valid_sources[0x02]	268371	1			T1	610		T2	2153		T3	19
valid_sources[0x03]	283342	1			T1	818		T2	1845		T3	15
valid_sources[0x04]	271785	1			T1	795		T2	2237		T3	27
valid_sources[0x05]	294496	1			T1	821		T2	2192		T3	18
valid_sources[0x06]	294266	1			T1	754		T2	2101		T3	21
valid_sources[0x07]	277032	1			T1	985		T2	2019		T3	20
valid_sources[0x08]	316319	1			T1	932		T2	2094		T3	13
valid_sources[0x09]	336676	1			T1	914		T2	2163		T3	25
valid_sources[0x0a]	289417	1			T1	1040		T2	2033		T3	29
valid_sources[0x0b]	280755	1			T1	862		T2	1986		T3	28
valid_sources[0x0c]	291183	1			T1	968		T2	2109		T3	23
valid_sources[0x0d]	275445	1			T1	937		T2	1945		T3	18
valid_sources[0x0e]	298526	1			T1	878		T2	2101		T3	29
valid_sources[0x0f]	301332	1			T1	900		T2	1975		T3	31
valid_sources[0x10]	274482	1			T1	821		T2	2043		T3	32
valid_sources[0x11]	406137	1			T1	887		T2	2128		T3	19
valid_sources[0x12]	272487	1			T1	923		T2	2207		T3	25
valid_sources[0x13]	306976	1			T1	1071		T2	2027		T3	17
valid_sources[0x14]	291724	1			T1	802		T2	2065		T3	21
valid_sources[0x15]	277989	1			T1	917		T2	2132		T3	39
valid_sources[0x16]	243529	1			T1	895		T2	2050		T3	23
valid_sources[0x17]	249182	1			T1	690		T2	2011		T3	15
valid_sources[0x18]	290164	1			T1	963		T2	2185		T3	20
valid_sources[0x19]	312567	1			T1	717		T2	2063		T3	38
valid_sources[0x1a]	398188	1			T1	810		T2	2046		T3	22
valid_sources[0x1b]	289355	1			T1	911		T2	2081		T3	14
valid_sources[0x1c]	330141	1			T1	858		T2	2060		T3	25
valid_sources[0x1d]	269227	1			T1	1034		T2	2136		T3	25
valid_sources[0x1e]	278638	1			T1	911		T2	2099		T3	28
valid_sources[0x1f]	260281	1			T1	807		T2	2043		T3	16
valid_sources[0x20]	301455	1			T1	974		T2	2077		T3	21
valid_sources[0x21]	311756	1			T1	719		T2	2026		T3	18
valid_sources[0x22]	329794	1			T1	916		T2	2038		T3	15
valid_sources[0x23]	323634	1			T1	855		T2	2124		T3	33
valid_sources[0x24]	346514	1			T1	850		T2	2172		T3	27
valid_sources[0x25]	270354	1			T1	1168		T2	2425		T3	20
valid_sources[0x26]	294735	1			T1	925		T2	2141		T3	35
valid_sources[0x27]	302469	1			T1	928		T2	2108		T3	31
valid_sources[0x28]	296586	1			T1	931		T2	2081		T3	27
valid_sources[0x29]	297418	1			T1	645		T2	2068		T3	22
valid_sources[0x2a]	254317	1			T1	1030		T2	2075		T3	22
valid_sources[0x2b]	299612	1			T1	948		T2	2247		T3	29
valid_sources[0x2c]	271634	1			T1	815		T2	1965		T3	34
valid_sources[0x2d]	279356	1			T1	832		T2	2097		T3	32
valid_sources[0x2e]	243772	1			T1	783		T2	2107		T3	20
valid_sources[0x2f]	247725	1			T1	943		T2	2105		T3	29
valid_sources[0x30]	301474	1			T1	1010		T2	1988		T3	15
valid_sources[0x31]	398854	1			T1	876		T2	2127		T3	26
valid_sources[0x32]	262087	1			T1	654		T2	2144		T3	19
valid_sources[0x33]	276544	1			T1	814		T2	2247		T3	28
valid_sources[0x34]	302206	1			T1	1000		T2	2022		T3	22
valid_sources[0x35]	378169	1			T1	948		T2	2147		T3	19
valid_sources[0x36]	252407	1			T1	899		T2	2029		T3	30
valid_sources[0x37]	250286	1			T1	754		T2	2019		T3	32
valid_sources[0x38]	256550	1			T1	883		T2	2162		T3	24
valid_sources[0x39]	292185	1			T1	840		T2	1916		T3	23
valid_sources[0x3a]	266033	1			T1	698		T2	2081		T3	27
valid_sources[0x3b]	309896	1			T1	846		T2	2069		T3	27
valid_sources[0x3c]	302365	1			T1	848		T2	2213		T3	27
valid_sources[0x3d]	259740	1			T1	814		T2	2116		T3	23
valid_sources[0x3e]	255162	1			T1	717		T2	1931		T3	24
valid_sources[0x3f]	263049	1			T1	1044		T2	2245		T3	25
valid_sources[0x40]	268236	1			T1	850		T2	1792		T3	21
valid_sources[0x41]	319518	1			T1	990		T2	1881		T3	26
valid_sources[0x42]	309725	1			T1	940		T2	1995		T3	29
valid_sources[0x43]	298004	1			T1	863		T2	2062		T3	32
valid_sources[0x44]	246120	1			T1	927		T2	2206		T3	24
valid_sources[0x45]	285436	1			T1	1104		T2	1989		T3	22
valid_sources[0x46]	289942	1			T1	884		T2	2189		T3	23
valid_sources[0x47]	315839	1			T1	1060		T2	2129		T3	18
valid_sources[0x48]	275768	1			T1	923		T2	2195		T3	31
valid_sources[0x49]	311514	1			T1	901		T2	2020		T3	26
valid_sources[0x4a]	277207	1			T1	846		T2	2038		T3	25
valid_sources[0x4b]	266518	1			T1	988		T2	2119		T3	18
valid_sources[0x4c]	292823	1			T1	762		T2	2098		T3	16
valid_sources[0x4d]	248516	1			T1	883		T2	2036		T3	29
valid_sources[0x4e]	313295	1			T1	874		T2	2038		T3	21
valid_sources[0x4f]	318511	1			T1	710		T2	2113		T3	36
valid_sources[0x50]	277613	1			T1	934		T2	2133		T3	18
valid_sources[0x51]	274687	1			T1	946		T2	2137		T3	24
valid_sources[0x52]	263455	1			T1	909		T2	2161		T3	29
valid_sources[0x53]	284146	1			T1	879		T2	2117		T3	18
valid_sources[0x54]	268090	1			T1	996		T2	2045		T3	16
valid_sources[0x55]	333684	1			T1	829		T2	2096		T3	19
valid_sources[0x56]	261956	1			T1	1116		T2	2137		T3	16
valid_sources[0x57]	299330	1			T1	1037		T2	1945		T3	18
valid_sources[0x58]	268370	1			T1	1030		T2	2157		T3	16
valid_sources[0x59]	276599	1			T1	1054		T2	2117		T3	33
valid_sources[0x5a]	273062	1			T1	1147		T2	2044		T3	23
valid_sources[0x5b]	334897	1			T1	783		T2	2010		T3	24
valid_sources[0x5c]	282133	1			T1	811		T2	2112		T3	13
valid_sources[0x5d]	310997	1			T1	746		T2	2072		T3	17
valid_sources[0x5e]	256500	1			T1	897		T2	2058		T3	25
valid_sources[0x5f]	290310	1			T1	875		T2	2129		T3	20
valid_sources[0x60]	254114	1			T1	872		T2	1982		T3	20
valid_sources[0x61]	281699	1			T1	736		T2	1925		T3	23
valid_sources[0x62]	351947	1			T1	753		T2	2071		T3	18
valid_sources[0x63]	292902	1			T1	833		T2	2103		T3	33
valid_sources[0x64]	311752	1			T1	882		T2	2192		T3	28
valid_sources[0x65]	301696	1			T1	1047		T2	2046		T3	33
valid_sources[0x66]	262292	1			T1	986		T2	1854		T3	16
valid_sources[0x67]	248529	1			T1	877		T2	2018		T3	26
valid_sources[0x68]	260335	1			T1	883		T2	1912		T3	28
valid_sources[0x69]	255116	1			T1	816		T2	2115		T3	30
valid_sources[0x6a]	250417	1			T1	897		T2	1912		T3	30
valid_sources[0x6b]	315650	1			T1	848		T2	2118		T3	29
valid_sources[0x6c]	276064	1			T1	1098		T2	2106		T3	21
valid_sources[0x6d]	316168	1			T1	835		T2	2009		T3	25
valid_sources[0x6e]	267047	1			T1	878		T2	2078		T3	22
valid_sources[0x6f]	299504	1			T1	991		T2	2049		T3	35
valid_sources[0x70]	264242	1			T1	1027		T2	2126		T3	25
valid_sources[0x71]	292442	1			T1	878		T2	2039		T3	32
valid_sources[0x72]	333681	1			T1	877		T2	2073		T3	26
valid_sources[0x73]	259333	1			T1	904		T2	2187		T3	29
valid_sources[0x74]	267779	1			T1	747		T2	2105		T3	24
valid_sources[0x75]	284930	1			T1	838		T2	2105		T3	22
valid_sources[0x76]	247629	1			T1	673		T2	2178		T3	22
valid_sources[0x77]	284745	1			T1	860		T2	2080		T3	29
valid_sources[0x78]	317314	1			T1	848		T2	2110		T3	22
valid_sources[0x79]	261912	1			T1	880		T2	1990		T3	34
valid_sources[0x7a]	308023	1			T1	982		T2	2160		T3	34
valid_sources[0x7b]	284542	1			T1	1016		T2	2199		T3	26
valid_sources[0x7c]	311077	1			T1	877		T2	2012		T3	25
valid_sources[0x7d]	277756	1			T1	929		T2	2052		T3	22
valid_sources[0x7e]	276734	1			T1	893		T2	2060		T3	21
valid_sources[0x7f]	264790	1			T1	1122		T2	2211		T3	36
valid_sources[0x80]	307196	1			T1	907		T2	2175		T3	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29740651

1

T1

20726

T2

242697

T3

2048

values[0x0]

all_enables

biggest_size

14979621

1

T1

10345

T2

120949

T3

2097

values[0x1]

all_enables

biggest_size

14982765

1

T1

10352

T2

121512

T3

1997

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145259

1

T2

71

T3

7

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51254	1			T2	63		T12	11		T5	30
values[0x0]	62102	1			T1	5		T2	83		T3	7
values[0x1]	67010	1			T1	3		T2	85		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153947

1

T2

94

T3

8

T9

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	514	1			T2	1		T15	4		T26	17
valid_sources[0x01]	772	1			T2	4		T26	18		T141	1
valid_sources[0x02]	955	1			T26	19		T142	1		T118	1
valid_sources[0x03]	509	1			T26	15		T132	1		T118	2
valid_sources[0x04]	704	1			T26	12		T118	1		T138	1
valid_sources[0x05]	801	1			T26	14		T143	1		T23	1
valid_sources[0x06]	930	1			T26	26		T144	3		T143	1
valid_sources[0x07]	817	1			T1	1		T26	11		T24	1
valid_sources[0x08]	557	1			T41	1		T26	15		T144	3
valid_sources[0x09]	615	1			T26	19		T28	3		T54	6
valid_sources[0x0a]	764	1			T26	8		T141	1		T22	1
valid_sources[0x0b]	471	1			T2	4		T26	12		T69	2
valid_sources[0x0c]	609	1			T56	3		T26	11		T69	2
valid_sources[0x0d]	565	1			T26	10		T141	1		T145	1
valid_sources[0x0e]	861	1			T3	1		T26	12		T6	1
valid_sources[0x0f]	708	1			T61	1		T26	21		T143	1
valid_sources[0x10]	819	1			T26	9		T88	1		T27	4
valid_sources[0x11]	590	1			T41	1		T26	21		T145	1
valid_sources[0x12]	534	1			T26	23		T146	10		T147	1
valid_sources[0x13]	536	1			T26	13		T148	1		T23	1
valid_sources[0x14]	782	1			T26	12		T132	1		T149	1
valid_sources[0x15]	834	1			T26	18		T150	1		T151	1
valid_sources[0x16]	902	1			T26	19		T69	1		T145	1
valid_sources[0x17]	1278	1			T26	22		T143	1		T22	2
valid_sources[0x18]	756	1			T2	1		T26	15		T6	1
valid_sources[0x19]	907	1			T26	11		T6	1		T144	1
valid_sources[0x1a]	484	1			T61	2		T26	16		T69	2
valid_sources[0x1b]	950	1			T26	16		T147	1		T23	1
valid_sources[0x1c]	824	1			T2	4		T26	20		T152	2
valid_sources[0x1d]	514	1			T61	2		T26	12		T153	1
valid_sources[0x1e]	473	1			T61	2		T26	16		T6	1
valid_sources[0x1f]	614	1			T26	15		T23	1		T27	3
valid_sources[0x20]	504	1			T41	1		T26	16		T24	2
valid_sources[0x21]	1155	1			T26	16		T137	1		T145	2
valid_sources[0x22]	520	1			T3	1		T26	9		T143	1
valid_sources[0x23]	685	1			T26	13		T24	2		T144	1
valid_sources[0x24]	784	1			T2	2		T41	1		T61	3
valid_sources[0x25]	555	1			T26	17		T24	3		T154	3
valid_sources[0x26]	672	1			T61	1		T26	10		T155	8
valid_sources[0x27]	709	1			T12	7		T14	2		T26	19
valid_sources[0x28]	470	1			T2	13		T41	1		T26	13
valid_sources[0x29]	689	1			T41	1		T26	21		T24	3
valid_sources[0x2a]	644	1			T26	12		T27	2		T54	14
valid_sources[0x2b]	1485	1			T2	1		T41	1		T26	22
valid_sources[0x2c]	832	1			T26	12		T24	4		T72	74
valid_sources[0x2d]	554	1			T26	18		T156	1		T152	1
valid_sources[0x2e]	831	1			T26	17		T145	2		T27	8
valid_sources[0x2f]	532	1			T2	11		T26	16		T6	1
valid_sources[0x30]	822	1			T2	23		T12	2		T26	12
valid_sources[0x31]	489	1			T2	2		T26	15		T6	1
valid_sources[0x32]	599	1			T26	11		T24	4		T157	1
valid_sources[0x33]	734	1			T26	17		T143	2		T27	6
valid_sources[0x34]	754	1			T2	7		T61	5		T26	11
valid_sources[0x35]	531	1			T26	21		T118	1		T141	1
valid_sources[0x36]	594	1			T61	2		T26	6		T144	5
valid_sources[0x37]	846	1			T2	2		T26	12		T6	2
valid_sources[0x38]	848	1			T11	1		T26	11		T118	1
valid_sources[0x39]	573	1			T26	12		T134	24		T141	1
valid_sources[0x3a]	537	1			T2	1		T26	10		T144	1
valid_sources[0x3b]	1046	1			T26	15		T150	5		T118	1
valid_sources[0x3c]	883	1			T61	4		T26	16		T118	1
valid_sources[0x3d]	742	1			T2	2		T26	20		T69	3
valid_sources[0x3e]	680	1			T26	13		T118	1		T145	1
valid_sources[0x3f]	585	1			T41	1		T26	15		T69	3
valid_sources[0x40]	668	1			T26	21		T158	2		T22	2
valid_sources[0x41]	530	1			T26	9		T118	2		T54	7
valid_sources[0x42]	728	1			T26	13		T6	2		T159	1
valid_sources[0x43]	691	1			T26	19		T6	2		T150	7
valid_sources[0x44]	550	1			T26	21		T144	4		T160	1
valid_sources[0x45]	491	1			T26	14		T6	1		T161	2
valid_sources[0x46]	540	1			T41	1		T26	12		T70	1
valid_sources[0x47]	501	1			T26	12		T22	2		T23	1
valid_sources[0x48]	767	1			T26	16		T141	1		T23	1
valid_sources[0x49]	732	1			T2	7		T8	2		T26	14
valid_sources[0x4a]	635	1			T26	11		T145	1		T162	2
valid_sources[0x4b]	768	1			T26	17		T141	1		T22	7
valid_sources[0x4c]	795	1			T2	3		T26	13		T163	2
valid_sources[0x4d]	711	1			T12	8		T26	9		T24	4
valid_sources[0x4e]	681	1			T12	5		T26	20		T22	2
valid_sources[0x4f]	599	1			T10	1		T26	16		T24	1
valid_sources[0x50]	641	1			T26	14		T132	1		T143	1
valid_sources[0x51]	664	1			T26	22		T24	1		T132	1
valid_sources[0x52]	657	1			T11	1		T26	14		T144	6
valid_sources[0x53]	506	1			T26	12		T24	3		T88	1
valid_sources[0x54]	690	1			T61	8		T26	15		T24	1
valid_sources[0x55]	786	1			T41	1		T26	12		T164	1
valid_sources[0x56]	988	1			T26	14		T143	1		T165	9
valid_sources[0x57]	937	1			T26	15		T159	2		T144	1
valid_sources[0x58]	598	1			T3	1		T26	22		T69	3
valid_sources[0x59]	554	1			T26	10		T152	4		T143	1
valid_sources[0x5a]	497	1			T26	17		T23	2		T27	7
valid_sources[0x5b]	1011	1			T2	4		T26	15		T166	18
valid_sources[0x5c]	892	1			T15	2		T41	1		T26	16
valid_sources[0x5d]	548	1			T26	14		T118	1		T137	1
valid_sources[0x5e]	652	1			T41	2		T26	14		T141	1
valid_sources[0x5f]	604	1			T2	2		T26	18		T24	2
valid_sources[0x60]	489	1			T26	11		T22	2		T54	6
valid_sources[0x61]	956	1			T2	4		T15	1		T26	12
valid_sources[0x62]	746	1			T26	17		T144	1		T132	3
valid_sources[0x63]	715	1			T26	20		T6	1		T118	2
valid_sources[0x64]	1393	1			T26	13		T24	3		T118	1
valid_sources[0x65]	969	1			T12	9		T26	15		T132	1
valid_sources[0x66]	688	1			T12	5		T26	24		T21	121
valid_sources[0x67]	527	1			T11	1		T26	18		T150	2
valid_sources[0x68]	544	1			T26	22		T145	1		T23	1
valid_sources[0x69]	836	1			T3	13		T26	19		T132	1
valid_sources[0x6a]	790	1			T26	22		T132	1		T145	1
valid_sources[0x6b]	513	1			T26	23		T6	1		T143	1
valid_sources[0x6c]	728	1			T61	1		T26	16		T150	3
valid_sources[0x6d]	579	1			T29	1		T26	15		T98	1
valid_sources[0x6e]	1367	1			T26	16		T24	2		T156	2
valid_sources[0x6f]	690	1			T26	19		T133	112		T164	1
valid_sources[0x70]	1049	1			T26	20		T22	1		T23	2
valid_sources[0x71]	631	1			T2	1		T4	3		T26	14
valid_sources[0x72]	773	1			T26	13		T144	3		T118	1
valid_sources[0x73]	538	1			T11	7		T26	11		T6	1
valid_sources[0x74]	752	1			T26	16		T145	1		T22	4
valid_sources[0x75]	534	1			T26	17		T6	1		T118	1
valid_sources[0x76]	499	1			T2	3		T26	15		T145	1
valid_sources[0x77]	702	1			T26	16		T27	2		T42	1
valid_sources[0x78]	504	1			T41	1		T26	17		T167	1
valid_sources[0x79]	729	1			T41	1		T26	8		T6	1
valid_sources[0x7a]	560	1			T2	5		T26	15		T87	1
valid_sources[0x7b]	628	1			T26	14		T6	1		T118	1
valid_sources[0x7c]	973	1			T11	1		T26	13		T132	1
valid_sources[0x7d]	585	1			T26	14		T150	3		T141	2
valid_sources[0x7e]	945	1			T61	2		T26	17		T149	1
valid_sources[0x7f]	671	1			T2	6		T61	1		T26	15
valid_sources[0x80]	519	1			T26	22		T149	1		T143	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39472

1

T2

31

T12

2

T5

18

values[0x0]

all_enables

biggest_size

53815

1

T2

27

T3

4

T9

2

values[0x1]

all_enables

biggest_size

51972

1

T2

13

T3

3

T11

3