Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14109141

1

T1

186442

T2

41607

T4

1881

full_word

54763909

1

T1

41423

T2

415678

T3

6142

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68872780	1			T1	227865		T2	457285		T3	6142
auto[TlIntgErrCmd]	93	1			T57	4		T58	7		T59	1
auto[TlIntgErrData]	87	1			T57	5		T58	10		T59	5
auto[TlIntgErrBoth]	90	1			T57	1		T58	3		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31616304

1

T1

113748

T2

192612

T3

2048

auto[1]

37256746

1

T1

114117

T2

264673

T3

4094

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6747001	1			T1	93022		T2	17602		T4	879
auto[TlIntgErrNone]	partial	auto[1]	7361890	1			T1	93420		T2	24005		T4	1002
auto[TlIntgErrNone]	full_word	auto[0]	24869195	1			T1	20726		T2	175010		T3	2048
auto[TlIntgErrNone]	full_word	auto[1]	29894694	1			T1	20697		T2	240668		T3	4094
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T57	1		T58	4		T119	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T57	2		T58	3		T59	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T120	1		T128	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	1		T126	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T57	2		T58	1		T59	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T57	3		T58	9		T59	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T122	1		T123	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T120	1		T129	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T58	1		T59	2		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T57	1		T58	2		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T131	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T59	1		T123	1		T124	1