Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	610790	1			T2	11532		T11	662		T5	13
auto[1]	10204305	1			T1	12097		T2	2786		T4	808
auto[2]	502750	1			T2	10509		T11	397		T5	14
auto[3]	10103320	1			T1	12014		T2	1596		T4	993

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14481449	1			T1	327		T2	20779		T4	4
auto[1]	1997917	1			T1	2774		T2	2893		T4	101
auto[2]	1983487	1			T1	2799		T2	2436		T4	155
auto[3]	2958312	1			T1	18211		T2	315		T4	1541

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8469684

1

T2

26402

T4

1800

T11

1739

auto[1]

12951481

1

T1

24111

T2

21

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	214777	1			T2	9536		T11	545		T5	12
auto[0]	auto[0]	auto[1]	22114	1			T2	953		T11	43		T21	211
auto[0]	auto[0]	auto[2]	22195	1			T2	942		T11	65		T5	1
auto[0]	auto[0]	auto[3]	7124	1			T2	91		T11	8		T21	21
auto[0]	auto[1]	auto[0]	3258939	1			T2	1559		T11	359		T12	3865
auto[0]	auto[1]	auto[1]	341828	1			T2	967		T4	5		T11	65
auto[0]	auto[1]	auto[2]	328411	1			T2	168		T4	69		T11	33
auto[0]	auto[1]	auto[3]	76855	1			T2	91		T4	734		T11	6
auto[0]	auto[2]	auto[0]	183490	1			T2	8892		T11	291		T5	12
auto[0]	auto[2]	auto[1]	19233	1			T2	891		T11	38		T5	1
auto[0]	auto[2]	auto[2]	18390	1			T2	650		T11	57		T5	1
auto[0]	auto[2]	auto[3]	6029	1			T2	67		T11	11		T21	11
auto[0]	auto[3]	auto[0]	3227408	1			T2	776		T4	4		T11	133
auto[0]	auto[3]	auto[1]	326358	1			T2	81		T4	96		T11	12
auto[0]	auto[3]	auto[2]	337976	1			T2	672		T4	86		T11	68
auto[0]	auto[3]	auto[3]	78557	1			T2	66		T4	806		T11	5
auto[1]	auto[0]	auto[0]	11656	1			T2	8		T21	2		T132	1
auto[1]	auto[0]	auto[1]	50950	1			T137	1		T138	1		T135	2723
auto[1]	auto[0]	auto[2]	50903	1			T2	2		T11	1		T138	2
auto[1]	auto[0]	auto[3]	231071	1			T87	2		T135	11889		T139	1
auto[1]	auto[1]	auto[0]	3786599	1			T1	154		T2	1		T12	5
auto[1]	auto[1]	auto[1]	616399	1			T1	2002		T13	13994		T41	3
auto[1]	auto[1]	auto[2]	580711	1			T1	743		T13	14010		T41	4
auto[1]	auto[1]	auto[3]	1214563	1			T1	9198		T13	63629		T97	6249
auto[1]	auto[2]	auto[0]	10220	1			T2	7		T21	3		T138	11
auto[1]	auto[2]	auto[1]	45835	1			T2	1		T138	1		T135	2574
auto[1]	auto[2]	auto[2]	39885	1			T2	1		T138	1		T135	1857
auto[1]	auto[2]	auto[3]	179668	1			T135	8056		T136	8215		T140	11945
auto[1]	auto[3]	auto[0]	3788360	1			T1	173		T12	4		T13	3057
auto[1]	auto[3]	auto[1]	575200	1			T1	772		T12	1		T13	14042
auto[1]	auto[3]	auto[2]	605016	1			T1	2056		T2	1		T11	1
auto[1]	auto[3]	auto[3]	1164445	1			T1	9013		T4	1		T13	63555