Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.92	100.00	88.89	100.00		100.00	85.71	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	320940029	216913	0	0
ctrl_regwen_rd_A	320940029	3288	0	0
exec_rd_A	320940029	3200	0	0
exec_regwen_rd_A	320940029	3270	0	0
readback_rd_A	320940029	1629	0	0
readback_regwen_rd_A	320940029	1287	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	216913	0	0
T6	32217	0	0	0
T21	189865	0	0	0
T24	60596	0	0	0
T25	365925	0	0	0
T26	107405	5376	0	0
T27	0	1595	0	0
T28	0	4178	0	0
T44	0	1340	0	0
T54	0	4432	0	0
T55	0	11304	0	0
T64	0	7337	0	0
T65	0	8287	0	0
T66	0	5600	0	0
T67	0	2496	0	0
T68	2994	0	0	0
T69	356973	0	0	0
T70	1968	0	0	0
T71	528558	0	0	0
T72	123878	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	3288	0	0
T37	337825	421	0	0
T38	5255	0	0	0
T39	6715	0	0	0
T40	226003	0	0	0
T58	0	77	0	0
T62	0	8	0	0
T75	0	389	0	0
T92	0	1	0	0
T102	0	452	0	0
T103	0	182	0	0
T104	0	67	0	0
T105	0	261	0	0
T106	0	48	0	0
T107	9994	0	0	0
T108	67131	0	0	0
T109	5504	0	0	0
T110	29115	0	0	0
T111	33045	0	0	0
T112	214355	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	3200	0	0
T37	337825	479	0	0
T38	5255	0	0	0
T39	6715	0	0	0
T40	226003	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T74	0	41	0	0
T92	0	21	0	0
T102	0	311	0	0
T103	0	106	0	0
T104	0	43	0	0
T105	0	335	0	0
T106	0	52	0	0
T107	9994	0	0	0
T108	67131	0	0	0
T109	5504	0	0	0
T110	29115	0	0	0
T111	33045	0	0	0
T112	214355	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	3270	0	0
T37	337825	441	0	0
T38	5255	0	0	0
T39	6715	0	0	0
T40	226003	0	0	0
T58	0	103	0	0
T62	0	1	0	0
T74	0	29	0	0
T75	0	421	0	0
T102	0	480	0	0
T103	0	190	0	0
T104	0	77	0	0
T105	0	237	0	0
T106	0	39	0	0
T107	9994	0	0	0
T108	67131	0	0	0
T109	5504	0	0	0
T110	29115	0	0	0
T111	33045	0	0	0
T112	214355	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	1629	0	0
T37	337825	466	0	0
T38	5255	0	0	0
T39	6715	0	0	0
T40	226003	0	0	0
T102	0	447	0	0
T103	0	107	0	0
T104	0	76	0	0
T105	0	251	0	0
T106	0	35	0	0
T107	9994	0	0	0
T108	67131	0	0	0
T109	5504	0	0	0
T110	29115	0	0	0
T111	33045	0	0	0
T112	214355	0	0	0
T113	0	21	0	0
T114	0	56	0	0
T115	0	5	0	0
T116	0	51	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320940029	1287	0	0
T37	337825	405	0	0
T38	5255	0	0	0
T39	6715	0	0	0
T40	226003	0	0	0
T102	0	297	0	0
T103	0	124	0	0
T104	0	32	0	0
T105	0	216	0	0
T106	0	31	0	0
T107	9994	0	0	0
T108	67131	0	0	0
T109	5504	0	0	0
T110	29115	0	0	0
T111	33045	0	0	0
T112	214355	0	0	0
T113	0	16	0	0
T114	0	44	0	0
T116	0	16	0	0
T117	0	42	0	0