Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.21 99.18 95.17 100.00 100.00 96.12 99.56 97.44


Total test records in report: 1019
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T553 /workspace/coverage/default/1.sram_ctrl_regwen.1804411563 Jun 05 04:39:36 PM PDT 24 Jun 05 04:52:58 PM PDT 24 53242470595 ps
T554 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1311373906 Jun 05 04:39:27 PM PDT 24 Jun 05 04:39:33 PM PDT 24 2322261613 ps
T555 /workspace/coverage/default/25.sram_ctrl_partial_access.4188150322 Jun 05 04:41:10 PM PDT 24 Jun 05 04:41:13 PM PDT 24 119113404 ps
T556 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1407363406 Jun 05 04:40:32 PM PDT 24 Jun 05 04:47:18 PM PDT 24 971843010 ps
T557 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1890296705 Jun 05 04:40:23 PM PDT 24 Jun 05 04:47:19 PM PDT 24 35569588154 ps
T558 /workspace/coverage/default/17.sram_ctrl_executable.2687719685 Jun 05 04:40:30 PM PDT 24 Jun 05 04:58:13 PM PDT 24 24748632004 ps
T559 /workspace/coverage/default/9.sram_ctrl_mem_walk.2181227169 Jun 05 04:40:05 PM PDT 24 Jun 05 04:40:11 PM PDT 24 75031595 ps
T560 /workspace/coverage/default/25.sram_ctrl_max_throughput.2313089662 Jun 05 04:41:12 PM PDT 24 Jun 05 04:42:27 PM PDT 24 330919931 ps
T561 /workspace/coverage/default/16.sram_ctrl_executable.1657052297 Jun 05 04:40:30 PM PDT 24 Jun 05 04:54:56 PM PDT 24 64927407139 ps
T562 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1422260356 Jun 05 04:39:56 PM PDT 24 Jun 05 04:47:19 PM PDT 24 62900055948 ps
T563 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.66167547 Jun 05 04:39:46 PM PDT 24 Jun 05 04:39:52 PM PDT 24 172489636 ps
T564 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.88145304 Jun 05 04:41:02 PM PDT 24 Jun 05 04:41:06 PM PDT 24 112905685 ps
T565 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2671766036 Jun 05 04:40:50 PM PDT 24 Jun 05 04:40:56 PM PDT 24 183933024 ps
T566 /workspace/coverage/default/14.sram_ctrl_regwen.3243760657 Jun 05 04:40:26 PM PDT 24 Jun 05 04:43:33 PM PDT 24 2385819913 ps
T567 /workspace/coverage/default/23.sram_ctrl_alert_test.2065490954 Jun 05 04:41:01 PM PDT 24 Jun 05 04:41:02 PM PDT 24 39721119 ps
T568 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1878887716 Jun 05 04:43:20 PM PDT 24 Jun 05 05:03:10 PM PDT 24 45789887424 ps
T569 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1683466538 Jun 05 04:40:29 PM PDT 24 Jun 05 04:44:40 PM PDT 24 97814561300 ps
T570 /workspace/coverage/default/6.sram_ctrl_max_throughput.2810619100 Jun 05 04:39:56 PM PDT 24 Jun 05 04:40:58 PM PDT 24 193647946 ps
T571 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4034125201 Jun 05 04:39:55 PM PDT 24 Jun 05 04:40:01 PM PDT 24 243370243 ps
T572 /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3332580689 Jun 05 04:41:19 PM PDT 24 Jun 05 04:45:16 PM PDT 24 10121921312 ps
T573 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3032800833 Jun 05 04:40:14 PM PDT 24 Jun 05 04:45:04 PM PDT 24 4179923697 ps
T574 /workspace/coverage/default/6.sram_ctrl_multiple_keys.476400138 Jun 05 04:39:55 PM PDT 24 Jun 05 04:41:42 PM PDT 24 810177102 ps
T575 /workspace/coverage/default/21.sram_ctrl_multiple_keys.3345084004 Jun 05 04:40:48 PM PDT 24 Jun 05 05:00:38 PM PDT 24 111722290432 ps
T576 /workspace/coverage/default/26.sram_ctrl_multiple_keys.2238530643 Jun 05 04:41:12 PM PDT 24 Jun 05 04:52:16 PM PDT 24 2559817659 ps
T20 /workspace/coverage/default/1.sram_ctrl_sec_cm.4244960739 Jun 05 04:39:36 PM PDT 24 Jun 05 04:39:39 PM PDT 24 182903290 ps
T577 /workspace/coverage/default/36.sram_ctrl_alert_test.2931217345 Jun 05 04:42:16 PM PDT 24 Jun 05 04:42:17 PM PDT 24 36238205 ps
T578 /workspace/coverage/default/19.sram_ctrl_stress_all.137104330 Jun 05 04:40:39 PM PDT 24 Jun 05 05:30:29 PM PDT 24 36151049315 ps
T579 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3988593637 Jun 05 04:39:31 PM PDT 24 Jun 05 04:57:30 PM PDT 24 3457088892 ps
T580 /workspace/coverage/default/43.sram_ctrl_bijection.587719532 Jun 05 04:43:04 PM PDT 24 Jun 05 04:43:43 PM PDT 24 4328635371 ps
T581 /workspace/coverage/default/34.sram_ctrl_alert_test.2907417483 Jun 05 04:42:11 PM PDT 24 Jun 05 04:42:12 PM PDT 24 17500436 ps
T582 /workspace/coverage/default/27.sram_ctrl_max_throughput.1044469731 Jun 05 04:41:21 PM PDT 24 Jun 05 04:42:05 PM PDT 24 186430646 ps
T583 /workspace/coverage/default/46.sram_ctrl_multiple_keys.3581604780 Jun 05 04:43:26 PM PDT 24 Jun 05 04:49:08 PM PDT 24 1455954164 ps
T584 /workspace/coverage/default/2.sram_ctrl_regwen.1659193266 Jun 05 04:39:36 PM PDT 24 Jun 05 05:09:29 PM PDT 24 11793461254 ps
T585 /workspace/coverage/default/37.sram_ctrl_bijection.1550766771 Jun 05 04:42:30 PM PDT 24 Jun 05 04:43:08 PM PDT 24 2180791331 ps
T586 /workspace/coverage/default/15.sram_ctrl_partial_access.4043437615 Jun 05 04:40:28 PM PDT 24 Jun 05 04:41:27 PM PDT 24 716433959 ps
T587 /workspace/coverage/default/20.sram_ctrl_bijection.1429102279 Jun 05 04:40:46 PM PDT 24 Jun 05 04:42:05 PM PDT 24 19829646618 ps
T588 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3239099735 Jun 05 04:40:25 PM PDT 24 Jun 05 04:46:32 PM PDT 24 11627162214 ps
T589 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2487876450 Jun 05 04:39:58 PM PDT 24 Jun 05 04:45:43 PM PDT 24 3758063200 ps
T590 /workspace/coverage/default/26.sram_ctrl_ram_cfg.245429110 Jun 05 04:41:18 PM PDT 24 Jun 05 04:41:19 PM PDT 24 27910077 ps
T591 /workspace/coverage/default/12.sram_ctrl_multiple_keys.3698670454 Jun 05 04:40:14 PM PDT 24 Jun 05 04:55:14 PM PDT 24 24322100586 ps
T592 /workspace/coverage/default/45.sram_ctrl_regwen.3725846114 Jun 05 04:43:27 PM PDT 24 Jun 05 04:49:17 PM PDT 24 1415767677 ps
T593 /workspace/coverage/default/44.sram_ctrl_executable.3477906097 Jun 05 04:43:24 PM PDT 24 Jun 05 05:05:31 PM PDT 24 2938914098 ps
T594 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2386566193 Jun 05 04:42:53 PM PDT 24 Jun 05 04:42:54 PM PDT 24 29533524 ps
T595 /workspace/coverage/default/28.sram_ctrl_partial_access.3034605059 Jun 05 04:41:28 PM PDT 24 Jun 05 04:41:38 PM PDT 24 182530424 ps
T596 /workspace/coverage/default/32.sram_ctrl_partial_access.512079588 Jun 05 04:41:46 PM PDT 24 Jun 05 04:42:01 PM PDT 24 265567620 ps
T597 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3982404291 Jun 05 04:40:25 PM PDT 24 Jun 05 04:42:26 PM PDT 24 1275026877 ps
T598 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3852989127 Jun 05 04:39:36 PM PDT 24 Jun 05 04:45:21 PM PDT 24 93337175139 ps
T599 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.656898934 Jun 05 04:39:48 PM PDT 24 Jun 05 04:57:50 PM PDT 24 4125867149 ps
T600 /workspace/coverage/default/5.sram_ctrl_bijection.2505310213 Jun 05 04:39:47 PM PDT 24 Jun 05 04:40:09 PM PDT 24 2045128404 ps
T601 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2102010929 Jun 05 04:41:34 PM PDT 24 Jun 05 04:41:46 PM PDT 24 153415987 ps
T602 /workspace/coverage/default/44.sram_ctrl_max_throughput.1027279537 Jun 05 04:43:23 PM PDT 24 Jun 05 04:43:26 PM PDT 24 47966850 ps
T603 /workspace/coverage/default/17.sram_ctrl_partial_access.1319163710 Jun 05 04:40:32 PM PDT 24 Jun 05 04:40:43 PM PDT 24 204873613 ps
T604 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.361185206 Jun 05 04:39:37 PM PDT 24 Jun 05 04:39:41 PM PDT 24 295547824 ps
T605 /workspace/coverage/default/13.sram_ctrl_ram_cfg.2418097676 Jun 05 04:40:12 PM PDT 24 Jun 05 04:40:13 PM PDT 24 45282848 ps
T606 /workspace/coverage/default/39.sram_ctrl_bijection.366911906 Jun 05 04:42:33 PM PDT 24 Jun 05 04:43:43 PM PDT 24 9474905201 ps
T607 /workspace/coverage/default/22.sram_ctrl_stress_pipeline.257221093 Jun 05 04:40:54 PM PDT 24 Jun 05 04:44:35 PM PDT 24 11260625304 ps
T608 /workspace/coverage/default/41.sram_ctrl_stress_all.3435893245 Jun 05 04:42:57 PM PDT 24 Jun 05 05:55:36 PM PDT 24 22155846458 ps
T609 /workspace/coverage/default/39.sram_ctrl_max_throughput.3208922755 Jun 05 04:42:35 PM PDT 24 Jun 05 04:43:32 PM PDT 24 103144663 ps
T610 /workspace/coverage/default/17.sram_ctrl_smoke.3597089981 Jun 05 04:40:31 PM PDT 24 Jun 05 04:40:41 PM PDT 24 846586104 ps
T611 /workspace/coverage/default/7.sram_ctrl_stress_all.3262302857 Jun 05 04:39:58 PM PDT 24 Jun 05 04:57:29 PM PDT 24 5263162323 ps
T612 /workspace/coverage/default/43.sram_ctrl_smoke.86397002 Jun 05 04:43:02 PM PDT 24 Jun 05 04:43:14 PM PDT 24 7886972403 ps
T613 /workspace/coverage/default/21.sram_ctrl_max_throughput.4197863641 Jun 05 04:40:49 PM PDT 24 Jun 05 04:42:14 PM PDT 24 239335208 ps
T614 /workspace/coverage/default/42.sram_ctrl_bijection.1275026835 Jun 05 04:42:57 PM PDT 24 Jun 05 04:44:12 PM PDT 24 2668565134 ps
T615 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.4252051970 Jun 05 04:40:13 PM PDT 24 Jun 05 04:47:33 PM PDT 24 63233575480 ps
T616 /workspace/coverage/default/12.sram_ctrl_executable.486161691 Jun 05 04:40:13 PM PDT 24 Jun 05 04:42:50 PM PDT 24 1275911111 ps
T617 /workspace/coverage/default/8.sram_ctrl_ram_cfg.3920601039 Jun 05 04:39:59 PM PDT 24 Jun 05 04:40:01 PM PDT 24 31709127 ps
T618 /workspace/coverage/default/32.sram_ctrl_alert_test.2934939172 Jun 05 04:41:52 PM PDT 24 Jun 05 04:41:53 PM PDT 24 32905753 ps
T619 /workspace/coverage/default/15.sram_ctrl_bijection.2052911342 Jun 05 04:40:23 PM PDT 24 Jun 05 04:41:12 PM PDT 24 4604940541 ps
T620 /workspace/coverage/default/3.sram_ctrl_stress_all.1482652573 Jun 05 04:39:47 PM PDT 24 Jun 05 05:05:35 PM PDT 24 145421147575 ps
T621 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2175403342 Jun 05 04:42:32 PM PDT 24 Jun 05 04:46:03 PM PDT 24 4459458322 ps
T622 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.123886089 Jun 05 04:39:30 PM PDT 24 Jun 05 04:39:36 PM PDT 24 70157028 ps
T623 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.4263589456 Jun 05 04:42:33 PM PDT 24 Jun 05 04:58:55 PM PDT 24 8001229245 ps
T624 /workspace/coverage/default/38.sram_ctrl_access_during_key_req.2416156399 Jun 05 04:42:32 PM PDT 24 Jun 05 04:58:39 PM PDT 24 17510542898 ps
T625 /workspace/coverage/default/38.sram_ctrl_partial_access.3776029741 Jun 05 04:42:32 PM PDT 24 Jun 05 04:42:47 PM PDT 24 1115291393 ps
T626 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2067447646 Jun 05 04:39:41 PM PDT 24 Jun 05 04:44:48 PM PDT 24 13711395980 ps
T627 /workspace/coverage/default/47.sram_ctrl_partial_access.3916614216 Jun 05 04:43:37 PM PDT 24 Jun 05 04:45:01 PM PDT 24 356721548 ps
T628 /workspace/coverage/default/24.sram_ctrl_smoke.4227936195 Jun 05 04:41:03 PM PDT 24 Jun 05 04:41:31 PM PDT 24 1326916650 ps
T629 /workspace/coverage/default/27.sram_ctrl_partial_access.853748895 Jun 05 04:41:18 PM PDT 24 Jun 05 04:41:47 PM PDT 24 1792094995 ps
T630 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3548357071 Jun 05 04:40:54 PM PDT 24 Jun 05 04:47:11 PM PDT 24 63420790549 ps
T631 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.4166469769 Jun 05 04:40:16 PM PDT 24 Jun 05 04:40:20 PM PDT 24 215840660 ps
T632 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2744093041 Jun 05 04:40:16 PM PDT 24 Jun 05 04:49:51 PM PDT 24 3850189662 ps
T633 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4267570966 Jun 05 04:40:10 PM PDT 24 Jun 05 04:40:14 PM PDT 24 181267496 ps
T634 /workspace/coverage/default/24.sram_ctrl_ram_cfg.3106425887 Jun 05 04:41:02 PM PDT 24 Jun 05 04:41:03 PM PDT 24 25636566 ps
T635 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1509400507 Jun 05 04:39:58 PM PDT 24 Jun 05 04:42:27 PM PDT 24 168516553 ps
T636 /workspace/coverage/default/2.sram_ctrl_max_throughput.1744927064 Jun 05 04:39:36 PM PDT 24 Jun 05 04:40:18 PM PDT 24 656231398 ps
T637 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.224915362 Jun 05 04:42:14 PM PDT 24 Jun 05 04:42:19 PM PDT 24 250302166 ps
T638 /workspace/coverage/default/11.sram_ctrl_stress_all.2955379329 Jun 05 04:40:14 PM PDT 24 Jun 05 05:48:32 PM PDT 24 264898208856 ps
T639 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.291072555 Jun 05 04:40:48 PM PDT 24 Jun 05 04:41:17 PM PDT 24 1027684023 ps
T640 /workspace/coverage/default/35.sram_ctrl_smoke.514810709 Jun 05 04:42:07 PM PDT 24 Jun 05 04:42:42 PM PDT 24 351408353 ps
T641 /workspace/coverage/default/20.sram_ctrl_smoke.137968932 Jun 05 04:40:47 PM PDT 24 Jun 05 04:43:20 PM PDT 24 656921757 ps
T642 /workspace/coverage/default/33.sram_ctrl_alert_test.3929148822 Jun 05 04:42:00 PM PDT 24 Jun 05 04:42:01 PM PDT 24 36922855 ps
T103 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3137716222 Jun 05 04:40:22 PM PDT 24 Jun 05 04:41:34 PM PDT 24 785620352 ps
T643 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.559733743 Jun 05 04:41:42 PM PDT 24 Jun 05 04:44:21 PM PDT 24 7257211538 ps
T644 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2870053995 Jun 05 04:39:54 PM PDT 24 Jun 05 04:42:01 PM PDT 24 484890612 ps
T645 /workspace/coverage/default/12.sram_ctrl_stress_all.2568774410 Jun 05 04:40:16 PM PDT 24 Jun 05 06:05:51 PM PDT 24 264684149739 ps
T646 /workspace/coverage/default/25.sram_ctrl_stress_all.182296138 Jun 05 04:41:12 PM PDT 24 Jun 05 05:21:47 PM PDT 24 83470694707 ps
T647 /workspace/coverage/default/3.sram_ctrl_lc_escalation.1605266568 Jun 05 04:39:35 PM PDT 24 Jun 05 04:39:36 PM PDT 24 143439995 ps
T648 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1456773965 Jun 05 04:40:30 PM PDT 24 Jun 05 05:06:27 PM PDT 24 4523073337 ps
T649 /workspace/coverage/default/49.sram_ctrl_alert_test.677042826 Jun 05 04:44:04 PM PDT 24 Jun 05 04:44:05 PM PDT 24 46711368 ps
T650 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3251364231 Jun 05 04:40:24 PM PDT 24 Jun 05 04:41:15 PM PDT 24 117428792 ps
T651 /workspace/coverage/default/19.sram_ctrl_alert_test.2116287779 Jun 05 04:40:48 PM PDT 24 Jun 05 04:40:50 PM PDT 24 13840614 ps
T652 /workspace/coverage/default/33.sram_ctrl_partial_access.1480371532 Jun 05 04:42:01 PM PDT 24 Jun 05 04:42:12 PM PDT 24 2073002390 ps
T653 /workspace/coverage/default/18.sram_ctrl_regwen.3912857361 Jun 05 04:40:40 PM PDT 24 Jun 05 05:08:11 PM PDT 24 107444990473 ps
T654 /workspace/coverage/default/5.sram_ctrl_executable.2731298525 Jun 05 04:39:46 PM PDT 24 Jun 05 04:54:48 PM PDT 24 12074160263 ps
T655 /workspace/coverage/default/27.sram_ctrl_bijection.3007523809 Jun 05 04:41:18 PM PDT 24 Jun 05 04:42:44 PM PDT 24 5585562669 ps
T656 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2357564592 Jun 05 04:40:16 PM PDT 24 Jun 05 04:43:17 PM PDT 24 7555862599 ps
T657 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2586538163 Jun 05 04:42:16 PM PDT 24 Jun 05 04:47:22 PM PDT 24 12703424519 ps
T658 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3391408791 Jun 05 04:40:37 PM PDT 24 Jun 05 04:40:40 PM PDT 24 43733777 ps
T659 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.769658744 Jun 05 04:40:03 PM PDT 24 Jun 05 04:40:06 PM PDT 24 151233001 ps
T660 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3634652652 Jun 05 04:42:42 PM PDT 24 Jun 05 04:45:08 PM PDT 24 7505053510 ps
T661 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1186866265 Jun 05 04:39:37 PM PDT 24 Jun 05 05:05:30 PM PDT 24 18441947232 ps
T662 /workspace/coverage/default/28.sram_ctrl_executable.1061375518 Jun 05 04:41:29 PM PDT 24 Jun 05 04:59:49 PM PDT 24 51655484200 ps
T663 /workspace/coverage/default/36.sram_ctrl_multiple_keys.795207596 Jun 05 04:42:14 PM PDT 24 Jun 05 04:49:17 PM PDT 24 54093962486 ps
T664 /workspace/coverage/default/33.sram_ctrl_executable.3225177689 Jun 05 04:42:01 PM PDT 24 Jun 05 04:47:18 PM PDT 24 1730856668 ps
T665 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3401345540 Jun 05 04:41:35 PM PDT 24 Jun 05 04:41:38 PM PDT 24 157920926 ps
T666 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2453503077 Jun 05 04:43:01 PM PDT 24 Jun 05 04:43:05 PM PDT 24 132499209 ps
T667 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.4063645185 Jun 05 04:43:13 PM PDT 24 Jun 05 04:47:21 PM PDT 24 2593118833 ps
T668 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.122735781 Jun 05 04:41:24 PM PDT 24 Jun 05 04:41:30 PM PDT 24 343228276 ps
T669 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2116314690 Jun 05 04:40:25 PM PDT 24 Jun 05 04:40:31 PM PDT 24 351178833 ps
T670 /workspace/coverage/default/48.sram_ctrl_lc_escalation.13526409 Jun 05 04:43:50 PM PDT 24 Jun 05 04:44:01 PM PDT 24 799307750 ps
T671 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.828429725 Jun 05 04:41:11 PM PDT 24 Jun 05 04:41:17 PM PDT 24 58097758 ps
T672 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.810371447 Jun 05 04:43:45 PM PDT 24 Jun 05 04:43:49 PM PDT 24 98221923 ps
T673 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3363689365 Jun 05 04:41:28 PM PDT 24 Jun 05 04:44:32 PM PDT 24 32523289409 ps
T674 /workspace/coverage/default/22.sram_ctrl_bijection.55266596 Jun 05 04:40:48 PM PDT 24 Jun 05 04:42:00 PM PDT 24 5138445865 ps
T675 /workspace/coverage/default/47.sram_ctrl_alert_test.3386816917 Jun 05 04:43:41 PM PDT 24 Jun 05 04:43:42 PM PDT 24 20437449 ps
T676 /workspace/coverage/default/3.sram_ctrl_alert_test.4148681969 Jun 05 04:39:45 PM PDT 24 Jun 05 04:39:47 PM PDT 24 43790291 ps
T677 /workspace/coverage/default/14.sram_ctrl_lc_escalation.3248958288 Jun 05 04:40:21 PM PDT 24 Jun 05 04:40:26 PM PDT 24 739874984 ps
T678 /workspace/coverage/default/19.sram_ctrl_mem_walk.3447292563 Jun 05 04:40:41 PM PDT 24 Jun 05 04:40:52 PM PDT 24 997079373 ps
T679 /workspace/coverage/default/49.sram_ctrl_max_throughput.3271053782 Jun 05 04:44:05 PM PDT 24 Jun 05 04:44:16 PM PDT 24 67288674 ps
T680 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.731459811 Jun 05 04:40:23 PM PDT 24 Jun 05 04:40:27 PM PDT 24 206442035 ps
T681 /workspace/coverage/default/15.sram_ctrl_executable.2398690574 Jun 05 04:40:25 PM PDT 24 Jun 05 05:00:43 PM PDT 24 35516253257 ps
T682 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.3067844241 Jun 05 04:41:53 PM PDT 24 Jun 05 04:41:59 PM PDT 24 173263541 ps
T683 /workspace/coverage/default/7.sram_ctrl_alert_test.700888465 Jun 05 04:39:58 PM PDT 24 Jun 05 04:40:00 PM PDT 24 33529275 ps
T684 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.728570371 Jun 05 04:41:42 PM PDT 24 Jun 05 04:45:52 PM PDT 24 3645955178 ps
T685 /workspace/coverage/default/4.sram_ctrl_executable.2487601006 Jun 05 04:39:45 PM PDT 24 Jun 05 04:42:34 PM PDT 24 4919312724 ps
T104 /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3303143426 Jun 05 04:40:29 PM PDT 24 Jun 05 04:40:37 PM PDT 24 218728319 ps
T686 /workspace/coverage/default/16.sram_ctrl_partial_access.2565936649 Jun 05 04:40:23 PM PDT 24 Jun 05 04:40:54 PM PDT 24 437102392 ps
T687 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.855845912 Jun 05 04:41:18 PM PDT 24 Jun 05 04:57:39 PM PDT 24 6047282924 ps
T688 /workspace/coverage/default/44.sram_ctrl_ram_cfg.1228896469 Jun 05 04:43:23 PM PDT 24 Jun 05 04:43:24 PM PDT 24 80654223 ps
T689 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.489183323 Jun 05 04:41:29 PM PDT 24 Jun 05 04:43:26 PM PDT 24 532514534 ps
T690 /workspace/coverage/default/44.sram_ctrl_smoke.2715629854 Jun 05 04:43:19 PM PDT 24 Jun 05 04:43:25 PM PDT 24 441381251 ps
T691 /workspace/coverage/default/26.sram_ctrl_stress_all.1317859000 Jun 05 04:41:20 PM PDT 24 Jun 05 04:47:46 PM PDT 24 22772026700 ps
T692 /workspace/coverage/default/1.sram_ctrl_stress_all.2530989405 Jun 05 04:39:36 PM PDT 24 Jun 05 05:31:23 PM PDT 24 174958864040 ps
T693 /workspace/coverage/default/1.sram_ctrl_smoke.146269837 Jun 05 04:39:28 PM PDT 24 Jun 05 04:39:38 PM PDT 24 1457417889 ps
T694 /workspace/coverage/default/11.sram_ctrl_multiple_keys.3704550308 Jun 05 04:40:05 PM PDT 24 Jun 05 04:48:30 PM PDT 24 44180647011 ps
T695 /workspace/coverage/default/47.sram_ctrl_stress_all.1415510827 Jun 05 04:43:41 PM PDT 24 Jun 05 05:37:57 PM PDT 24 37597793110 ps
T696 /workspace/coverage/default/49.sram_ctrl_smoke.3248179160 Jun 05 04:44:04 PM PDT 24 Jun 05 04:45:25 PM PDT 24 467903106 ps
T697 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1684912305 Jun 05 04:42:08 PM PDT 24 Jun 05 04:42:11 PM PDT 24 631277641 ps
T698 /workspace/coverage/default/23.sram_ctrl_max_throughput.3072738416 Jun 05 04:40:55 PM PDT 24 Jun 05 04:41:48 PM PDT 24 465418729 ps
T699 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3121894773 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:43 PM PDT 24 344663909 ps
T30 /workspace/coverage/default/4.sram_ctrl_sec_cm.3582575468 Jun 05 04:39:49 PM PDT 24 Jun 05 04:39:53 PM PDT 24 555241815 ps
T700 /workspace/coverage/default/16.sram_ctrl_mem_walk.1382028913 Jun 05 04:40:29 PM PDT 24 Jun 05 04:40:35 PM PDT 24 1362921390 ps
T701 /workspace/coverage/default/17.sram_ctrl_alert_test.3464733598 Jun 05 04:40:30 PM PDT 24 Jun 05 04:40:31 PM PDT 24 69095929 ps
T702 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1693929361 Jun 05 04:43:25 PM PDT 24 Jun 05 04:53:49 PM PDT 24 28331513451 ps
T703 /workspace/coverage/default/26.sram_ctrl_executable.3182227976 Jun 05 04:41:19 PM PDT 24 Jun 05 04:57:30 PM PDT 24 11983469992 ps
T704 /workspace/coverage/default/25.sram_ctrl_regwen.3154249731 Jun 05 04:41:10 PM PDT 24 Jun 05 04:50:51 PM PDT 24 20582930289 ps
T705 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2910941323 Jun 05 04:42:11 PM PDT 24 Jun 05 04:42:20 PM PDT 24 72532283 ps
T706 /workspace/coverage/default/33.sram_ctrl_smoke.2850833948 Jun 05 04:41:53 PM PDT 24 Jun 05 04:41:55 PM PDT 24 100106046 ps
T707 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.3317184583 Jun 05 04:39:57 PM PDT 24 Jun 05 04:43:56 PM PDT 24 5096545960 ps
T708 /workspace/coverage/default/33.sram_ctrl_lc_escalation.1333169307 Jun 05 04:42:02 PM PDT 24 Jun 05 04:42:10 PM PDT 24 940626032 ps
T709 /workspace/coverage/default/45.sram_ctrl_smoke.1066364345 Jun 05 04:43:23 PM PDT 24 Jun 05 04:43:29 PM PDT 24 658398452 ps
T710 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.925901640 Jun 05 04:40:15 PM PDT 24 Jun 05 04:42:50 PM PDT 24 1669756950 ps
T711 /workspace/coverage/default/22.sram_ctrl_alert_test.2047283771 Jun 05 04:40:58 PM PDT 24 Jun 05 04:40:59 PM PDT 24 14451146 ps
T712 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2210245506 Jun 05 04:39:47 PM PDT 24 Jun 05 04:39:51 PM PDT 24 302682383 ps
T713 /workspace/coverage/default/25.sram_ctrl_alert_test.2469291296 Jun 05 04:41:12 PM PDT 24 Jun 05 04:41:13 PM PDT 24 27561482 ps
T714 /workspace/coverage/default/22.sram_ctrl_executable.2651092389 Jun 05 04:40:56 PM PDT 24 Jun 05 04:55:07 PM PDT 24 62549581082 ps
T715 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.917558851 Jun 05 04:40:13 PM PDT 24 Jun 05 04:45:39 PM PDT 24 1919193082 ps
T716 /workspace/coverage/default/28.sram_ctrl_max_throughput.2968603351 Jun 05 04:41:26 PM PDT 24 Jun 05 04:43:20 PM PDT 24 167652797 ps
T717 /workspace/coverage/default/21.sram_ctrl_executable.2791828223 Jun 05 04:40:45 PM PDT 24 Jun 05 05:08:32 PM PDT 24 3084943961 ps
T718 /workspace/coverage/default/47.sram_ctrl_bijection.2420083725 Jun 05 04:43:42 PM PDT 24 Jun 05 04:44:32 PM PDT 24 1713028278 ps
T719 /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1403026053 Jun 05 04:43:42 PM PDT 24 Jun 05 04:59:43 PM PDT 24 3895042697 ps
T720 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.948743905 Jun 05 04:43:28 PM PDT 24 Jun 05 04:47:10 PM PDT 24 3372108556 ps
T721 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3414325316 Jun 05 04:42:38 PM PDT 24 Jun 05 04:42:42 PM PDT 24 96834046 ps
T105 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2685526752 Jun 05 04:41:32 PM PDT 24 Jun 05 04:44:51 PM PDT 24 2413642454 ps
T722 /workspace/coverage/default/45.sram_ctrl_lc_escalation.1775086025 Jun 05 04:43:29 PM PDT 24 Jun 05 04:43:35 PM PDT 24 1250267963 ps
T723 /workspace/coverage/default/47.sram_ctrl_multiple_keys.1361768382 Jun 05 04:43:37 PM PDT 24 Jun 05 04:59:28 PM PDT 24 30371984338 ps
T724 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4238743482 Jun 05 04:39:56 PM PDT 24 Jun 05 04:45:22 PM PDT 24 11645994533 ps
T725 /workspace/coverage/default/32.sram_ctrl_max_throughput.2548857155 Jun 05 04:41:44 PM PDT 24 Jun 05 04:43:22 PM PDT 24 502644695 ps
T726 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.375823253 Jun 05 04:39:49 PM PDT 24 Jun 05 04:40:04 PM PDT 24 492959425 ps
T727 /workspace/coverage/default/45.sram_ctrl_bijection.2790107877 Jun 05 04:43:29 PM PDT 24 Jun 05 04:44:20 PM PDT 24 798801717 ps
T728 /workspace/coverage/default/19.sram_ctrl_bijection.967056895 Jun 05 04:40:37 PM PDT 24 Jun 05 04:40:52 PM PDT 24 323335511 ps
T729 /workspace/coverage/default/11.sram_ctrl_alert_test.3004766693 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:16 PM PDT 24 20763618 ps
T730 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2075809587 Jun 05 04:42:09 PM PDT 24 Jun 05 04:58:29 PM PDT 24 3195301897 ps
T731 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2022328675 Jun 05 04:40:46 PM PDT 24 Jun 05 04:52:10 PM PDT 24 2519518615 ps
T732 /workspace/coverage/default/49.sram_ctrl_mem_walk.2208378633 Jun 05 04:44:06 PM PDT 24 Jun 05 04:44:11 PM PDT 24 640358112 ps
T733 /workspace/coverage/default/46.sram_ctrl_regwen.3916532141 Jun 05 04:43:36 PM PDT 24 Jun 05 04:57:51 PM PDT 24 7267763060 ps
T734 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2714920428 Jun 05 04:40:57 PM PDT 24 Jun 05 04:41:03 PM PDT 24 104559421 ps
T735 /workspace/coverage/default/29.sram_ctrl_lc_escalation.997922582 Jun 05 04:41:34 PM PDT 24 Jun 05 04:41:41 PM PDT 24 2626240315 ps
T736 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3915869661 Jun 05 04:43:28 PM PDT 24 Jun 05 04:48:04 PM PDT 24 1960473860 ps
T737 /workspace/coverage/default/5.sram_ctrl_multiple_keys.2253304182 Jun 05 04:39:50 PM PDT 24 Jun 05 04:53:12 PM PDT 24 2129235488 ps
T738 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1522227045 Jun 05 04:42:15 PM PDT 24 Jun 05 05:06:43 PM PDT 24 81989850882 ps
T739 /workspace/coverage/default/22.sram_ctrl_ram_cfg.4028048688 Jun 05 04:40:55 PM PDT 24 Jun 05 04:40:57 PM PDT 24 29500793 ps
T740 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.804148490 Jun 05 04:40:53 PM PDT 24 Jun 05 04:43:20 PM PDT 24 5174566250 ps
T741 /workspace/coverage/default/36.sram_ctrl_max_throughput.3449630459 Jun 05 04:42:14 PM PDT 24 Jun 05 04:42:34 PM PDT 24 321696332 ps
T742 /workspace/coverage/default/1.sram_ctrl_partial_access.1271343394 Jun 05 04:39:35 PM PDT 24 Jun 05 04:40:42 PM PDT 24 1036190046 ps
T743 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1840037265 Jun 05 04:41:01 PM PDT 24 Jun 05 04:57:02 PM PDT 24 4516986228 ps
T744 /workspace/coverage/default/16.sram_ctrl_ram_cfg.2719410258 Jun 05 04:40:29 PM PDT 24 Jun 05 04:40:31 PM PDT 24 48246277 ps
T745 /workspace/coverage/default/23.sram_ctrl_partial_access.97987799 Jun 05 04:40:57 PM PDT 24 Jun 05 04:41:47 PM PDT 24 1422746669 ps
T746 /workspace/coverage/default/25.sram_ctrl_executable.2508164984 Jun 05 04:41:10 PM PDT 24 Jun 05 05:00:57 PM PDT 24 16331579491 ps
T747 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.592908892 Jun 05 04:41:42 PM PDT 24 Jun 05 04:48:21 PM PDT 24 4209198460 ps
T748 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2839771623 Jun 05 04:43:51 PM PDT 24 Jun 05 05:08:54 PM PDT 24 5046511664 ps
T749 /workspace/coverage/default/8.sram_ctrl_stress_all.1299070815 Jun 05 04:39:59 PM PDT 24 Jun 05 06:03:26 PM PDT 24 240166983415 ps
T750 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3491756561 Jun 05 04:40:03 PM PDT 24 Jun 05 04:59:31 PM PDT 24 25412013084 ps
T751 /workspace/coverage/default/37.sram_ctrl_stress_all.321498037 Jun 05 04:42:36 PM PDT 24 Jun 05 05:17:00 PM PDT 24 32104952950 ps
T752 /workspace/coverage/default/47.sram_ctrl_max_throughput.1712190216 Jun 05 04:43:36 PM PDT 24 Jun 05 04:45:08 PM PDT 24 132655685 ps
T753 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2705738693 Jun 05 04:41:10 PM PDT 24 Jun 05 04:41:32 PM PDT 24 704965820 ps
T754 /workspace/coverage/default/49.sram_ctrl_partial_access.3088792264 Jun 05 04:44:04 PM PDT 24 Jun 05 04:44:25 PM PDT 24 4625639807 ps
T755 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2643311444 Jun 05 04:39:43 PM PDT 24 Jun 05 04:39:50 PM PDT 24 247577412 ps
T756 /workspace/coverage/default/6.sram_ctrl_stress_all.3125101263 Jun 05 04:39:55 PM PDT 24 Jun 05 05:09:35 PM PDT 24 101449506764 ps
T757 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.232407705 Jun 05 04:43:37 PM PDT 24 Jun 05 04:48:18 PM PDT 24 5891915444 ps
T758 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2546040610 Jun 05 04:43:20 PM PDT 24 Jun 05 04:44:56 PM PDT 24 2740738177 ps
T759 /workspace/coverage/default/15.sram_ctrl_multiple_keys.532606444 Jun 05 04:40:24 PM PDT 24 Jun 05 04:57:07 PM PDT 24 1892100582 ps
T760 /workspace/coverage/default/19.sram_ctrl_regwen.1140504591 Jun 05 04:40:44 PM PDT 24 Jun 05 04:45:15 PM PDT 24 48152458916 ps
T761 /workspace/coverage/default/13.sram_ctrl_regwen.2336426733 Jun 05 04:40:14 PM PDT 24 Jun 05 05:10:07 PM PDT 24 10316282202 ps
T762 /workspace/coverage/default/29.sram_ctrl_multiple_keys.610252385 Jun 05 04:41:27 PM PDT 24 Jun 05 04:47:25 PM PDT 24 1708205314 ps
T763 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2043984580 Jun 05 04:41:28 PM PDT 24 Jun 05 04:41:34 PM PDT 24 208684909 ps
T764 /workspace/coverage/default/46.sram_ctrl_smoke.2462665191 Jun 05 04:43:28 PM PDT 24 Jun 05 04:44:44 PM PDT 24 156858524 ps
T765 /workspace/coverage/default/9.sram_ctrl_smoke.604669483 Jun 05 04:39:57 PM PDT 24 Jun 05 04:42:02 PM PDT 24 738707901 ps
T766 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2108765720 Jun 05 04:41:59 PM PDT 24 Jun 05 04:51:43 PM PDT 24 14661401929 ps
T767 /workspace/coverage/default/40.sram_ctrl_partial_access.1070870419 Jun 05 04:42:41 PM PDT 24 Jun 05 04:43:31 PM PDT 24 655706560 ps
T768 /workspace/coverage/default/12.sram_ctrl_bijection.2417976150 Jun 05 04:40:13 PM PDT 24 Jun 05 04:41:53 PM PDT 24 82115848927 ps
T769 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1590273563 Jun 05 04:42:57 PM PDT 24 Jun 05 04:43:27 PM PDT 24 314829362 ps
T770 /workspace/coverage/default/6.sram_ctrl_mem_walk.2983998091 Jun 05 04:39:55 PM PDT 24 Jun 05 04:40:05 PM PDT 24 140544540 ps
T771 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3885396968 Jun 05 04:40:14 PM PDT 24 Jun 05 04:44:54 PM PDT 24 9541840362 ps
T772 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3285641446 Jun 05 04:42:57 PM PDT 24 Jun 05 04:54:57 PM PDT 24 11855620156 ps
T773 /workspace/coverage/default/2.sram_ctrl_partial_access.1696634493 Jun 05 04:39:37 PM PDT 24 Jun 05 04:41:34 PM PDT 24 683479501 ps
T774 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2496132186 Jun 05 04:39:48 PM PDT 24 Jun 05 04:45:37 PM PDT 24 6890012041 ps
T775 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1111171497 Jun 05 04:43:53 PM PDT 24 Jun 05 04:43:57 PM PDT 24 181370346 ps
T776 /workspace/coverage/default/24.sram_ctrl_max_throughput.2156280914 Jun 05 04:41:02 PM PDT 24 Jun 05 04:41:06 PM PDT 24 57260208 ps
T777 /workspace/coverage/default/44.sram_ctrl_bijection.3519276197 Jun 05 04:43:21 PM PDT 24 Jun 05 04:44:27 PM PDT 24 8907962838 ps
T778 /workspace/coverage/default/16.sram_ctrl_bijection.3902592462 Jun 05 04:40:23 PM PDT 24 Jun 05 04:40:47 PM PDT 24 366681432 ps
T779 /workspace/coverage/default/36.sram_ctrl_regwen.767222049 Jun 05 04:42:16 PM PDT 24 Jun 05 04:57:26 PM PDT 24 132943720621 ps
T780 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1190084589 Jun 05 04:39:48 PM PDT 24 Jun 05 04:51:11 PM PDT 24 27005088272 ps
T781 /workspace/coverage/default/11.sram_ctrl_regwen.4115697672 Jun 05 04:40:14 PM PDT 24 Jun 05 04:42:32 PM PDT 24 7937155645 ps
T782 /workspace/coverage/default/45.sram_ctrl_stress_all.1659201152 Jun 05 04:43:30 PM PDT 24 Jun 05 05:29:15 PM PDT 24 111969549676 ps
T783 /workspace/coverage/default/17.sram_ctrl_mem_walk.2897528690 Jun 05 04:40:31 PM PDT 24 Jun 05 04:40:40 PM PDT 24 928121610 ps
T784 /workspace/coverage/default/25.sram_ctrl_mem_walk.31646704 Jun 05 04:41:10 PM PDT 24 Jun 05 04:41:16 PM PDT 24 142283978 ps
T785 /workspace/coverage/default/37.sram_ctrl_alert_test.1116232328 Jun 05 04:42:32 PM PDT 24 Jun 05 04:42:33 PM PDT 24 159769389 ps
T786 /workspace/coverage/default/27.sram_ctrl_mem_walk.4217227893 Jun 05 04:41:17 PM PDT 24 Jun 05 04:41:29 PM PDT 24 5068277425 ps
T787 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3583495003 Jun 05 04:40:09 PM PDT 24 Jun 05 04:40:23 PM PDT 24 352248991 ps
T788 /workspace/coverage/default/39.sram_ctrl_multiple_keys.84033128 Jun 05 04:42:32 PM PDT 24 Jun 05 04:52:22 PM PDT 24 10773378475 ps
T789 /workspace/coverage/default/27.sram_ctrl_smoke.3292685977 Jun 05 04:41:18 PM PDT 24 Jun 05 04:41:33 PM PDT 24 638313450 ps
T790 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1471824082 Jun 05 04:41:28 PM PDT 24 Jun 05 04:47:11 PM PDT 24 4701175230 ps
T791 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2854512248 Jun 05 04:43:51 PM PDT 24 Jun 05 04:44:38 PM PDT 24 440047960 ps
T792 /workspace/coverage/default/38.sram_ctrl_ram_cfg.995333157 Jun 05 04:42:37 PM PDT 24 Jun 05 04:42:38 PM PDT 24 75819447 ps
T106 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1027593795 Jun 05 04:40:15 PM PDT 24 Jun 05 04:40:20 PM PDT 24 556108008 ps
T793 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.940773841 Jun 05 04:39:57 PM PDT 24 Jun 05 04:54:21 PM PDT 24 3591186672 ps
T794 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.4199963549 Jun 05 04:40:17 PM PDT 24 Jun 05 04:57:09 PM PDT 24 20246698051 ps
T795 /workspace/coverage/default/35.sram_ctrl_alert_test.956615279 Jun 05 04:42:14 PM PDT 24 Jun 05 04:42:15 PM PDT 24 13975391 ps
T796 /workspace/coverage/default/29.sram_ctrl_ram_cfg.2565176444 Jun 05 04:41:35 PM PDT 24 Jun 05 04:41:36 PM PDT 24 157559928 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%