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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.21 99.18 95.17 100.00 100.00 96.12 99.56 97.44


Total test records in report: 1019
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T797 /workspace/coverage/default/27.sram_ctrl_multiple_keys.3268705249 Jun 05 04:41:18 PM PDT 24 Jun 05 04:45:07 PM PDT 24 5738403021 ps
T798 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.4203860864 Jun 05 04:43:28 PM PDT 24 Jun 05 04:47:14 PM PDT 24 15444193385 ps
T799 /workspace/coverage/default/23.sram_ctrl_smoke.3717738123 Jun 05 04:40:55 PM PDT 24 Jun 05 04:41:13 PM PDT 24 658185106 ps
T800 /workspace/coverage/default/20.sram_ctrl_access_during_key_req.885008223 Jun 05 04:40:46 PM PDT 24 Jun 05 04:50:09 PM PDT 24 2164764812 ps
T801 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3877721790 Jun 05 04:39:54 PM PDT 24 Jun 05 04:56:44 PM PDT 24 36272249103 ps
T802 /workspace/coverage/default/10.sram_ctrl_alert_test.2150319975 Jun 05 04:40:03 PM PDT 24 Jun 05 04:40:05 PM PDT 24 42257460 ps
T803 /workspace/coverage/default/1.sram_ctrl_lc_escalation.744502254 Jun 05 04:39:36 PM PDT 24 Jun 05 04:39:41 PM PDT 24 522118155 ps
T804 /workspace/coverage/default/5.sram_ctrl_regwen.1491470970 Jun 05 04:39:46 PM PDT 24 Jun 05 04:49:55 PM PDT 24 13921584760 ps
T805 /workspace/coverage/default/23.sram_ctrl_multiple_keys.1081300014 Jun 05 04:41:01 PM PDT 24 Jun 05 04:53:06 PM PDT 24 2508273986 ps
T806 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.198654219 Jun 05 04:42:42 PM PDT 24 Jun 05 04:53:32 PM PDT 24 13958018666 ps
T807 /workspace/coverage/default/31.sram_ctrl_mem_walk.3849849314 Jun 05 04:41:42 PM PDT 24 Jun 05 04:41:47 PM PDT 24 298786038 ps
T808 /workspace/coverage/default/36.sram_ctrl_stress_all.2685175230 Jun 05 04:42:16 PM PDT 24 Jun 05 05:13:00 PM PDT 24 144769943830 ps
T809 /workspace/coverage/default/11.sram_ctrl_executable.1761596123 Jun 05 04:40:05 PM PDT 24 Jun 05 05:00:11 PM PDT 24 14340359518 ps
T810 /workspace/coverage/default/24.sram_ctrl_mem_walk.277217519 Jun 05 04:41:11 PM PDT 24 Jun 05 04:41:18 PM PDT 24 345079104 ps
T811 /workspace/coverage/default/9.sram_ctrl_bijection.2882585533 Jun 05 04:39:56 PM PDT 24 Jun 05 04:41:03 PM PDT 24 2188925507 ps
T812 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3121116805 Jun 05 04:40:06 PM PDT 24 Jun 05 04:45:30 PM PDT 24 50315936139 ps
T813 /workspace/coverage/default/29.sram_ctrl_max_throughput.3988176914 Jun 05 04:41:33 PM PDT 24 Jun 05 04:42:06 PM PDT 24 737254067 ps
T814 /workspace/coverage/default/21.sram_ctrl_bijection.2580779136 Jun 05 04:40:47 PM PDT 24 Jun 05 04:42:10 PM PDT 24 5511970265 ps
T815 /workspace/coverage/default/13.sram_ctrl_partial_access.1748881455 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:50 PM PDT 24 356992735 ps
T816 /workspace/coverage/default/18.sram_ctrl_smoke.4079097445 Jun 05 04:40:31 PM PDT 24 Jun 05 04:41:02 PM PDT 24 443295476 ps
T817 /workspace/coverage/default/17.sram_ctrl_max_throughput.1531241381 Jun 05 04:40:30 PM PDT 24 Jun 05 04:41:53 PM PDT 24 215175223 ps
T31 /workspace/coverage/default/2.sram_ctrl_sec_cm.1508225056 Jun 05 04:39:42 PM PDT 24 Jun 05 04:39:46 PM PDT 24 678845175 ps
T818 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3946319502 Jun 05 04:41:34 PM PDT 24 Jun 05 04:42:11 PM PDT 24 759608192 ps
T819 /workspace/coverage/default/13.sram_ctrl_bijection.1977997767 Jun 05 04:40:14 PM PDT 24 Jun 05 04:41:27 PM PDT 24 17322705278 ps
T820 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2864946405 Jun 05 04:40:03 PM PDT 24 Jun 05 05:09:38 PM PDT 24 18322964587 ps
T821 /workspace/coverage/default/49.sram_ctrl_regwen.2595477876 Jun 05 04:44:03 PM PDT 24 Jun 05 04:51:16 PM PDT 24 23826896545 ps
T822 /workspace/coverage/default/32.sram_ctrl_smoke.1738210704 Jun 05 04:41:45 PM PDT 24 Jun 05 04:41:48 PM PDT 24 257402896 ps
T823 /workspace/coverage/default/15.sram_ctrl_max_throughput.4201751326 Jun 05 04:40:27 PM PDT 24 Jun 05 04:41:22 PM PDT 24 114285629 ps
T824 /workspace/coverage/default/30.sram_ctrl_max_throughput.3204490870 Jun 05 04:41:32 PM PDT 24 Jun 05 04:41:44 PM PDT 24 103112148 ps
T825 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1179922151 Jun 05 04:41:35 PM PDT 24 Jun 05 04:46:13 PM PDT 24 7447921638 ps
T826 /workspace/coverage/default/31.sram_ctrl_smoke.1661477859 Jun 05 04:41:43 PM PDT 24 Jun 05 04:41:55 PM PDT 24 637017851 ps
T827 /workspace/coverage/default/39.sram_ctrl_stress_all.1989759081 Jun 05 04:42:40 PM PDT 24 Jun 05 05:34:24 PM PDT 24 46094631385 ps
T828 /workspace/coverage/default/27.sram_ctrl_executable.266381446 Jun 05 04:41:19 PM PDT 24 Jun 05 05:17:13 PM PDT 24 48451671522 ps
T829 /workspace/coverage/default/41.sram_ctrl_ram_cfg.2323173060 Jun 05 04:42:56 PM PDT 24 Jun 05 04:42:57 PM PDT 24 28168722 ps
T830 /workspace/coverage/default/36.sram_ctrl_ram_cfg.69355642 Jun 05 04:42:14 PM PDT 24 Jun 05 04:42:15 PM PDT 24 27595193 ps
T831 /workspace/coverage/default/45.sram_ctrl_multiple_keys.3419393672 Jun 05 04:43:19 PM PDT 24 Jun 05 04:51:22 PM PDT 24 1586564516 ps
T832 /workspace/coverage/default/0.sram_ctrl_mem_walk.2199667257 Jun 05 04:39:30 PM PDT 24 Jun 05 04:39:41 PM PDT 24 2600663985 ps
T833 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1057300626 Jun 05 04:43:28 PM PDT 24 Jun 05 04:46:03 PM PDT 24 1699018937 ps
T834 /workspace/coverage/default/40.sram_ctrl_max_throughput.1360229518 Jun 05 04:42:43 PM PDT 24 Jun 05 04:42:52 PM PDT 24 112357005 ps
T835 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1418497594 Jun 05 04:41:12 PM PDT 24 Jun 05 04:55:28 PM PDT 24 10153548963 ps
T836 /workspace/coverage/default/4.sram_ctrl_mem_walk.1624239940 Jun 05 04:39:46 PM PDT 24 Jun 05 04:39:53 PM PDT 24 890499632 ps
T837 /workspace/coverage/default/20.sram_ctrl_multiple_keys.1284951414 Jun 05 04:40:46 PM PDT 24 Jun 05 04:59:01 PM PDT 24 85045854189 ps
T838 /workspace/coverage/default/7.sram_ctrl_ram_cfg.420499681 Jun 05 04:39:57 PM PDT 24 Jun 05 04:39:59 PM PDT 24 29094178 ps
T839 /workspace/coverage/default/43.sram_ctrl_partial_access.3632808999 Jun 05 04:43:11 PM PDT 24 Jun 05 04:43:24 PM PDT 24 612245416 ps
T840 /workspace/coverage/default/6.sram_ctrl_bijection.49230753 Jun 05 04:40:00 PM PDT 24 Jun 05 04:40:30 PM PDT 24 1320932823 ps
T841 /workspace/coverage/default/29.sram_ctrl_executable.2706194557 Jun 05 04:41:35 PM PDT 24 Jun 05 05:12:39 PM PDT 24 41173257344 ps
T842 /workspace/coverage/default/32.sram_ctrl_bijection.1734718754 Jun 05 04:41:41 PM PDT 24 Jun 05 04:42:41 PM PDT 24 1669394911 ps
T843 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1309808448 Jun 05 04:39:53 PM PDT 24 Jun 05 04:44:36 PM PDT 24 18886299590 ps
T844 /workspace/coverage/default/33.sram_ctrl_stress_all.2077672056 Jun 05 04:42:01 PM PDT 24 Jun 05 04:52:54 PM PDT 24 4627391270 ps
T845 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1236283318 Jun 05 04:41:11 PM PDT 24 Jun 05 04:48:23 PM PDT 24 72061022831 ps
T846 /workspace/coverage/default/0.sram_ctrl_max_throughput.2084367066 Jun 05 04:39:28 PM PDT 24 Jun 05 04:40:26 PM PDT 24 117180106 ps
T847 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4276623309 Jun 05 04:39:54 PM PDT 24 Jun 05 04:51:37 PM PDT 24 5397420508 ps
T848 /workspace/coverage/default/37.sram_ctrl_partial_access.3896456873 Jun 05 04:42:32 PM PDT 24 Jun 05 04:43:44 PM PDT 24 2292433551 ps
T849 /workspace/coverage/default/34.sram_ctrl_lc_escalation.4017385494 Jun 05 04:42:06 PM PDT 24 Jun 05 04:42:11 PM PDT 24 697836847 ps
T850 /workspace/coverage/default/37.sram_ctrl_regwen.3586150131 Jun 05 04:42:34 PM PDT 24 Jun 05 04:51:05 PM PDT 24 9418471951 ps
T851 /workspace/coverage/default/0.sram_ctrl_partial_access.3333647849 Jun 05 04:39:29 PM PDT 24 Jun 05 04:39:40 PM PDT 24 210356647 ps
T852 /workspace/coverage/default/43.sram_ctrl_regwen.4139680347 Jun 05 04:43:12 PM PDT 24 Jun 05 05:03:01 PM PDT 24 16009610552 ps
T853 /workspace/coverage/default/28.sram_ctrl_stress_all.1916030964 Jun 05 04:41:25 PM PDT 24 Jun 05 05:01:02 PM PDT 24 54990162516 ps
T854 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2906142681 Jun 05 04:42:41 PM PDT 24 Jun 05 04:50:30 PM PDT 24 7198940109 ps
T855 /workspace/coverage/default/37.sram_ctrl_smoke.1214584194 Jun 05 04:42:33 PM PDT 24 Jun 05 04:42:36 PM PDT 24 136586322 ps
T856 /workspace/coverage/default/22.sram_ctrl_mem_walk.343297231 Jun 05 04:40:54 PM PDT 24 Jun 05 04:41:05 PM PDT 24 202895211 ps
T857 /workspace/coverage/default/16.sram_ctrl_alert_test.2806919531 Jun 05 04:40:31 PM PDT 24 Jun 05 04:40:33 PM PDT 24 39285817 ps
T858 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1541949830 Jun 05 04:43:29 PM PDT 24 Jun 05 04:43:30 PM PDT 24 87657760 ps
T859 /workspace/coverage/default/30.sram_ctrl_executable.4062971209 Jun 05 04:41:35 PM PDT 24 Jun 05 04:48:59 PM PDT 24 1002807679 ps
T860 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2756587393 Jun 05 04:42:37 PM PDT 24 Jun 05 04:43:40 PM PDT 24 274333556 ps
T861 /workspace/coverage/default/23.sram_ctrl_lc_escalation.425823430 Jun 05 04:40:56 PM PDT 24 Jun 05 04:41:00 PM PDT 24 298428457 ps
T862 /workspace/coverage/default/15.sram_ctrl_smoke.2612127198 Jun 05 04:40:26 PM PDT 24 Jun 05 04:40:28 PM PDT 24 31033248 ps
T863 /workspace/coverage/default/22.sram_ctrl_max_throughput.3071244434 Jun 05 04:40:53 PM PDT 24 Jun 05 04:42:13 PM PDT 24 352404520 ps
T864 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2837709209 Jun 05 04:41:33 PM PDT 24 Jun 05 04:47:06 PM PDT 24 3244767855 ps
T865 /workspace/coverage/default/13.sram_ctrl_smoke.4141498 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:19 PM PDT 24 70055471 ps
T866 /workspace/coverage/default/44.sram_ctrl_regwen.4100650949 Jun 05 04:43:23 PM PDT 24 Jun 05 04:57:22 PM PDT 24 16022820025 ps
T867 /workspace/coverage/default/34.sram_ctrl_stress_all.1608796010 Jun 05 04:42:07 PM PDT 24 Jun 05 05:22:29 PM PDT 24 51515148769 ps
T868 /workspace/coverage/default/42.sram_ctrl_executable.3512630399 Jun 05 04:43:04 PM PDT 24 Jun 05 04:48:02 PM PDT 24 4961082788 ps
T869 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1252783457 Jun 05 04:42:09 PM PDT 24 Jun 05 04:43:21 PM PDT 24 8182649135 ps
T870 /workspace/coverage/default/1.sram_ctrl_alert_test.2864820028 Jun 05 04:39:38 PM PDT 24 Jun 05 04:39:39 PM PDT 24 11921227 ps
T871 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1235104710 Jun 05 04:42:47 PM PDT 24 Jun 05 04:42:56 PM PDT 24 483287406 ps
T872 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.451715693 Jun 05 04:40:03 PM PDT 24 Jun 05 04:45:28 PM PDT 24 3534250476 ps
T873 /workspace/coverage/default/43.sram_ctrl_mem_walk.3882728971 Jun 05 04:43:12 PM PDT 24 Jun 05 04:43:22 PM PDT 24 248369159 ps
T874 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.668358301 Jun 05 04:43:11 PM PDT 24 Jun 05 05:04:12 PM PDT 24 72730281113 ps
T875 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2102648850 Jun 05 04:41:24 PM PDT 24 Jun 05 04:41:27 PM PDT 24 75551080 ps
T876 /workspace/coverage/default/46.sram_ctrl_executable.4290362408 Jun 05 04:43:35 PM PDT 24 Jun 05 05:09:02 PM PDT 24 16770758502 ps
T877 /workspace/coverage/default/18.sram_ctrl_stress_all.890419996 Jun 05 04:40:38 PM PDT 24 Jun 05 05:27:00 PM PDT 24 92833400933 ps
T878 /workspace/coverage/default/18.sram_ctrl_max_throughput.3138357145 Jun 05 04:40:38 PM PDT 24 Jun 05 04:41:06 PM PDT 24 176489662 ps
T879 /workspace/coverage/default/43.sram_ctrl_alert_test.1332199434 Jun 05 04:43:20 PM PDT 24 Jun 05 04:43:22 PM PDT 24 10660433 ps
T880 /workspace/coverage/default/32.sram_ctrl_lc_escalation.1875154383 Jun 05 04:41:51 PM PDT 24 Jun 05 04:41:59 PM PDT 24 2111012435 ps
T881 /workspace/coverage/default/31.sram_ctrl_regwen.3753483413 Jun 05 04:41:42 PM PDT 24 Jun 05 05:04:08 PM PDT 24 12498684909 ps
T882 /workspace/coverage/default/38.sram_ctrl_alert_test.2834572202 Jun 05 04:42:37 PM PDT 24 Jun 05 04:42:39 PM PDT 24 32763173 ps
T883 /workspace/coverage/default/41.sram_ctrl_bijection.1267197732 Jun 05 04:42:49 PM PDT 24 Jun 05 04:44:11 PM PDT 24 4924824671 ps
T884 /workspace/coverage/default/28.sram_ctrl_smoke.3351088156 Jun 05 04:41:29 PM PDT 24 Jun 05 04:41:41 PM PDT 24 2234556882 ps
T885 /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1389545793 Jun 05 04:40:37 PM PDT 24 Jun 05 04:42:50 PM PDT 24 5424894876 ps
T886 /workspace/coverage/default/39.sram_ctrl_lc_escalation.3708793444 Jun 05 04:42:32 PM PDT 24 Jun 05 04:42:37 PM PDT 24 912225160 ps
T887 /workspace/coverage/default/18.sram_ctrl_lc_escalation.8462955 Jun 05 04:40:42 PM PDT 24 Jun 05 04:40:47 PM PDT 24 459818169 ps
T888 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.25438416 Jun 05 04:40:02 PM PDT 24 Jun 05 04:44:45 PM PDT 24 2090454445 ps
T889 /workspace/coverage/default/14.sram_ctrl_bijection.425668822 Jun 05 04:40:13 PM PDT 24 Jun 05 04:41:12 PM PDT 24 12444866804 ps
T890 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2844000401 Jun 05 04:39:47 PM PDT 24 Jun 05 04:44:38 PM PDT 24 2926019979 ps
T891 /workspace/coverage/default/18.sram_ctrl_executable.2476823847 Jun 05 04:40:39 PM PDT 24 Jun 05 04:51:33 PM PDT 24 109271502974 ps
T892 /workspace/coverage/default/16.sram_ctrl_regwen.952470686 Jun 05 04:40:30 PM PDT 24 Jun 05 05:13:48 PM PDT 24 19814858662 ps
T893 /workspace/coverage/default/12.sram_ctrl_smoke.3538741854 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:29 PM PDT 24 249697230 ps
T894 /workspace/coverage/default/40.sram_ctrl_executable.410112077 Jun 05 04:42:46 PM PDT 24 Jun 05 04:48:41 PM PDT 24 20640651168 ps
T895 /workspace/coverage/default/6.sram_ctrl_regwen.3381355880 Jun 05 04:39:55 PM PDT 24 Jun 05 05:07:21 PM PDT 24 16672247425 ps
T896 /workspace/coverage/default/8.sram_ctrl_partial_access.593129223 Jun 05 04:39:55 PM PDT 24 Jun 05 04:40:34 PM PDT 24 1104277649 ps
T897 /workspace/coverage/default/32.sram_ctrl_stress_all.817361850 Jun 05 04:41:53 PM PDT 24 Jun 05 05:41:29 PM PDT 24 11044749361 ps
T898 /workspace/coverage/default/12.sram_ctrl_max_throughput.3763613045 Jun 05 04:40:13 PM PDT 24 Jun 05 04:41:53 PM PDT 24 539217094 ps
T899 /workspace/coverage/default/7.sram_ctrl_mem_walk.924395791 Jun 05 04:39:54 PM PDT 24 Jun 05 04:40:06 PM PDT 24 1995049367 ps
T900 /workspace/coverage/default/40.sram_ctrl_mem_walk.532853303 Jun 05 04:42:52 PM PDT 24 Jun 05 04:42:58 PM PDT 24 231409977 ps
T901 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2676519172 Jun 05 04:40:02 PM PDT 24 Jun 05 04:41:49 PM PDT 24 1455036978 ps
T902 /workspace/coverage/default/21.sram_ctrl_ram_cfg.16958482 Jun 05 04:40:47 PM PDT 24 Jun 05 04:40:49 PM PDT 24 85888432 ps
T903 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2745728519 Jun 05 04:39:58 PM PDT 24 Jun 05 04:42:53 PM PDT 24 3089982609 ps
T904 /workspace/coverage/default/33.sram_ctrl_mem_walk.2630369506 Jun 05 04:42:01 PM PDT 24 Jun 05 04:42:12 PM PDT 24 780813620 ps
T905 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.702864726 Jun 05 04:41:01 PM PDT 24 Jun 05 04:41:05 PM PDT 24 89881207 ps
T906 /workspace/coverage/default/48.sram_ctrl_alert_test.964552814 Jun 05 04:44:02 PM PDT 24 Jun 05 04:44:03 PM PDT 24 28177592 ps
T907 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.919228018 Jun 05 04:39:46 PM PDT 24 Jun 05 05:00:02 PM PDT 24 3673553972 ps
T908 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1202752481 Jun 05 04:39:28 PM PDT 24 Jun 05 04:40:46 PM PDT 24 368665044 ps
T909 /workspace/coverage/default/7.sram_ctrl_executable.1981019125 Jun 05 04:39:56 PM PDT 24 Jun 05 04:52:44 PM PDT 24 24879701788 ps
T910 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.912892397 Jun 05 04:42:48 PM PDT 24 Jun 05 04:48:13 PM PDT 24 13476577374 ps
T911 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3395470587 Jun 05 04:42:35 PM PDT 24 Jun 05 04:45:08 PM PDT 24 1571895466 ps
T912 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1589036343 Jun 05 04:40:14 PM PDT 24 Jun 05 04:40:20 PM PDT 24 1173635291 ps
T913 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3640278573 Jun 05 04:39:46 PM PDT 24 Jun 05 04:48:16 PM PDT 24 90994911750 ps
T914 /workspace/coverage/default/33.sram_ctrl_bijection.176130287 Jun 05 04:42:00 PM PDT 24 Jun 05 04:42:44 PM PDT 24 645203092 ps
T915 /workspace/coverage/default/39.sram_ctrl_alert_test.1482922879 Jun 05 04:42:41 PM PDT 24 Jun 05 04:42:43 PM PDT 24 46908210 ps
T916 /workspace/coverage/default/35.sram_ctrl_max_throughput.3384022135 Jun 05 04:42:08 PM PDT 24 Jun 05 04:42:14 PM PDT 24 153722800 ps
T917 /workspace/coverage/default/36.sram_ctrl_executable.826242233 Jun 05 04:42:14 PM PDT 24 Jun 05 04:43:35 PM PDT 24 16418732629 ps
T918 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1396313780 Jun 05 04:40:37 PM PDT 24 Jun 05 04:48:54 PM PDT 24 19465657762 ps
T919 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1204460320 Jun 05 04:41:18 PM PDT 24 Jun 05 04:49:08 PM PDT 24 1993447136 ps
T920 /workspace/coverage/default/28.sram_ctrl_multiple_keys.4265387392 Jun 05 04:41:27 PM PDT 24 Jun 05 04:46:29 PM PDT 24 2438208123 ps
T921 /workspace/coverage/default/46.sram_ctrl_partial_access.1826473910 Jun 05 04:43:30 PM PDT 24 Jun 05 04:43:50 PM PDT 24 4860394966 ps
T922 /workspace/coverage/default/18.sram_ctrl_alert_test.1366878510 Jun 05 04:40:38 PM PDT 24 Jun 05 04:40:39 PM PDT 24 14803735 ps
T923 /workspace/coverage/default/11.sram_ctrl_max_throughput.1517222980 Jun 05 04:40:03 PM PDT 24 Jun 05 04:40:09 PM PDT 24 68898279 ps
T924 /workspace/coverage/default/47.sram_ctrl_ram_cfg.1215838684 Jun 05 04:43:42 PM PDT 24 Jun 05 04:43:43 PM PDT 24 30597127 ps
T925 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2772333481 Jun 05 04:42:19 PM PDT 24 Jun 05 05:00:47 PM PDT 24 9553598175 ps
T926 /workspace/coverage/default/24.sram_ctrl_lc_escalation.1941740644 Jun 05 04:41:00 PM PDT 24 Jun 05 04:41:07 PM PDT 24 597449568 ps
T927 /workspace/coverage/default/39.sram_ctrl_partial_access.414963467 Jun 05 04:42:36 PM PDT 24 Jun 05 04:42:57 PM PDT 24 1093725065 ps
T928 /workspace/coverage/default/45.sram_ctrl_max_throughput.4206205771 Jun 05 04:43:29 PM PDT 24 Jun 05 04:43:48 PM PDT 24 252309273 ps
T929 /workspace/coverage/default/5.sram_ctrl_ram_cfg.2774422247 Jun 05 04:39:47 PM PDT 24 Jun 05 04:39:49 PM PDT 24 121628333 ps
T930 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4155496206 Jun 05 04:41:19 PM PDT 24 Jun 05 04:45:33 PM PDT 24 1116850129 ps
T931 /workspace/coverage/default/30.sram_ctrl_ram_cfg.392719942 Jun 05 04:41:33 PM PDT 24 Jun 05 04:41:34 PM PDT 24 75487136 ps
T932 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2612199844 Jun 05 04:44:02 PM PDT 24 Jun 05 04:44:06 PM PDT 24 103449686 ps
T62 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.899102490 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:44 PM PDT 24 45950050 ps
T57 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2038785857 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:04 PM PDT 24 611798714 ps
T63 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1688574319 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 16411150 ps
T73 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1672229124 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:52 PM PDT 24 3269198209 ps
T92 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3408770471 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:50 PM PDT 24 31160103 ps
T74 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1755436365 Jun 05 04:34:09 PM PDT 24 Jun 05 04:34:11 PM PDT 24 46537424 ps
T101 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1216454113 Jun 05 04:33:51 PM PDT 24 Jun 05 04:33:53 PM PDT 24 37201041 ps
T933 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.612329717 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 51015996 ps
T93 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2090478171 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 22404834 ps
T75 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2150164418 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:47 PM PDT 24 182132743 ps
T94 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.119834369 Jun 05 04:33:50 PM PDT 24 Jun 05 04:33:52 PM PDT 24 27823230 ps
T934 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.47786018 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:48 PM PDT 24 142294595 ps
T935 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2639692573 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:05 PM PDT 24 241193130 ps
T58 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4070946647 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:52 PM PDT 24 189652948 ps
T59 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2099710662 Jun 05 04:33:40 PM PDT 24 Jun 05 04:33:43 PM PDT 24 878155386 ps
T119 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3429743386 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:03 PM PDT 24 173527764 ps
T95 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.751673348 Jun 05 04:34:05 PM PDT 24 Jun 05 04:34:07 PM PDT 24 89088458 ps
T76 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3545385767 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:45 PM PDT 24 41717824 ps
T936 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3128226975 Jun 05 04:33:59 PM PDT 24 Jun 05 04:34:01 PM PDT 24 200405717 ps
T77 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.434394339 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:02 PM PDT 24 220242033 ps
T96 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3749766684 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 16394189 ps
T126 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.712712260 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:51 PM PDT 24 569960219 ps
T937 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.847836463 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 62561202 ps
T938 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.989310045 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:03 PM PDT 24 49839787 ps
T78 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.743492823 Jun 05 04:34:06 PM PDT 24 Jun 05 04:34:15 PM PDT 24 1517542186 ps
T79 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1767032617 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:08 PM PDT 24 421327460 ps
T120 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1070766115 Jun 05 04:33:51 PM PDT 24 Jun 05 04:33:54 PM PDT 24 164674128 ps
T113 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1894922202 Jun 05 04:34:17 PM PDT 24 Jun 05 04:34:21 PM PDT 24 289476479 ps
T939 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.480789768 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 19107899 ps
T940 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2630011504 Jun 05 04:34:02 PM PDT 24 Jun 05 04:34:05 PM PDT 24 181133721 ps
T121 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3975793412 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:50 PM PDT 24 251472192 ps
T80 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3754363944 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 15594249 ps
T114 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1618064568 Jun 05 04:34:06 PM PDT 24 Jun 05 04:34:11 PM PDT 24 280548513 ps
T81 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2962887802 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:51 PM PDT 24 834914283 ps
T941 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.760812860 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:04 PM PDT 24 152321569 ps
T942 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.361379805 Jun 05 04:33:54 PM PDT 24 Jun 05 04:33:56 PM PDT 24 200540127 ps
T943 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3902268193 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:06 PM PDT 24 65594245 ps
T944 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1098352998 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:45 PM PDT 24 81816872 ps
T945 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1915340668 Jun 05 04:34:03 PM PDT 24 Jun 05 04:34:08 PM PDT 24 96422311 ps
T82 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2664566969 Jun 05 04:33:49 PM PDT 24 Jun 05 04:33:51 PM PDT 24 41660068 ps
T946 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3557732267 Jun 05 04:33:55 PM PDT 24 Jun 05 04:33:56 PM PDT 24 63481601 ps
T947 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2444789344 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:50 PM PDT 24 16603677 ps
T115 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.251432631 Jun 05 04:33:42 PM PDT 24 Jun 05 04:33:44 PM PDT 24 42783313 ps
T948 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2819372437 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:54 PM PDT 24 55915108 ps
T129 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3180300785 Jun 05 04:34:03 PM PDT 24 Jun 05 04:34:06 PM PDT 24 846023449 ps
T116 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3440456908 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:57 PM PDT 24 243658478 ps
T83 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2587606732 Jun 05 04:34:03 PM PDT 24 Jun 05 04:34:05 PM PDT 24 14600533 ps
T949 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.715406876 Jun 05 04:34:05 PM PDT 24 Jun 05 04:34:11 PM PDT 24 1057066453 ps
T117 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3462693917 Jun 05 04:34:19 PM PDT 24 Jun 05 04:34:24 PM PDT 24 1238367857 ps
T950 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1421092101 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:51 PM PDT 24 470818510 ps
T951 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2919162252 Jun 05 04:33:51 PM PDT 24 Jun 05 04:33:53 PM PDT 24 48561797 ps
T952 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1814535661 Jun 05 04:33:54 PM PDT 24 Jun 05 04:33:58 PM PDT 24 366012840 ps
T953 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1321045620 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 37076377 ps
T954 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1243750082 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:03 PM PDT 24 38818196 ps
T955 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1258048440 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 348824344 ps
T956 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2396253224 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:50 PM PDT 24 95218186 ps
T957 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1319225067 Jun 05 04:34:08 PM PDT 24 Jun 05 04:34:10 PM PDT 24 35837541 ps
T958 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4144644854 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:43 PM PDT 24 37528929 ps
T959 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3278277744 Jun 05 04:34:05 PM PDT 24 Jun 05 04:34:08 PM PDT 24 49608339 ps
T960 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4079398305 Jun 05 04:34:16 PM PDT 24 Jun 05 04:34:19 PM PDT 24 53825423 ps
T131 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2192353128 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 119580607 ps
T84 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.733579184 Jun 05 04:33:46 PM PDT 24 Jun 05 04:33:51 PM PDT 24 1897041704 ps
T961 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2106516917 Jun 05 04:34:04 PM PDT 24 Jun 05 04:34:07 PM PDT 24 71300877 ps
T962 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1639627560 Jun 05 04:34:08 PM PDT 24 Jun 05 04:34:11 PM PDT 24 132380219 ps
T963 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2442940007 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 23568682 ps
T122 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3476419521 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:47 PM PDT 24 129469135 ps
T85 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1792910124 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 212989756 ps
T86 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2848668694 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:45 PM PDT 24 227525024 ps
T964 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.134737695 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:03 PM PDT 24 26294669 ps
T965 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.116955404 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:01 PM PDT 24 35668020 ps
T966 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1999241870 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 2193470956 ps
T967 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1851812129 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 40418437 ps
T968 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2307832515 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 20685235 ps
T90 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2629579832 Jun 05 04:34:08 PM PDT 24 Jun 05 04:34:10 PM PDT 24 51968500 ps
T128 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.753335427 Jun 05 04:33:46 PM PDT 24 Jun 05 04:33:49 PM PDT 24 686661455 ps
T969 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.724622381 Jun 05 04:33:49 PM PDT 24 Jun 05 04:33:53 PM PDT 24 430103617 ps
T970 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2095668437 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:51 PM PDT 24 43750338 ps
T971 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3501808164 Jun 05 04:34:16 PM PDT 24 Jun 05 04:34:17 PM PDT 24 19612076 ps
T972 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2771712295 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:49 PM PDT 24 14159688 ps
T973 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1951382022 Jun 05 04:33:59 PM PDT 24 Jun 05 04:34:01 PM PDT 24 11733753 ps
T974 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3884808330 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 18588332 ps
T91 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3840747631 Jun 05 04:33:43 PM PDT 24 Jun 05 04:33:46 PM PDT 24 25231975 ps
T975 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4276526963 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:49 PM PDT 24 279481186 ps
T976 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.674355047 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:51 PM PDT 24 40392285 ps
T977 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3785472870 Jun 05 04:33:54 PM PDT 24 Jun 05 04:33:56 PM PDT 24 58823226 ps
T978 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2716707829 Jun 05 04:34:20 PM PDT 24 Jun 05 04:34:21 PM PDT 24 464215417 ps
T979 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3449943147 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:04 PM PDT 24 164862313 ps
T127 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4156343642 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:09 PM PDT 24 175607751 ps
T980 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.295016107 Jun 05 04:33:44 PM PDT 24 Jun 05 04:33:47 PM PDT 24 16325837 ps
T981 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3640496463 Jun 05 04:33:49 PM PDT 24 Jun 05 04:33:52 PM PDT 24 15695783 ps
T982 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1734269267 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:51 PM PDT 24 804132356 ps
T983 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.162563705 Jun 05 04:34:02 PM PDT 24 Jun 05 04:34:07 PM PDT 24 121958317 ps
T123 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1478526754 Jun 05 04:33:58 PM PDT 24 Jun 05 04:34:04 PM PDT 24 3365675371 ps
T984 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1767157949 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:08 PM PDT 24 29192846 ps
T985 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3364937398 Jun 05 04:33:48 PM PDT 24 Jun 05 04:33:52 PM PDT 24 171531958 ps
T986 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1475523513 Jun 05 04:34:15 PM PDT 24 Jun 05 04:34:18 PM PDT 24 134343281 ps
T987 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1455948794 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:55 PM PDT 24 305801974 ps
T988 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3593946648 Jun 05 04:33:49 PM PDT 24 Jun 05 04:33:52 PM PDT 24 50671828 ps
T989 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1135585842 Jun 05 04:33:47 PM PDT 24 Jun 05 04:33:53 PM PDT 24 57144973 ps
T990 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3054012943 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:02 PM PDT 24 42870847 ps
T991 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.966465600 Jun 05 04:33:53 PM PDT 24 Jun 05 04:33:56 PM PDT 24 108538790 ps
T992 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3815136824 Jun 05 04:34:00 PM PDT 24 Jun 05 04:34:01 PM PDT 24 32634407 ps
T993 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3952608978 Jun 05 04:33:59 PM PDT 24 Jun 05 04:34:04 PM PDT 24 620604524 ps
T994 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.142536866 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:09 PM PDT 24 807204353 ps
T130 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2837447264 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:55 PM PDT 24 164210225 ps
T995 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.159495963 Jun 05 04:34:14 PM PDT 24 Jun 05 04:34:16 PM PDT 24 46640803 ps
T996 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1196392715 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:46 PM PDT 24 1569177992 ps
T997 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.127009004 Jun 05 04:34:07 PM PDT 24 Jun 05 04:34:09 PM PDT 24 47035695 ps
T998 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2788827085 Jun 05 04:33:52 PM PDT 24 Jun 05 04:33:57 PM PDT 24 547274072 ps
T124 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2019952100 Jun 05 04:34:01 PM PDT 24 Jun 05 04:34:05 PM PDT 24 206661597 ps
T999 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1063196407 Jun 05 04:33:46 PM PDT 24 Jun 05 04:33:49 PM PDT 24 20119320 ps
T1000 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.520706222 Jun 05 04:33:57 PM PDT 24 Jun 05 04:33:59 PM PDT 24 22992203 ps
T1001 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2700297377 Jun 05 04:33:41 PM PDT 24 Jun 05 04:33:44 PM PDT 24 58818650 ps
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