Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14126728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57703842

1

T1

35260

T2

56

T3

127485

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35809038	1			T1	95974		T2	352		T3	70017
values[0x0]	16600296	1			T1	32525		T2	243		T3	33821
values[0x1]	19421236	1			T1	64310		T2	424		T3	36416

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7039409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

64791161

1

T1

114377

T2

476

T3

133876

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	397263	1			T1	793		T2	3		T3	544
valid_sources[0x01]	248888	1			T1	788		T2	4		T3	583
valid_sources[0x02]	294797	1			T1	964		T2	5		T3	538
valid_sources[0x03]	244003	1			T1	765		T2	5		T3	568
valid_sources[0x04]	286290	1			T1	757		T2	4		T3	539
valid_sources[0x05]	243288	1			T1	676		T2	2		T3	515
valid_sources[0x06]	295947	1			T1	659		T2	4		T3	562
valid_sources[0x07]	279401	1			T1	609		T2	3		T3	525
valid_sources[0x08]	261832	1			T1	781		T2	6		T3	555
valid_sources[0x09]	282572	1			T1	828		T2	1		T3	510
valid_sources[0x0a]	325516	1			T1	891		T2	4		T3	597
valid_sources[0x0b]	252736	1			T1	615		T2	5		T3	516
valid_sources[0x0c]	301286	1			T1	966		T2	6		T3	457
valid_sources[0x0d]	286293	1			T1	770		T2	6		T3	528
valid_sources[0x0e]	245977	1			T1	607		T2	2		T3	534
valid_sources[0x0f]	320292	1			T1	653		T2	3		T3	555
valid_sources[0x10]	283869	1			T1	730		T2	3		T3	559
valid_sources[0x11]	253070	1			T1	799		T2	2		T3	510
valid_sources[0x12]	285498	1			T1	672		T2	5		T3	550
valid_sources[0x13]	278658	1			T1	884		T2	5		T3	556
valid_sources[0x14]	267814	1			T1	885		T2	3		T3	508
valid_sources[0x15]	257395	1			T1	693		T2	6		T3	576
valid_sources[0x16]	260422	1			T1	630		T2	1		T3	565
valid_sources[0x17]	376456	1			T1	646		T2	3		T3	558
valid_sources[0x18]	260982	1			T1	662		T2	5		T3	485
valid_sources[0x19]	319550	1			T1	901		T2	5		T3	580
valid_sources[0x1a]	283132	1			T1	922		T2	1		T3	521
valid_sources[0x1b]	287037	1			T1	768		T2	4		T3	508
valid_sources[0x1c]	278594	1			T1	602		T2	7		T3	526
valid_sources[0x1d]	285317	1			T1	535		T3	537		T4	475
valid_sources[0x1e]	279437	1			T1	759		T2	7		T3	541
valid_sources[0x1f]	245513	1			T1	789		T2	3		T3	577
valid_sources[0x20]	264547	1			T1	493		T2	3		T3	522
valid_sources[0x21]	263237	1			T1	711		T2	7		T3	558
valid_sources[0x22]	246325	1			T1	746		T2	2		T3	585
valid_sources[0x23]	302163	1			T1	943		T2	8		T3	562
valid_sources[0x24]	238300	1			T1	860		T2	5		T3	536
valid_sources[0x25]	298932	1			T1	711		T2	2		T3	495
valid_sources[0x26]	259910	1			T1	928		T2	8		T3	562
valid_sources[0x27]	308789	1			T1	826		T2	5		T3	517
valid_sources[0x28]	318734	1			T1	783		T2	6		T3	557
valid_sources[0x29]	352544	1			T1	766		T2	7		T3	569
valid_sources[0x2a]	282584	1			T1	808		T2	5		T3	589
valid_sources[0x2b]	253982	1			T1	815		T2	2		T3	550
valid_sources[0x2c]	255196	1			T1	746		T2	2		T3	536
valid_sources[0x2d]	344175	1			T1	623		T2	5		T3	581
valid_sources[0x2e]	280905	1			T1	675		T2	4		T3	577
valid_sources[0x2f]	285791	1			T1	751		T2	2		T3	574
valid_sources[0x30]	248912	1			T1	893		T2	3		T3	528
valid_sources[0x31]	309735	1			T1	778		T2	5		T3	543
valid_sources[0x32]	283239	1			T1	901		T2	2		T3	589
valid_sources[0x33]	251003	1			T1	787		T2	6		T3	596
valid_sources[0x34]	241491	1			T1	1107		T2	9		T3	508
valid_sources[0x35]	264716	1			T1	921		T2	6		T3	534
valid_sources[0x36]	256443	1			T1	605		T2	6		T3	527
valid_sources[0x37]	282129	1			T1	584		T2	1		T3	554
valid_sources[0x38]	418300	1			T1	753		T2	8		T3	561
valid_sources[0x39]	247065	1			T1	960		T2	6		T3	543
valid_sources[0x3a]	260360	1			T1	826		T2	7		T3	568
valid_sources[0x3b]	252244	1			T1	661		T2	3		T3	546
valid_sources[0x3c]	297165	1			T1	861		T2	3		T3	527
valid_sources[0x3d]	255636	1			T1	676		T2	3		T3	540
valid_sources[0x3e]	250568	1			T1	873		T2	6		T3	505
valid_sources[0x3f]	353253	1			T1	608		T2	2		T3	527
valid_sources[0x40]	327098	1			T1	585		T2	2		T3	538
valid_sources[0x41]	252958	1			T1	689		T2	3		T3	578
valid_sources[0x42]	260201	1			T1	719		T2	1		T3	577
valid_sources[0x43]	277312	1			T1	559		T2	11		T3	544
valid_sources[0x44]	257784	1			T1	677		T2	1		T3	585
valid_sources[0x45]	283572	1			T1	762		T2	1		T3	592
valid_sources[0x46]	272779	1			T1	857		T2	2		T3	527
valid_sources[0x47]	250489	1			T1	484		T2	3		T3	563
valid_sources[0x48]	271365	1			T1	798		T2	2		T3	586
valid_sources[0x49]	286060	1			T1	643		T2	2		T3	550
valid_sources[0x4a]	305801	1			T1	970		T2	5		T3	523
valid_sources[0x4b]	294460	1			T1	656		T2	5		T3	531
valid_sources[0x4c]	295802	1			T1	744		T2	2		T3	529
valid_sources[0x4d]	289431	1			T1	934		T2	2		T3	594
valid_sources[0x4e]	276341	1			T1	708		T2	6		T3	552
valid_sources[0x4f]	257180	1			T1	809		T2	5		T3	540
valid_sources[0x50]	250266	1			T1	757		T2	3		T3	558
valid_sources[0x51]	265920	1			T1	626		T2	5		T3	517
valid_sources[0x52]	240730	1			T1	768		T2	3		T3	569
valid_sources[0x53]	443777	1			T1	681		T2	3		T3	550
valid_sources[0x54]	330163	1			T1	766		T2	8		T3	554
valid_sources[0x55]	292247	1			T1	791		T2	5		T3	534
valid_sources[0x56]	292430	1			T1	654		T2	5		T3	552
valid_sources[0x57]	291571	1			T1	969		T2	1		T3	518
valid_sources[0x58]	246290	1			T1	654		T2	4		T3	514
valid_sources[0x59]	314128	1			T1	642		T2	4		T3	567
valid_sources[0x5a]	333704	1			T1	698		T2	3		T3	573
valid_sources[0x5b]	247141	1			T1	652		T2	5		T3	584
valid_sources[0x5c]	259346	1			T1	655		T2	4		T3	523
valid_sources[0x5d]	258757	1			T1	583		T2	2		T3	557
valid_sources[0x5e]	282627	1			T1	894		T2	9		T3	621
valid_sources[0x5f]	255068	1			T1	724		T2	4		T3	520
valid_sources[0x60]	312238	1			T1	851		T2	2		T3	554
valid_sources[0x61]	277555	1			T1	697		T2	4		T3	559
valid_sources[0x62]	248180	1			T1	709		T2	6		T3	585
valid_sources[0x63]	295508	1			T1	937		T2	3		T3	567
valid_sources[0x64]	298959	1			T1	970		T2	1		T3	552
valid_sources[0x65]	291795	1			T1	911		T2	6		T3	524
valid_sources[0x66]	312441	1			T1	637		T2	1		T3	554
valid_sources[0x67]	288847	1			T1	849		T2	3		T3	514
valid_sources[0x68]	270878	1			T1	586		T2	1		T3	521
valid_sources[0x69]	259899	1			T1	733		T2	2		T3	555
valid_sources[0x6a]	290794	1			T1	799		T2	3		T3	552
valid_sources[0x6b]	244570	1			T1	783		T2	8		T3	532
valid_sources[0x6c]	291456	1			T1	599		T2	3		T3	562
valid_sources[0x6d]	255845	1			T1	810		T2	4		T3	572
valid_sources[0x6e]	261917	1			T1	643		T2	9		T3	544
valid_sources[0x6f]	242696	1			T1	880		T2	3		T3	560
valid_sources[0x70]	286630	1			T1	668		T2	1		T3	549
valid_sources[0x71]	270219	1			T1	547		T2	4		T3	568
valid_sources[0x72]	259314	1			T1	670		T2	1		T3	523
valid_sources[0x73]	286350	1			T1	633		T2	7		T3	541
valid_sources[0x74]	274561	1			T1	626		T2	2		T3	581
valid_sources[0x75]	279530	1			T1	639		T2	3		T3	565
valid_sources[0x76]	261476	1			T1	903		T2	2		T3	567
valid_sources[0x77]	256554	1			T1	820		T2	9		T3	521
valid_sources[0x78]	302866	1			T1	732		T2	4		T3	503
valid_sources[0x79]	298405	1			T1	810		T2	9		T3	583
valid_sources[0x7a]	253354	1			T1	792		T2	5		T3	546
valid_sources[0x7b]	314480	1			T1	798		T2	6		T3	537
valid_sources[0x7c]	381945	1			T1	821		T2	4		T3	572
valid_sources[0x7d]	254329	1			T1	771		T2	7		T3	532
valid_sources[0x7e]	251289	1			T1	666		T2	1		T3	555
valid_sources[0x7f]	266606	1			T1	705		T2	3		T3	565
valid_sources[0x80]	250895	1			T1	939		T2	6		T3	552

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28753104

1

T1

17478

T2

4

T3

63624

values[0x0]

all_enables

biggest_size

14478840

1

T1

8838

T2

32

T3

31917

values[0x1]

all_enables

biggest_size

14471898

1

T1

8944

T2

20

T3

31944

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

130269

1

T1

1

T3

6

T5

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48536	1			T5	37		T6	27		T16	2
values[0x0]	56848	1			T1	3		T3	11		T5	16
values[0x1]	61188	1			T1	1		T2	2		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138792

1

T1

1

T2

1

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	552	1			T23	2		T24	5		T126	1
valid_sources[0x01]	661	1			T7	1		T23	101		T126	2
valid_sources[0x02]	457	1			T32	1		T23	2		T126	1
valid_sources[0x03]	720	1			T82	2		T24	1		T111	4
valid_sources[0x04]	669	1			T5	1		T22	2		T23	3
valid_sources[0x05]	691	1			T16	1		T32	1		T23	147
valid_sources[0x06]	498	1			T139	1		T40	9		T42	11
valid_sources[0x07]	588	1			T7	2		T17	1		T22	1
valid_sources[0x08]	1108	1			T10	2		T23	1		T100	4
valid_sources[0x09]	692	1			T7	1		T26	1		T82	1
valid_sources[0x0a]	618	1			T3	1		T18	36		T22	2
valid_sources[0x0b]	823	1			T22	1		T23	61		T62	1
valid_sources[0x0c]	507	1			T138	1		T140	4		T40	5
valid_sources[0x0d]	1343	1			T12	1		T82	2		T40	10
valid_sources[0x0e]	540	1			T17	2		T23	4		T40	7
valid_sources[0x0f]	579	1			T7	1		T82	3		T24	10
valid_sources[0x10]	741	1			T7	1		T17	4		T22	1
valid_sources[0x11]	763	1			T3	1		T5	1		T7	1
valid_sources[0x12]	487	1			T12	1		T7	1		T40	12
valid_sources[0x13]	536	1			T3	1		T23	70		T24	2
valid_sources[0x14]	515	1			T7	1		T23	8		T126	3
valid_sources[0x15]	530	1			T2	2		T24	1		T141	1
valid_sources[0x16]	540	1			T7	1		T17	2		T22	1
valid_sources[0x17]	621	1			T23	6		T66	1		T56	4
valid_sources[0x18]	535	1			T5	1		T12	1		T7	1
valid_sources[0x19]	418	1			T12	1		T22	1		T40	8
valid_sources[0x1a]	609	1			T22	2		T23	1		T126	1
valid_sources[0x1b]	663	1			T10	4		T141	2		T111	6
valid_sources[0x1c]	451	1			T5	2		T22	1		T23	3
valid_sources[0x1d]	1107	1			T5	2		T22	2		T23	4
valid_sources[0x1e]	750	1			T22	1		T23	30		T111	10
valid_sources[0x1f]	493	1			T5	1		T24	15		T142	1
valid_sources[0x20]	756	1			T23	4		T35	1		T24	2
valid_sources[0x21]	789	1			T5	1		T30	10		T111	1
valid_sources[0x22]	506	1			T13	1		T22	1		T40	11
valid_sources[0x23]	794	1			T23	1		T126	1		T40	5
valid_sources[0x24]	642	1			T5	1		T82	4		T24	1
valid_sources[0x25]	637	1			T23	143		T24	7		T126	1
valid_sources[0x26]	529	1			T7	3		T24	3		T111	3
valid_sources[0x27]	510	1			T22	3		T24	4		T111	3
valid_sources[0x28]	687	1			T3	1		T5	1		T23	102
valid_sources[0x29]	490	1			T10	2		T64	8		T99	3
valid_sources[0x2a]	660	1			T32	1		T23	2		T126	3
valid_sources[0x2b]	511	1			T3	1		T5	1		T7	1
valid_sources[0x2c]	517	1			T12	1		T23	2		T126	1
valid_sources[0x2d]	538	1			T10	1		T23	1		T126	2
valid_sources[0x2e]	580	1			T1	1		T30	2		T17	1
valid_sources[0x2f]	590	1			T12	1		T7	1		T22	2
valid_sources[0x30]	701	1			T22	1		T82	1		T126	1
valid_sources[0x31]	802	1			T3	1		T5	1		T22	1
valid_sources[0x32]	512	1			T23	2		T126	3		T40	6
valid_sources[0x33]	596	1			T17	5		T43	3		T23	1
valid_sources[0x34]	670	1			T22	1		T25	1		T40	6
valid_sources[0x35]	488	1			T17	2		T62	1		T142	1
valid_sources[0x36]	693	1			T7	2		T22	1		T24	3
valid_sources[0x37]	452	1			T12	1		T7	1		T22	1
valid_sources[0x38]	673	1			T7	1		T30	1		T17	1
valid_sources[0x39]	574	1			T3	1		T7	1		T19	1
valid_sources[0x3a]	511	1			T7	3		T22	2		T142	1
valid_sources[0x3b]	847	1			T5	1		T13	2		T17	8
valid_sources[0x3c]	722	1			T7	1		T23	1		T126	1
valid_sources[0x3d]	839	1			T7	1		T32	4		T22	3
valid_sources[0x3e]	618	1			T7	1		T23	2		T141	1
valid_sources[0x3f]	650	1			T22	2		T137	1		T24	161
valid_sources[0x40]	1204	1			T7	1		T62	2		T24	10
valid_sources[0x41]	522	1			T5	1		T24	1		T111	2
valid_sources[0x42]	812	1			T16	2		T17	1		T22	1
valid_sources[0x43]	510	1			T5	1		T22	2		T46	1
valid_sources[0x44]	765	1			T22	3		T23	4		T24	2
valid_sources[0x45]	611	1			T5	1		T17	3		T18	3
valid_sources[0x46]	547	1			T7	2		T32	1		T23	1
valid_sources[0x47]	744	1			T126	1		T140	1		T40	14
valid_sources[0x48]	783	1			T12	1		T13	2		T32	1
valid_sources[0x49]	583	1			T126	5		T140	4		T40	11
valid_sources[0x4a]	1050	1			T12	1		T22	2		T23	133
valid_sources[0x4b]	647	1			T12	1		T23	47		T126	1
valid_sources[0x4c]	1074	1			T143	1		T144	1		T40	12
valid_sources[0x4d]	682	1			T32	1		T22	1		T23	1
valid_sources[0x4e]	511	1			T40	7		T145	1		T146	1
valid_sources[0x4f]	487	1			T5	1		T45	1		T126	2
valid_sources[0x50]	546	1			T3	1		T5	2		T7	1
valid_sources[0x51]	523	1			T53	6		T126	3		T40	14
valid_sources[0x52]	649	1			T22	3		T23	2		T40	8
valid_sources[0x53]	1004	1			T23	1		T126	2		T40	14
valid_sources[0x54]	598	1			T126	2		T25	1		T40	3
valid_sources[0x55]	575	1			T3	1		T10	3		T7	1
valid_sources[0x56]	525	1			T16	1		T22	5		T23	1
valid_sources[0x57]	735	1			T7	1		T126	2		T40	3
valid_sources[0x58]	527	1			T23	1		T62	1		T111	1
valid_sources[0x59]	576	1			T7	1		T22	1		T111	3
valid_sources[0x5a]	531	1			T7	1		T17	1		T126	2
valid_sources[0x5b]	418	1			T5	1		T7	1		T32	1
valid_sources[0x5c]	537	1			T22	1		T126	1		T40	15
valid_sources[0x5d]	806	1			T5	1		T17	1		T40	11
valid_sources[0x5e]	495	1			T7	1		T23	7		T53	2
valid_sources[0x5f]	675	1			T7	1		T24	176		T111	2
valid_sources[0x60]	609	1			T8	1		T13	1		T22	1
valid_sources[0x61]	654	1			T23	1		T24	1		T142	2
valid_sources[0x62]	905	1			T5	1		T22	1		T40	5
valid_sources[0x63]	847	1			T7	1		T32	1		T23	2
valid_sources[0x64]	577	1			T5	2		T7	1		T30	2
valid_sources[0x65]	722	1			T7	1		T17	1		T23	127
valid_sources[0x66]	920	1			T34	2		T23	159		T24	152
valid_sources[0x67]	865	1			T11	6		T147	1		T22	1
valid_sources[0x68]	803	1			T5	1		T24	92		T126	1
valid_sources[0x69]	783	1			T5	1		T22	1		T23	113
valid_sources[0x6a]	499	1			T29	1		T32	1		T24	1
valid_sources[0x6b]	559	1			T3	2		T22	3		T23	1
valid_sources[0x6c]	549	1			T22	1		T23	1		T24	2
valid_sources[0x6d]	1155	1			T10	1		T23	1		T126	1
valid_sources[0x6e]	724	1			T3	1		T7	1		T111	10
valid_sources[0x6f]	818	1			T22	2		T62	1		T24	286
valid_sources[0x70]	601	1			T17	2		T22	1		T126	1
valid_sources[0x71]	950	1			T142	1		T128	3		T126	1
valid_sources[0x72]	507	1			T7	2		T23	1		T140	2
valid_sources[0x73]	443	1			T7	1		T32	1		T22	2
valid_sources[0x74]	458	1			T12	2		T40	4		T42	9
valid_sources[0x75]	493	1			T5	1		T22	1		T23	1
valid_sources[0x76]	494	1			T5	1		T148	3		T40	11
valid_sources[0x77]	734	1			T32	1		T23	4		T25	6
valid_sources[0x78]	408	1			T7	1		T22	3		T23	1
valid_sources[0x79]	709	1			T5	2		T7	1		T17	1
valid_sources[0x7a]	664	1			T17	3		T22	5		T33	1
valid_sources[0x7b]	587	1			T3	1		T5	1		T17	3
valid_sources[0x7c]	571	1			T3	1		T22	1		T149	2
valid_sources[0x7d]	597	1			T5	1		T12	1		T40	7
valid_sources[0x7e]	615	1			T12	1		T23	128		T126	1
valid_sources[0x7f]	598	1			T7	1		T147	1		T24	1
valid_sources[0x80]	622	1			T5	1		T22	1		T53	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35816

1

T5

17

T6

14

T16

1

values[0x0]

all_enables

biggest_size

48145

1

T1

1

T3

3

T5

7

values[0x1]

all_enables

biggest_size

46308

1

T3

3

T5

1

T11

1