Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13827242

1

T1

157549

T2

963

T3

12769

full_word

52979608

1

T1

35260

T2

56

T3

127485

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66806550	1			T1	192809		T2	1019		T3	140254
auto[TlIntgErrCmd]	100	1			T50	8		T51	4		T52	1
auto[TlIntgErrData]	107	1			T50	10		T51	11		T52	4
auto[TlIntgErrBoth]	93	1			T50	2		T51	5		T52	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30743022

1

T1

95974

T2

352

T3

70017

auto[1]

36063828

1

T1

96835

T2

667

T3

70237

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6627106	1			T1	78496		T2	348		T3	6393
auto[TlIntgErrNone]	partial	auto[1]	7199864	1			T1	79053		T2	615		T3	6376
auto[TlIntgErrNone]	full_word	auto[0]	24115789	1			T1	17478		T2	4		T3	63624
auto[TlIntgErrNone]	full_word	auto[1]	28863791	1			T1	17782		T2	52		T3	63861
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T50	1		T51	1		T118	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T50	6		T51	3		T52	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T119	1		T120	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T50	1		T121	1		T117	2
auto[TlIntgErrData]	partial	auto[0]	52	1			T50	5		T51	4		T52	1
auto[TlIntgErrData]	partial	auto[1]	43	1			T50	5		T51	6		T118	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T51	1		T52	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T52	2		T121	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T51	2		T52	1		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T50	2		T51	3		T52	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T122	1		T120	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	2		T124	1		T123	1