Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	552022	1			T6	25		T29	160		T18	1577
auto[1]	10080127	1			T1	80841		T2	58		T3	27584
auto[2]	464751	1			T6	20		T29	109		T18	1390
auto[3]	9995993	1			T1	81444		T2	124		T3	27715

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13772981	1			T1	5372		T3	45806		T4	4185
auto[1]	2017699	1			T1	24254		T2	6		T3	4495
auto[2]	2010071	1			T1	24202		T2	11		T3	4578
auto[3]	3292142	1			T1	108457		T2	165		T3	420

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7850939

1

T1

28

T2

182

T3

55253

auto[1]

13241954

1

T1

162257

T3

46

T4

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	224285	1			T6	19		T29	127		T18	1301
auto[0]	auto[0]	auto[1]	23170	1			T6	2		T29	20		T18	117
auto[0]	auto[0]	auto[2]	23327	1			T6	3		T29	11		T18	139
auto[0]	auto[0]	auto[3]	6153	1			T6	1		T29	2		T18	17
auto[0]	auto[1]	auto[0]	2993398	1			T1	1		T3	22803		T4	2093
auto[0]	auto[1]	auto[1]	317262	1			T1	1		T3	2236		T4	194
auto[0]	auto[1]	auto[2]	303643	1			T3	2323		T4	204		T8	32
auto[0]	auto[1]	auto[3]	65327	1			T1	13		T2	58		T3	201
auto[0]	auto[2]	auto[0]	200574	1			T6	16		T29	80		T18	1176
auto[0]	auto[2]	auto[1]	20624	1			T6	1		T29	10		T18	111
auto[0]	auto[2]	auto[2]	18194	1			T6	2		T29	18		T18	94
auto[0]	auto[2]	auto[3]	4908	1			T6	1		T18	9		T32	9
auto[0]	auto[3]	auto[0]	2968261	1			T3	22964		T4	2090		T5	8
auto[0]	auto[3]	auto[1]	301216	1			T1	4		T2	6		T3	2256
auto[0]	auto[3]	auto[2]	313389	1			T1	3		T2	11		T3	2251
auto[0]	auto[3]	auto[3]	67208	1			T1	6		T2	107		T3	219
auto[1]	auto[0]	auto[0]	9367	1			T18	2		T32	2		T43	2
auto[1]	auto[0]	auto[1]	40932	1			T43	1		T101	1573		T134	2
auto[1]	auto[0]	auto[2]	41030	1			T18	1		T101	1485		T135	2
auto[1]	auto[0]	auto[3]	183758	1			T101	6965		T133	18526		T136	12100
auto[1]	auto[1]	auto[0]	3685310	1			T1	2608		T3	17		T8	1
auto[1]	auto[1]	auto[1]	659436	1			T1	12036		T3	1		T9	2
auto[1]	auto[1]	auto[2]	627886	1			T1	12001		T3	3		T11	16823
auto[1]	auto[1]	auto[3]	1427865	1			T1	54181		T11	76909		T17	1
auto[1]	auto[2]	auto[0]	7825	1			T43	1		T33	2		T137	1
auto[1]	auto[2]	auto[1]	34894	1			T43	1		T101	930		T135	1
auto[1]	auto[2]	auto[2]	32423	1			T29	1		T101	1712		T138	1
auto[1]	auto[2]	auto[3]	145309	1			T101	7586		T132	1		T133	15634
auto[1]	auto[3]	auto[0]	3683961	1			T1	2763		T3	22		T4	2
auto[1]	auto[3]	auto[1]	620165	1			T1	12213		T3	2		T4	1
auto[1]	auto[3]	auto[2]	650179	1			T1	12198		T3	1		T9	1
auto[1]	auto[3]	auto[3]	1391614	1			T1	54257		T9	1		T11	77267