Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	326168688	182571	0	0
ctrl_regwen_rd_A	326168688	6629	0	0
exec_rd_A	326168688	6211	0	0
exec_regwen_rd_A	326168688	6312	0	0
readback_rd_A	326168688	4042	0	0
readback_regwen_rd_A	326168688	3447	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	182571	0	0
T23	147984	5076	0	0
T24	0	3853	0	0
T25	0	665	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T40	0	3226	0	0
T42	0	3017	0	0
T47	0	5220	0	0
T48	0	9937	0	0
T49	0	4526	0	0
T58	0	3801	0	0
T59	0	9541	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	6629	0	0
T23	147984	414	0	0
T24	0	181	0	0
T25	0	52	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T42	0	90	0	0
T58	0	144	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0
T106	0	293	0	0
T107	0	400	0	0
T108	0	227	0	0
T109	0	455	0	0
T110	0	160	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	6211	0	0
T23	147984	421	0	0
T24	0	175	0	0
T25	0	63	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T42	0	142	0	0
T58	0	160	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0
T106	0	254	0	0
T107	0	428	0	0
T108	0	165	0	0
T109	0	473	0	0
T110	0	125	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	6312	0	0
T23	147984	378	0	0
T24	0	175	0	0
T25	0	46	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T42	0	73	0	0
T58	0	119	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0
T106	0	275	0	0
T107	0	385	0	0
T108	0	126	0	0
T109	0	469	0	0
T110	0	179	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	4042	0	0
T23	147984	302	0	0
T24	0	177	0	0
T25	0	38	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T42	0	134	0	0
T58	0	122	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0
T106	0	271	0	0
T107	0	400	0	0
T108	0	172	0	0
T109	0	420	0	0
T110	0	56	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326168688	3447	0	0
T23	147984	274	0	0
T24	0	105	0	0
T25	0	27	0	0
T28	2875	0	0	0
T33	561273	0	0	0
T42	0	135	0	0
T58	0	133	0	0
T60	291454	0	0	0
T61	13584	0	0	0
T62	381662	0	0	0
T63	490299	0	0	0
T64	174432	0	0	0
T65	23037	0	0	0
T66	14309	0	0	0
T106	0	202	0	0
T107	0	331	0	0
T108	0	143	0	0
T109	0	464	0	0
T110	0	70	0	0