Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.84	99.31	93.07		100.00	91.80	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte	97.40	99.31	95.88		100.00	91.80	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	99.31	95.88		100.00	91.80	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	98.83	94.94		100.00	92.38	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.49	97.37	86.84			93.75	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_integ_handling.gen_readback_logic.u_rdback_check_flop	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf	100.00	100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp_intg	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_en_flop	100.00	100.00				100.00
gen_integ_handling.u_state_regs	100.00	100.00				100.00	100.00
gen_integ_handling.u_sync_fifo	90.73	95.00	86.67			81.25	100.00
gen_integ_handling.u_sync_fifo_a_size	100.00	100.00	100.00			100.00	100.00
gen_integ_handling.u_tlul_data_integ_enc	100.00	100.00

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	144	99.31
ALWAYS	104	3	3	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	233	95	94	98.95
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	536	2	2	100.00
ALWAYS	547	0	0
ALWAYS	547	2	2	100.00
ALWAYS	566	2	2	100.00
ALWAYS	573	22	22	100.00
CONT_ASSIGN	627	1	1	100.00
ALWAYS	652	4	4	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
104	3	3
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
150	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
249	1	1
251	1	1
256	1	1
257	1	1
260	1	1
261	0	1
			MISSING_ELSE
			MISSING_ELSE
265	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
270	1	1
274	1	1
275	1	1
			MISSING_ELSE
278	1	1
281	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			==> MISSING_ELSE
			MISSING_ELSE
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
			==> MISSING_ELSE
314	1	1
316		unreachable
			MISSING_ELSE
320	1	1
324	1	1
325	1	1
328	1	1
329	1	1
330	1	1
331	1	1
334	1	1
337	1	1
			MISSING_ELSE
344	1	1
346		unreachable
			MISSING_ELSE
349	1	1
351	1	1
353	1	1
359	1	1
361		unreachable
			MISSING_ELSE
365	1	1
367	1	1
369	1	1
372	1	1
			MISSING_ELSE
379	1	1
381		unreachable
			MISSING_ELSE
386	1	1
389	1	1
392	1	1
394	1	1
397	1	1
403	1	1
			==> MISSING_ELSE
411	1	1
413		unreachable
			MISSING_ELSE
416	1	1
418	1	1
420	1	1
424	1	1
426		unreachable
			MISSING_ELSE
429	1	1
432	1	1
434	1	1
437	1	1
			MISSING_ELSE
442	1	1
444		unreachable
			MISSING_ELSE
449	1	1
453	1	1
454	1	1
456	1	1
457	1	1
459	1	1
460	1	1
461	1	1
464	1	1
			MISSING_ELSE
470	1	1
472		unreachable
			MISSING_ELSE
475	1	1
477	1	1
480	1	1
482	1	1
483	1	1
484	1	1
			MISSING_ELSE
500	1	1
511	1	1
536	1	1
537	1	1
			MISSING_ELSE
547	1	1
548	1	1
566	1	1
567	1	1
573	1	1
575	1	1
584	1	1
585	1	1
587	1	1
590	1	1
592	1	1
596	1	1
597	1	1
599	1	1
600	1	1
601	1	1
602	1	1
604	1	1
606	1	1
608	1	1
611	1	1
612	1	1
614	1	1
615	1	1
			MISSING_ELSE
617	1	1
620	1	1
			MISSING_ELSE
627	1	1
652	1	1
655	1	1
659	1	1
664	1	1
670	1	1
693	1	1
710	1	1
711	1	1

---

Cond Coverage for Module : tlul_sram_byte

	Total	Covered	Percent
Conditions	101	94	93.07
Logical	101	94	93.07
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T29
1	1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T10,T12
1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       260
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T23,T35
1	0	Not Covered
1	1	Not Covered

 LINE       275
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T34,T23,T35

 LINE       291
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T6,T29,T18
1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T24,T36,T37
1	Covered	T34,T23,T35

 LINE       389
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T34,T23,T35

 LINE       453
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T24,T36,T37
1	Covered	T34,T23,T35

 LINE       511
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T23,T35

 LINE       536
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       548
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       575
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T4,T8,T10
1	0	0	Covered	T1,T2,T3

 LINE       584
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T34,T23,T35
1	0	0	Covered	T1,T2,T3

 LINE       587
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       590
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       592
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       592
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       597
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       597
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       601
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       602
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       627
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       655
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T34,T23,T35
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       659
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T34,T23,T35
1	1	1	Covered	T1,T2,T3

 LINE       693
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T34,T23,T35
1	0	0	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	397	Covered	T34,T23,T35
StByteWrReadBackDWait	403	Covered	T34,T23,T35
StByteWrReadBackInit	304	Covered	T34,T23,T35
StPassThru	304	Covered	T1,T2,T3
StRdReadBack	275	Covered	T34,T23,T35
StRdReadBackDWait	464	Covered	T35,T24,T38
StWaitRd	268	Covered	T1,T2,T3
StWrReadBack	334	Covered	T34,T23,T35
StWrReadBackDWait	337	Covered	T35,T24,T38
StWrReadBackInit	275	Covered	T34,T23,T35
StWriteCmd	294	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	420	Covered	T34,T23,T35
StByteWrReadBackDWait->StByteWrReadBack	437	Covered	T34,T23,T35
StByteWrReadBackInit->StByteWrReadBack	397	Covered	T34,T23,T35
StByteWrReadBackInit->StByteWrReadBackDWait	403	Covered	T34,T23,T35
StPassThru->StRdReadBack	275	Covered	T34,T23,T35
StPassThru->StWaitRd	268	Covered	T1,T2,T3
StPassThru->StWrReadBackInit	275	Covered	T34,T23,T35
StRdReadBack->StPassThru	457	Covered	T34,T23,T35
StRdReadBack->StRdReadBackDWait	464	Covered	T35,T24,T38
StRdReadBackDWait->StPassThru	480	Covered	T35,T24,T38
StWaitRd->StWriteCmd	294	Covered	T1,T2,T3
StWrReadBack->StPassThru	353	Covered	T34,T23,T35
StWrReadBackDWait->StWrReadBack	372	Covered	T35,T24,T38
StWrReadBackInit->StWrReadBack	334	Covered	T34,T23,T35
StWrReadBackInit->StWrReadBackDWait	337	Covered	T35,T24,T38
StWriteCmd->StByteWrReadBackInit	304	Covered	T34,T23,T35
StWriteCmd->StPassThru	304	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	56	91.80
IF	104	2	2	100.00
CASE	249	39	34	87.18
IF	536	2	2	100.00
TERNARY	548	2	2	100.00
IF	584	16	16	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	case (gen_integ_handling.state_q)
-2-:	251	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	260	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	265	if (gen_integ_handling.byte_wr_txn)
-5-:	267	if (gen_integ_handling.byte_req_ack)
-6-:	270	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	275	(gen_integ_handling.wr_txn) ? 
-8-:	278	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	291	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	293	if (gen_integ_handling.sram_d_ack)
-11-:	303	if (gen_integ_handling.sram_a_ack)
-12-:	314	if ((EnableReadback == 1'b0))
-13-:	324	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	331	if (gen_integ_handling.d_ack)
-15-:	344	if ((EnableReadback == 1'b0))
-16-:	359	if ((EnableReadback == 1'b0))
-17-:	369	if (gen_integ_handling.d_ack)
-18-:	379	if ((EnableReadback == 1'b0))
-19-:	389	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	394	if (gen_integ_handling.d_ack)
-21-:	411	if ((EnableReadback == 1'b0))
-22-:	424	if ((EnableReadback == 1'b0))
-23-:	434	if (gen_integ_handling.d_ack)
-24-:	442	if ((EnableReadback == 1'b0))
-25-:	453	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	456	if (gen_integ_handling.d_ack)
-27-:	470	if ((EnableReadback == 1'b0))
-28-:	477	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T10
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T18
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T35,T24
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T36,T37
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T34,T35,T24
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T24,T36,T37
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T35,T24,T38
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T35,T24,T38
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T35,T24,T38
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	536	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	548	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	587	(gen_integ_handling.wr_phase) ? 
-3-:	590	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	592	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	597	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	601	(gen_integ_handling.wr_phase) ? 
-7-:	602	(gen_integ_handling.wr_phase) ? 
-8-:	604	if (gen_integ_handling.rd_phase)
-9-:	608	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	617	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	0	-	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	0	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	0	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	0	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	-	0	-	-	-	Covered	T34,T23,T35
0	-	-	-	-	-	-	1	1	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	1	0	-	Covered	T4,T10,T12
0	-	-	-	-	-	-	0	-	1	Covered	T34,T23,T35
0	-	-	-	-	-	-	0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	884	884	0	0
gen_integ_handling.ByteAccessStateChange_A	324857284	6378584	0	0
gen_integ_handling.ReadCompleteStateChange_A	324857284	6378584	0	0
gen_integ_handling.ReadbackAccessAlwaysGranted_A	324857284	158997	0	0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A	324857284	210365	0	0
gen_integ_handling.TlulSramByteTlSize_A	324857284	324751233	0	0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A	324857284	21585	0	0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A	324857284	377811	0	0
gen_integ_handling.u_state_regs_A	324857284	324751233	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	884	884	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	6378584	0	0
T1	371626	79053	0	0
T2	8717	615	0	0
T3	267007	6376	0	0
T4	192311	2181	0	0
T5	118498	13	0	0
T8	3766	51	0	0
T9	14755	894	0	0
T10	158063	1597	0	0
T11	526859	112102	0	0
T12	303911	3390	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	6378584	0	0
T1	371626	79053	0	0
T2	8717	615	0	0
T3	267007	6376	0	0
T4	192311	2181	0	0
T5	118498	13	0	0
T8	3766	51	0	0
T9	14755	894	0	0
T10	158063	1597	0	0
T11	526859	112102	0	0
T12	303911	3390	0	0

gen_integ_handling.ReadbackAccessAlwaysGranted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	158997	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	234	0	0
T24	0	505	0	0
T25	0	2	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	444	0	0
T35	0	663	0	0
T38	0	126	0	0
T39	0	4094	0	0
T40	0	4093	0	0
T41	0	848	0	0
T42	0	6	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	210365	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	603	0	0
T24	0	787	0	0
T25	0	2	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	512	0	0
T35	0	1054	0	0
T38	0	308	0	0
T39	0	6141	0	0
T40	0	8185	0	0
T41	0	906	0	0
T42	0	16	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	324751233	0	0
T1	371626	371566	0	0
T2	8717	8663	0	0
T3	267007	266951	0	0
T4	192311	192258	0	0
T5	118498	117129	0	0
T8	3766	3703	0	0
T9	14755	14660	0	0
T10	158063	157670	0	0
T11	526859	526795	0	0
T12	303911	303856	0	0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	21585	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	57	0	0
T24	0	213	0	0
T25	0	1	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	564	0	0
T35	0	942	0	0
T41	0	1077	0	0
T42	0	14	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0
T47	0	386	0	0
T48	0	425	0	0
T49	0	163	0	0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	377811	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	4044	0	0
T24	0	4807	0	0
T25	0	66	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	1004	0	0
T35	0	1880	0	0
T38	0	2062	0	0
T39	0	6142	0	0
T40	0	8192	0	0
T41	0	1990	0	0
T42	0	276	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	324751233	0	0
T1	371626	371566	0	0
T2	8717	8663	0	0
T3	267007	266951	0	0
T4	192311	192258	0	0
T5	118498	117129	0	0
T8	3766	3703	0	0
T9	14755	14660	0	0
T10	158063	157670	0	0
T11	526859	526795	0	0
T12	303911	303856	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	144	99.31
ALWAYS	104	3	3	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
ALWAYS	233	95	94	98.95
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	536	2	2	100.00
ALWAYS	547	0	0
ALWAYS	547	2	2	100.00
ALWAYS	566	2	2	100.00
ALWAYS	573	22	22	100.00
CONT_ASSIGN	627	1	1	100.00
ALWAYS	652	4	4	100.00
CONT_ASSIGN	670	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	711	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
104	3	3
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
150	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
249	1	1
251	1	1
256	1	1
257	1	1
260	1	1
261	0	1
			MISSING_ELSE
			MISSING_ELSE
265	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
270	1	1
274	1	1
275	1	1
			MISSING_ELSE
278	1	1
281	1	1
			MISSING_ELSE
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
			==> MISSING_ELSE
			MISSING_ELSE
300	1	1
301	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
			==> MISSING_ELSE
314	1	1
316		unreachable
			MISSING_ELSE
320	1	1
324	1	1
325	1	1
328	1	1
329	1	1
330	1	1
331	1	1
334	1	1
337	1	1
			MISSING_ELSE
344	1	1
346		unreachable
			MISSING_ELSE
349	1	1
351	1	1
353	1	1
359	1	1
361		unreachable
			MISSING_ELSE
365	1	1
367	1	1
369	1	1
372	1	1
			MISSING_ELSE
379	1	1
381		unreachable
			MISSING_ELSE
386	1	1
389	1	1
392	1	1
394	1	1
397	1	1
403	1	1
			==> MISSING_ELSE
411	1	1
413		unreachable
			MISSING_ELSE
416	1	1
418	1	1
420	1	1
424	1	1
426		unreachable
			MISSING_ELSE
429	1	1
432	1	1
434	1	1
437	1	1
			MISSING_ELSE
442	1	1
444		unreachable
			MISSING_ELSE
449	1	1
453	1	1
454	1	1
456	1	1
457	1	1
459	1	1
460	1	1
461	1	1
464	1	1
			MISSING_ELSE
470	1	1
472		unreachable
			MISSING_ELSE
475	1	1
477	1	1
480	1	1
482	1	1
483	1	1
484	1	1
			MISSING_ELSE
500	1	1
511	1	1
536	1	1
537	1	1
			MISSING_ELSE
547	1	1
548	1	1
566	1	1
567	1	1
573	1	1
575	1	1
584	1	1
585	1	1
587	1	1
590	1	1
592	1	1
596	1	1
597	1	1
599	1	1
600	1	1
601	1	1
602	1	1
604	1	1
606	1	1
608	1	1
611	1	1
612	1	1
614	1	1
615	1	1
			MISSING_ELSE
617	1	1
620	1	1
			MISSING_ELSE
627	1	1
652	1	1
655	1	1
659	1	1
664	1	1
670	1	1
693	1	1
710	1	1
711	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Covered	Percent
Conditions	97	93	95.88
Logical	97	93	95.88
Non-Logical	0	0
Event	0	0

 LINE       132
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T29
1	1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T10,T12
1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       260
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T23,T35
1	0	Not Covered
1	1	Not Covered

 LINE       275
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T34,T23,T35

 LINE       291
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T6,T29,T18
1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T24,T36,T37
1	Covered	T34,T23,T35

 LINE       389
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T34,T23,T35

 LINE       453
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T24,T36,T37
1	Covered	T34,T23,T35

 LINE       511
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T23,T35

 LINE       536
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       548
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       575
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T4,T8,T10
1	0	0	Covered	T1,T2,T3

 LINE       584
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T34,T23,T35
1	0	0	Covered	T1,T2,T3

 LINE       587
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       590
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       590
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       592
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       592
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       597
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       597
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T23,T35
0	1	Covered	T34,T23,T35
1	0	Covered	T1,T2,T3

 LINE       601
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       602
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T34,T23,T35
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       627
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       655
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded	T34,T23,T35	VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       659
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T34,T23,T35
1	1	1	Covered	T1,T2,T3

 LINE       693
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T34,T23,T35
0	1	0	Covered	T34,T23,T35
1	0	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	397	Covered	T34,T23,T35
StByteWrReadBackDWait	403	Covered	T34,T23,T35
StByteWrReadBackInit	304	Covered	T34,T23,T35
StPassThru	304	Covered	T1,T2,T3
StRdReadBack	275	Covered	T34,T23,T35
StRdReadBackDWait	464	Covered	T35,T24,T38
StWaitRd	268	Covered	T1,T2,T3
StWrReadBack	334	Covered	T34,T23,T35
StWrReadBackDWait	337	Covered	T35,T24,T38
StWrReadBackInit	275	Covered	T34,T23,T35
StWriteCmd	294	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	420	Covered	T34,T23,T35
StByteWrReadBackDWait->StByteWrReadBack	437	Covered	T34,T23,T35
StByteWrReadBackInit->StByteWrReadBack	397	Covered	T34,T23,T35
StByteWrReadBackInit->StByteWrReadBackDWait	403	Covered	T34,T23,T35
StPassThru->StRdReadBack	275	Covered	T34,T23,T35
StPassThru->StWaitRd	268	Covered	T1,T2,T3
StPassThru->StWrReadBackInit	275	Covered	T34,T23,T35
StRdReadBack->StPassThru	457	Covered	T34,T23,T35
StRdReadBack->StRdReadBackDWait	464	Covered	T35,T24,T38
StRdReadBackDWait->StPassThru	480	Covered	T35,T24,T38
StWaitRd->StWriteCmd	294	Covered	T1,T2,T3
StWrReadBack->StPassThru	353	Covered	T34,T23,T35
StWrReadBackDWait->StWrReadBack	372	Covered	T35,T24,T38
StWrReadBackInit->StWrReadBack	334	Covered	T34,T23,T35
StWrReadBackInit->StWrReadBackDWait	337	Covered	T35,T24,T38
StWriteCmd->StByteWrReadBackInit	304	Covered	T34,T23,T35
StWriteCmd->StPassThru	304	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	56	91.80
IF	104	2	2	100.00
CASE	249	39	34	87.18
IF	536	2	2	100.00
TERNARY	548	2	2	100.00
IF	584	16	16	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	case (gen_integ_handling.state_q)
-2-:	251	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	260	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	265	if (gen_integ_handling.byte_wr_txn)
-5-:	267	if (gen_integ_handling.byte_req_ack)
-6-:	270	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	275	(gen_integ_handling.wr_txn) ? 
-8-:	278	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	291	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	293	if (gen_integ_handling.sram_d_ack)
-11-:	303	if (gen_integ_handling.sram_a_ack)
-12-:	314	if ((EnableReadback == 1'b0))
-13-:	324	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	331	if (gen_integ_handling.d_ack)
-15-:	344	if ((EnableReadback == 1'b0))
-16-:	359	if ((EnableReadback == 1'b0))
-17-:	369	if (gen_integ_handling.d_ack)
-18-:	379	if ((EnableReadback == 1'b0))
-19-:	389	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	394	if (gen_integ_handling.d_ack)
-21-:	411	if ((EnableReadback == 1'b0))
-22-:	424	if ((EnableReadback == 1'b0))
-23-:	434	if (gen_integ_handling.d_ack)
-24-:	442	if ((EnableReadback == 1'b0))
-25-:	453	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	456	if (gen_integ_handling.d_ack)
-27-:	470	if ((EnableReadback == 1'b0))
-28-:	477	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T10
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T29,T18
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T35,T24
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T36,T37
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T24,T38
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T34,T23,T35
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T34,T23,T35
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T34,T35,T24
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T24,T36,T37
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T35,T24,T38
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T35,T24,T38
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T35,T24,T38
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	536	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	548	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	587	(gen_integ_handling.wr_phase) ? 
-3-:	590	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	592	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	597	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	601	(gen_integ_handling.wr_phase) ? 
-7-:	602	(gen_integ_handling.wr_phase) ? 
-8-:	604	if (gen_integ_handling.rd_phase)
-9-:	608	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	617	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	0	-	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	0	-	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	0	-	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	0	-	-	-	-	Covered	T34,T23,T35
1	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	-	0	-	-	-	Covered	T34,T23,T35
0	-	-	-	-	-	-	1	1	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	1	0	-	Covered	T4,T10,T12
0	-	-	-	-	-	-	0	-	1	Covered	T34,T23,T35
0	-	-	-	-	-	-	0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	884	884	0	0
gen_integ_handling.ByteAccessStateChange_A	324857284	6378584	0	0
gen_integ_handling.ReadCompleteStateChange_A	324857284	6378584	0	0
gen_integ_handling.ReadbackAccessAlwaysGranted_A	324857284	158997	0	0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A	324857284	210365	0	0
gen_integ_handling.TlulSramByteTlSize_A	324857284	324751233	0	0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A	324857284	21585	0	0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A	324857284	377811	0	0
gen_integ_handling.u_state_regs_A	324857284	324751233	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	884	884	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	6378584	0	0
T1	371626	79053	0	0
T2	8717	615	0	0
T3	267007	6376	0	0
T4	192311	2181	0	0
T5	118498	13	0	0
T8	3766	51	0	0
T9	14755	894	0	0
T10	158063	1597	0	0
T11	526859	112102	0	0
T12	303911	3390	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	6378584	0	0
T1	371626	79053	0	0
T2	8717	615	0	0
T3	267007	6376	0	0
T4	192311	2181	0	0
T5	118498	13	0	0
T8	3766	51	0	0
T9	14755	894	0	0
T10	158063	1597	0	0
T11	526859	112102	0	0
T12	303911	3390	0	0

gen_integ_handling.ReadbackAccessAlwaysGranted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	158997	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	234	0	0
T24	0	505	0	0
T25	0	2	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	444	0	0
T35	0	663	0	0
T38	0	126	0	0
T39	0	4094	0	0
T40	0	4093	0	0
T41	0	848	0	0
T42	0	6	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	210365	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	603	0	0
T24	0	787	0	0
T25	0	2	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	512	0	0
T35	0	1054	0	0
T38	0	308	0	0
T39	0	6141	0	0
T40	0	8185	0	0
T41	0	906	0	0
T42	0	16	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	324751233	0	0
T1	371626	371566	0	0
T2	8717	8663	0	0
T3	267007	266951	0	0
T4	192311	192258	0	0
T5	118498	117129	0	0
T8	3766	3703	0	0
T9	14755	14660	0	0
T10	158063	157670	0	0
T11	526859	526795	0	0
T12	303911	303856	0	0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	21585	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	57	0	0
T24	0	213	0	0
T25	0	1	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	564	0	0
T35	0	942	0	0
T41	0	1077	0	0
T42	0	14	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0
T47	0	386	0	0
T48	0	425	0	0
T49	0	163	0	0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	377811	0	0
T18	145500	0	0	0
T21	47162	0	0	0
T22	175807	0	0	0
T23	0	4044	0	0
T24	0	4807	0	0
T25	0	66	0	0
T31	25751	0	0	0
T32	170569	0	0	0
T34	9067	1004	0	0
T35	0	1880	0	0
T38	0	2062	0	0
T39	0	6142	0	0
T40	0	8192	0	0
T41	0	1990	0	0
T42	0	276	0	0
T43	724178	0	0	0
T44	8495	0	0	0
T45	231044	0	0	0
T46	61335	0	0	0

gen_integ_handling.u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324857284	324751233	0	0
T1	371626	371566	0	0
T2	8717	8663	0	0
T3	267007	266951	0	0
T4	192311	192258	0	0
T5	118498	117129	0	0
T8	3766	3703	0	0
T9	14755	14660	0	0
T10	158063	157670	0	0
T11	526859	526795	0	0
T12	303911	303856	0	0