| T801 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1267335690 |
|
|
Jun 07 07:40:48 PM PDT 24 |
Jun 07 07:40:57 PM PDT 24 |
454978576 ps |
| T802 |
/workspace/coverage/default/5.sram_ctrl_regwen.1732888045 |
|
|
Jun 07 07:33:45 PM PDT 24 |
Jun 07 07:56:36 PM PDT 24 |
13671616556 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_bijection.112690418 |
|
|
Jun 07 07:40:41 PM PDT 24 |
Jun 07 07:41:43 PM PDT 24 |
4339071293 ps |
| T804 |
/workspace/coverage/default/22.sram_ctrl_alert_test.740405635 |
|
|
Jun 07 07:35:33 PM PDT 24 |
Jun 07 07:35:35 PM PDT 24 |
13325364 ps |
| T805 |
/workspace/coverage/default/6.sram_ctrl_executable.1591811004 |
|
|
Jun 07 07:33:52 PM PDT 24 |
Jun 07 07:48:37 PM PDT 24 |
15745123965 ps |
| T806 |
/workspace/coverage/default/38.sram_ctrl_executable.1841149409 |
|
|
Jun 07 07:39:12 PM PDT 24 |
Jun 07 07:44:29 PM PDT 24 |
6067628744 ps |
| T807 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3285010325 |
|
|
Jun 07 07:41:01 PM PDT 24 |
Jun 07 07:41:04 PM PDT 24 |
32552020 ps |
| T808 |
/workspace/coverage/default/48.sram_ctrl_partial_access.554708460 |
|
|
Jun 07 07:41:02 PM PDT 24 |
Jun 07 07:43:42 PM PDT 24 |
670393956 ps |
| T809 |
/workspace/coverage/default/32.sram_ctrl_bijection.1087065896 |
|
|
Jun 07 07:37:52 PM PDT 24 |
Jun 07 07:39:14 PM PDT 24 |
3475193649 ps |
| T810 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.823755510 |
|
|
Jun 07 07:34:47 PM PDT 24 |
Jun 07 07:34:50 PM PDT 24 |
78438104 ps |
| T811 |
/workspace/coverage/default/15.sram_ctrl_bijection.3073388874 |
|
|
Jun 07 07:34:31 PM PDT 24 |
Jun 07 07:35:01 PM PDT 24 |
6602006762 ps |
| T812 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3992429502 |
|
|
Jun 07 07:35:43 PM PDT 24 |
Jun 07 07:35:51 PM PDT 24 |
175398331 ps |
| T813 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2176971870 |
|
|
Jun 07 07:38:44 PM PDT 24 |
Jun 07 07:38:49 PM PDT 24 |
37058680 ps |
| T814 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1207587900 |
|
|
Jun 07 07:33:42 PM PDT 24 |
Jun 07 07:34:11 PM PDT 24 |
896694668 ps |
| T815 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3721239474 |
|
|
Jun 07 07:33:34 PM PDT 24 |
Jun 07 07:33:48 PM PDT 24 |
679560539 ps |
| T816 |
/workspace/coverage/default/41.sram_ctrl_partial_access.2681670646 |
|
|
Jun 07 07:39:55 PM PDT 24 |
Jun 07 07:40:02 PM PDT 24 |
238858683 ps |
| T817 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1275969759 |
|
|
Jun 07 07:36:38 PM PDT 24 |
Jun 07 07:37:22 PM PDT 24 |
358614740 ps |
| T818 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3331170856 |
|
|
Jun 07 07:36:04 PM PDT 24 |
Jun 07 08:01:40 PM PDT 24 |
38446209692 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1287433862 |
|
|
Jun 07 07:40:46 PM PDT 24 |
Jun 07 07:47:00 PM PDT 24 |
20261512359 ps |
| T820 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3919092236 |
|
|
Jun 07 07:38:01 PM PDT 24 |
Jun 07 07:51:10 PM PDT 24 |
23914474164 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_smoke.890888185 |
|
|
Jun 07 07:37:50 PM PDT 24 |
Jun 07 07:37:59 PM PDT 24 |
1155568719 ps |
| T822 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.1862737382 |
|
|
Jun 07 07:37:40 PM PDT 24 |
Jun 07 07:37:50 PM PDT 24 |
535898270 ps |
| T823 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2225296266 |
|
|
Jun 07 07:39:28 PM PDT 24 |
Jun 07 08:10:59 PM PDT 24 |
3917878159 ps |
| T824 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3227332457 |
|
|
Jun 07 07:41:09 PM PDT 24 |
Jun 07 07:41:17 PM PDT 24 |
1596100936 ps |
| T825 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1705470775 |
|
|
Jun 07 07:39:28 PM PDT 24 |
Jun 07 07:39:34 PM PDT 24 |
577377368 ps |
| T826 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.137944660 |
|
|
Jun 07 07:40:46 PM PDT 24 |
Jun 07 07:41:05 PM PDT 24 |
76618819 ps |
| T827 |
/workspace/coverage/default/41.sram_ctrl_executable.4275680311 |
|
|
Jun 07 07:39:58 PM PDT 24 |
Jun 07 07:49:24 PM PDT 24 |
7807498193 ps |
| T828 |
/workspace/coverage/default/20.sram_ctrl_smoke.2869459054 |
|
|
Jun 07 07:35:04 PM PDT 24 |
Jun 07 07:35:11 PM PDT 24 |
95939950 ps |
| T829 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1472050697 |
|
|
Jun 07 07:34:29 PM PDT 24 |
Jun 07 07:34:35 PM PDT 24 |
119002674 ps |
| T830 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1871827109 |
|
|
Jun 07 07:35:01 PM PDT 24 |
Jun 07 07:35:55 PM PDT 24 |
4254862305 ps |
| T831 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.3698979160 |
|
|
Jun 07 07:34:04 PM PDT 24 |
Jun 07 07:34:14 PM PDT 24 |
545080316 ps |
| T832 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.354007303 |
|
|
Jun 07 07:33:33 PM PDT 24 |
Jun 07 07:33:38 PM PDT 24 |
90378476 ps |
| T833 |
/workspace/coverage/default/37.sram_ctrl_bijection.2271125463 |
|
|
Jun 07 07:38:50 PM PDT 24 |
Jun 07 07:39:31 PM PDT 24 |
589823091 ps |
| T834 |
/workspace/coverage/default/8.sram_ctrl_stress_all.212287077 |
|
|
Jun 07 07:34:08 PM PDT 24 |
Jun 07 09:00:03 PM PDT 24 |
57824647959 ps |
| T835 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.1588998301 |
|
|
Jun 07 07:34:31 PM PDT 24 |
Jun 07 07:34:43 PM PDT 24 |
833356089 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1479846029 |
|
|
Jun 07 07:37:20 PM PDT 24 |
Jun 07 07:38:00 PM PDT 24 |
366396643 ps |
| T837 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1655977960 |
|
|
Jun 07 07:34:28 PM PDT 24 |
Jun 07 08:23:41 PM PDT 24 |
74409803356 ps |
| T838 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3328561827 |
|
|
Jun 07 07:39:21 PM PDT 24 |
Jun 07 08:26:02 PM PDT 24 |
37249510894 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.314530468 |
|
|
Jun 07 07:34:30 PM PDT 24 |
Jun 07 07:37:09 PM PDT 24 |
355350501 ps |
| T840 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4166798354 |
|
|
Jun 07 07:34:22 PM PDT 24 |
Jun 07 07:36:54 PM PDT 24 |
167050030 ps |
| T841 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1428803530 |
|
|
Jun 07 07:34:38 PM PDT 24 |
Jun 07 07:41:29 PM PDT 24 |
15712100534 ps |
| T842 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3975735140 |
|
|
Jun 07 07:33:43 PM PDT 24 |
Jun 07 07:35:04 PM PDT 24 |
159675354 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_stress_all.2364066964 |
|
|
Jun 07 07:37:58 PM PDT 24 |
Jun 07 08:11:03 PM PDT 24 |
249427841230 ps |
| T844 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1214777491 |
|
|
Jun 07 07:33:42 PM PDT 24 |
Jun 07 07:33:58 PM PDT 24 |
201965562 ps |
| T845 |
/workspace/coverage/default/38.sram_ctrl_smoke.3492001129 |
|
|
Jun 07 07:39:05 PM PDT 24 |
Jun 07 07:39:33 PM PDT 24 |
362552908 ps |
| T846 |
/workspace/coverage/default/28.sram_ctrl_bijection.2609039566 |
|
|
Jun 07 07:36:51 PM PDT 24 |
Jun 07 07:38:05 PM PDT 24 |
17286166772 ps |
| T847 |
/workspace/coverage/default/46.sram_ctrl_bijection.2607572265 |
|
|
Jun 07 07:40:46 PM PDT 24 |
Jun 07 07:41:31 PM PDT 24 |
3654446493 ps |
| T848 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1604996809 |
|
|
Jun 07 07:39:08 PM PDT 24 |
Jun 07 08:04:53 PM PDT 24 |
81623503107 ps |
| T849 |
/workspace/coverage/default/39.sram_ctrl_smoke.2861402243 |
|
|
Jun 07 07:39:22 PM PDT 24 |
Jun 07 07:39:26 PM PDT 24 |
36675290 ps |
| T850 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.4253774687 |
|
|
Jun 07 07:40:48 PM PDT 24 |
Jun 07 07:40:57 PM PDT 24 |
371908653 ps |
| T851 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.827219450 |
|
|
Jun 07 07:34:53 PM PDT 24 |
Jun 07 07:42:14 PM PDT 24 |
16339930214 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_alert_test.911193944 |
|
|
Jun 07 07:39:22 PM PDT 24 |
Jun 07 07:39:25 PM PDT 24 |
13786669 ps |
| T853 |
/workspace/coverage/default/13.sram_ctrl_smoke.195525055 |
|
|
Jun 07 07:34:33 PM PDT 24 |
Jun 07 07:34:45 PM PDT 24 |
619320469 ps |
| T854 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2655447645 |
|
|
Jun 07 07:35:08 PM PDT 24 |
Jun 07 07:47:26 PM PDT 24 |
8508319236 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.1082823241 |
|
|
Jun 07 07:38:08 PM PDT 24 |
Jun 07 07:54:58 PM PDT 24 |
48776945618 ps |
| T856 |
/workspace/coverage/default/11.sram_ctrl_stress_all.205826567 |
|
|
Jun 07 07:34:24 PM PDT 24 |
Jun 07 07:46:31 PM PDT 24 |
100653065951 ps |
| T857 |
/workspace/coverage/default/19.sram_ctrl_smoke.2148928636 |
|
|
Jun 07 07:34:53 PM PDT 24 |
Jun 07 07:35:55 PM PDT 24 |
499811916 ps |
| T858 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.202855870 |
|
|
Jun 07 07:33:54 PM PDT 24 |
Jun 07 07:34:02 PM PDT 24 |
555451014 ps |
| T859 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3977941546 |
|
|
Jun 07 07:40:49 PM PDT 24 |
Jun 07 07:40:58 PM PDT 24 |
587189351 ps |
| T860 |
/workspace/coverage/default/0.sram_ctrl_smoke.2462693253 |
|
|
Jun 07 07:33:30 PM PDT 24 |
Jun 07 07:33:47 PM PDT 24 |
370559065 ps |
| T861 |
/workspace/coverage/default/12.sram_ctrl_executable.2103701970 |
|
|
Jun 07 07:34:32 PM PDT 24 |
Jun 07 07:37:58 PM PDT 24 |
30317986324 ps |
| T862 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3109164706 |
|
|
Jun 07 07:40:06 PM PDT 24 |
Jun 07 07:40:54 PM PDT 24 |
792157610 ps |
| T863 |
/workspace/coverage/default/3.sram_ctrl_smoke.2411352549 |
|
|
Jun 07 07:33:39 PM PDT 24 |
Jun 07 07:35:18 PM PDT 24 |
2356315475 ps |
| T864 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.4258510216 |
|
|
Jun 07 07:36:52 PM PDT 24 |
Jun 07 07:36:54 PM PDT 24 |
197148166 ps |
| T865 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2507166978 |
|
|
Jun 07 07:39:51 PM PDT 24 |
Jun 07 07:46:40 PM PDT 24 |
62966168285 ps |
| T866 |
/workspace/coverage/default/38.sram_ctrl_partial_access.3405461753 |
|
|
Jun 07 07:39:13 PM PDT 24 |
Jun 07 07:41:33 PM PDT 24 |
3000641052 ps |
| T867 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2736825314 |
|
|
Jun 07 07:38:36 PM PDT 24 |
Jun 07 07:38:39 PM PDT 24 |
26544704 ps |
| T868 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2673288339 |
|
|
Jun 07 07:41:34 PM PDT 24 |
Jun 07 07:41:36 PM PDT 24 |
81013105 ps |
| T869 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.371665097 |
|
|
Jun 07 07:40:54 PM PDT 24 |
Jun 07 07:41:21 PM PDT 24 |
86946264 ps |
| T870 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3783113766 |
|
|
Jun 07 07:33:30 PM PDT 24 |
Jun 07 07:33:47 PM PDT 24 |
3847985930 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_bijection.1072774387 |
|
|
Jun 07 07:38:43 PM PDT 24 |
Jun 07 07:40:00 PM PDT 24 |
12537124761 ps |
| T872 |
/workspace/coverage/default/35.sram_ctrl_smoke.2242342798 |
|
|
Jun 07 07:38:27 PM PDT 24 |
Jun 07 07:40:39 PM PDT 24 |
1416237596 ps |
| T873 |
/workspace/coverage/default/38.sram_ctrl_regwen.942335931 |
|
|
Jun 07 07:39:11 PM PDT 24 |
Jun 07 07:51:13 PM PDT 24 |
12397361560 ps |
| T874 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.870011307 |
|
|
Jun 07 07:36:37 PM PDT 24 |
Jun 07 07:40:32 PM PDT 24 |
2495869939 ps |
| T875 |
/workspace/coverage/default/49.sram_ctrl_stress_all.1665128016 |
|
|
Jun 07 07:41:09 PM PDT 24 |
Jun 07 09:14:40 PM PDT 24 |
163708613838 ps |
| T876 |
/workspace/coverage/default/12.sram_ctrl_stress_all.649601368 |
|
|
Jun 07 07:34:30 PM PDT 24 |
Jun 07 07:59:18 PM PDT 24 |
64818967167 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3336607105 |
|
|
Jun 07 07:34:08 PM PDT 24 |
Jun 07 07:34:48 PM PDT 24 |
638988225 ps |
| T878 |
/workspace/coverage/default/6.sram_ctrl_regwen.3515206128 |
|
|
Jun 07 07:33:56 PM PDT 24 |
Jun 07 07:51:02 PM PDT 24 |
27022100034 ps |
| T879 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.4082453551 |
|
|
Jun 07 07:40:46 PM PDT 24 |
Jun 07 08:15:01 PM PDT 24 |
16692799768 ps |
| T880 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.4123103939 |
|
|
Jun 07 07:35:58 PM PDT 24 |
Jun 07 07:42:26 PM PDT 24 |
8389321027 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2172180672 |
|
|
Jun 07 07:35:10 PM PDT 24 |
Jun 07 07:43:06 PM PDT 24 |
2262310030 ps |
| T882 |
/workspace/coverage/default/7.sram_ctrl_partial_access.3435509224 |
|
|
Jun 07 07:33:57 PM PDT 24 |
Jun 07 07:34:22 PM PDT 24 |
529206702 ps |
| T883 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3170572890 |
|
|
Jun 07 07:35:41 PM PDT 24 |
Jun 07 07:35:48 PM PDT 24 |
66022353 ps |
| T884 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1196578462 |
|
|
Jun 07 07:35:51 PM PDT 24 |
Jun 07 07:36:12 PM PDT 24 |
3350730254 ps |
| T885 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3051173579 |
|
|
Jun 07 07:33:42 PM PDT 24 |
Jun 07 07:34:34 PM PDT 24 |
5413225517 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_regwen.2274796285 |
|
|
Jun 07 07:37:51 PM PDT 24 |
Jun 07 07:58:04 PM PDT 24 |
25759897881 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.1603666827 |
|
|
Jun 07 07:34:39 PM PDT 24 |
Jun 07 07:35:18 PM PDT 24 |
500492953 ps |
| T888 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2482733293 |
|
|
Jun 07 07:34:44 PM PDT 24 |
Jun 07 07:44:16 PM PDT 24 |
41395596645 ps |
| T889 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3006483997 |
|
|
Jun 07 07:34:44 PM PDT 24 |
Jun 07 07:34:48 PM PDT 24 |
16424084 ps |
| T890 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1642995219 |
|
|
Jun 07 07:40:53 PM PDT 24 |
Jun 07 08:50:09 PM PDT 24 |
125426879750 ps |
| T891 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.1687235244 |
|
|
Jun 07 07:40:53 PM PDT 24 |
Jun 07 07:40:55 PM PDT 24 |
53177727 ps |
| T892 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.296747420 |
|
|
Jun 07 07:33:51 PM PDT 24 |
Jun 07 07:47:10 PM PDT 24 |
30864727806 ps |
| T893 |
/workspace/coverage/default/37.sram_ctrl_alert_test.636327346 |
|
|
Jun 07 07:39:05 PM PDT 24 |
Jun 07 07:39:08 PM PDT 24 |
32527549 ps |
| T894 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.69854060 |
|
|
Jun 07 07:34:42 PM PDT 24 |
Jun 07 07:34:52 PM PDT 24 |
1645911229 ps |
| T895 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1675186703 |
|
|
Jun 07 07:41:03 PM PDT 24 |
Jun 07 07:41:06 PM PDT 24 |
35089026 ps |
| T896 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2490476358 |
|
|
Jun 07 07:36:29 PM PDT 24 |
Jun 07 07:36:35 PM PDT 24 |
290175276 ps |
| T897 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.481644200 |
|
|
Jun 07 07:34:48 PM PDT 24 |
Jun 07 07:34:51 PM PDT 24 |
124299012 ps |
| T898 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2664848843 |
|
|
Jun 07 07:40:44 PM PDT 24 |
Jun 07 07:46:56 PM PDT 24 |
9733946314 ps |
| T899 |
/workspace/coverage/default/42.sram_ctrl_alert_test.501643119 |
|
|
Jun 07 07:40:21 PM PDT 24 |
Jun 07 07:40:23 PM PDT 24 |
37467263 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2567898572 |
|
|
Jun 07 07:36:36 PM PDT 24 |
Jun 07 07:38:11 PM PDT 24 |
132345956 ps |
| T85 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2665816466 |
|
|
Jun 07 07:36:02 PM PDT 24 |
Jun 07 07:36:07 PM PDT 24 |
63778268 ps |
| T901 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1702289771 |
|
|
Jun 07 07:41:00 PM PDT 24 |
Jun 07 07:46:49 PM PDT 24 |
59338739303 ps |
| T902 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3159336971 |
|
|
Jun 07 07:34:30 PM PDT 24 |
Jun 07 07:34:39 PM PDT 24 |
1119493431 ps |
| T903 |
/workspace/coverage/default/27.sram_ctrl_regwen.3647170169 |
|
|
Jun 07 07:36:44 PM PDT 24 |
Jun 07 07:45:38 PM PDT 24 |
7122775275 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3185197599 |
|
|
Jun 07 07:33:33 PM PDT 24 |
Jun 07 07:39:10 PM PDT 24 |
14419573133 ps |
| T905 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1426333442 |
|
|
Jun 07 07:40:53 PM PDT 24 |
Jun 07 07:46:30 PM PDT 24 |
2849829556 ps |
| T906 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2431155505 |
|
|
Jun 07 07:38:34 PM PDT 24 |
Jun 07 07:40:01 PM PDT 24 |
142962949 ps |
| T907 |
/workspace/coverage/default/44.sram_ctrl_partial_access.580283426 |
|
|
Jun 07 07:40:43 PM PDT 24 |
Jun 07 07:40:45 PM PDT 24 |
309365158 ps |
| T908 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.505408998 |
|
|
Jun 07 07:35:00 PM PDT 24 |
Jun 07 07:35:05 PM PDT 24 |
233325859 ps |
| T909 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2115803962 |
|
|
Jun 07 07:33:56 PM PDT 24 |
Jun 07 07:34:03 PM PDT 24 |
1795608014 ps |
| T910 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3573931803 |
|
|
Jun 07 07:34:40 PM PDT 24 |
Jun 07 07:35:05 PM PDT 24 |
404212633 ps |
| T911 |
/workspace/coverage/default/1.sram_ctrl_bijection.3535304731 |
|
|
Jun 07 07:33:43 PM PDT 24 |
Jun 07 07:34:50 PM PDT 24 |
16314830845 ps |
| T912 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2332457047 |
|
|
Jun 07 07:38:00 PM PDT 24 |
Jun 07 07:44:07 PM PDT 24 |
14542030351 ps |
| T913 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1757657913 |
|
|
Jun 07 07:40:34 PM PDT 24 |
Jun 07 07:41:12 PM PDT 24 |
170605393 ps |
| T914 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2312169789 |
|
|
Jun 07 07:41:02 PM PDT 24 |
Jun 07 07:41:10 PM PDT 24 |
1661722206 ps |
| T915 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2716818368 |
|
|
Jun 07 07:33:52 PM PDT 24 |
Jun 07 07:33:57 PM PDT 24 |
87576613 ps |
| T916 |
/workspace/coverage/default/37.sram_ctrl_smoke.2076831666 |
|
|
Jun 07 07:38:49 PM PDT 24 |
Jun 07 07:39:02 PM PDT 24 |
1708637742 ps |
| T917 |
/workspace/coverage/default/42.sram_ctrl_stress_all.1245206014 |
|
|
Jun 07 07:40:22 PM PDT 24 |
Jun 07 08:20:22 PM PDT 24 |
29064828232 ps |
| T918 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.971157176 |
|
|
Jun 07 07:39:54 PM PDT 24 |
Jun 07 07:40:37 PM PDT 24 |
183046954 ps |
| T919 |
/workspace/coverage/default/14.sram_ctrl_smoke.4269403384 |
|
|
Jun 07 07:34:30 PM PDT 24 |
Jun 07 07:34:54 PM PDT 24 |
12008917841 ps |
| T920 |
/workspace/coverage/default/20.sram_ctrl_regwen.3020258022 |
|
|
Jun 07 07:35:02 PM PDT 24 |
Jun 07 08:07:12 PM PDT 24 |
4210580494 ps |
| T921 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3537923494 |
|
|
Jun 07 07:39:58 PM PDT 24 |
Jun 07 07:42:33 PM PDT 24 |
2740731838 ps |
| T922 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3031096488 |
|
|
Jun 07 07:36:49 PM PDT 24 |
Jun 07 07:38:14 PM PDT 24 |
5104930522 ps |
| T923 |
/workspace/coverage/default/30.sram_ctrl_executable.2476484527 |
|
|
Jun 07 07:37:19 PM PDT 24 |
Jun 07 07:59:03 PM PDT 24 |
110957402675 ps |
| T924 |
/workspace/coverage/default/18.sram_ctrl_bijection.465795837 |
|
|
Jun 07 07:34:47 PM PDT 24 |
Jun 07 07:35:55 PM PDT 24 |
6599429481 ps |
| T925 |
/workspace/coverage/default/30.sram_ctrl_alert_test.193747101 |
|
|
Jun 07 07:37:29 PM PDT 24 |
Jun 07 07:37:32 PM PDT 24 |
36060651 ps |
| T926 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.344286094 |
|
|
Jun 07 07:37:51 PM PDT 24 |
Jun 07 07:42:32 PM PDT 24 |
39519474397 ps |
| T927 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2739925553 |
|
|
Jun 07 07:37:55 PM PDT 24 |
Jun 07 07:38:03 PM PDT 24 |
421012381 ps |
| T928 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3691893555 |
|
|
Jun 07 07:41:01 PM PDT 24 |
Jun 07 07:42:53 PM PDT 24 |
153338927 ps |
| T929 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2370799356 |
|
|
Jun 07 07:35:34 PM PDT 24 |
Jun 07 07:39:54 PM PDT 24 |
9737635591 ps |
| T930 |
/workspace/coverage/default/46.sram_ctrl_regwen.1537198771 |
|
|
Jun 07 07:40:56 PM PDT 24 |
Jun 07 08:14:57 PM PDT 24 |
130274103987 ps |
| T931 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2681071441 |
|
|
Jun 07 07:40:19 PM PDT 24 |
Jun 07 07:43:59 PM PDT 24 |
1895774628 ps |
| T932 |
/workspace/coverage/default/12.sram_ctrl_regwen.481255386 |
|
|
Jun 07 07:34:31 PM PDT 24 |
Jun 07 07:45:13 PM PDT 24 |
30832837968 ps |
| T933 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.878136493 |
|
|
Jun 07 07:33:45 PM PDT 24 |
Jun 07 07:38:36 PM PDT 24 |
14412263255 ps |
| T54 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2751070005 |
|
|
Jun 07 07:28:41 PM PDT 24 |
Jun 07 07:28:43 PM PDT 24 |
42748318 ps |
| T55 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2084677363 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:23 PM PDT 24 |
17978933 ps |
| T50 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2168188333 |
|
|
Jun 07 07:28:08 PM PDT 24 |
Jun 07 07:28:13 PM PDT 24 |
377056118 ps |
| T94 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.915362156 |
|
|
Jun 07 07:28:48 PM PDT 24 |
Jun 07 07:28:51 PM PDT 24 |
20991910 ps |
| T934 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1117391540 |
|
|
Jun 07 07:28:57 PM PDT 24 |
Jun 07 07:29:03 PM PDT 24 |
299287528 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1584549279 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:18 PM PDT 24 |
22491410 ps |
| T67 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4045923048 |
|
|
Jun 07 07:28:39 PM PDT 24 |
Jun 07 07:28:45 PM PDT 24 |
1974514568 ps |
| T125 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3848529398 |
|
|
Jun 07 07:28:57 PM PDT 24 |
Jun 07 07:29:01 PM PDT 24 |
41097593 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4075928563 |
|
|
Jun 07 07:28:27 PM PDT 24 |
Jun 07 07:28:31 PM PDT 24 |
12055514 ps |
| T935 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.776087790 |
|
|
Jun 07 07:28:07 PM PDT 24 |
Jun 07 07:28:12 PM PDT 24 |
123633322 ps |
| T69 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.52996491 |
|
|
Jun 07 07:28:56 PM PDT 24 |
Jun 07 07:29:02 PM PDT 24 |
239822652 ps |
| T104 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.294444892 |
|
|
Jun 07 07:28:32 PM PDT 24 |
Jun 07 07:28:35 PM PDT 24 |
42774858 ps |
| T96 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.836018195 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
29487758 ps |
| T105 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1055930305 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:20 PM PDT 24 |
30087016 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1531828101 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:39 PM PDT 24 |
212554253 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.513647094 |
|
|
Jun 07 07:28:24 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
49950932 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1416713747 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:22 PM PDT 24 |
16315273 ps |
| T51 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3792241791 |
|
|
Jun 07 07:28:38 PM PDT 24 |
Jun 07 07:28:43 PM PDT 24 |
182917730 ps |
| T937 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1624500176 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:33 PM PDT 24 |
38651069 ps |
| T71 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.569154161 |
|
|
Jun 07 07:28:47 PM PDT 24 |
Jun 07 07:28:53 PM PDT 24 |
414248061 ps |
| T938 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3265788384 |
|
|
Jun 07 07:29:02 PM PDT 24 |
Jun 07 07:29:08 PM PDT 24 |
57685003 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1545007398 |
|
|
Jun 07 07:28:24 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
36613850 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1125199786 |
|
|
Jun 07 07:28:10 PM PDT 24 |
Jun 07 07:28:14 PM PDT 24 |
21537120 ps |
| T52 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.195617949 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:53 PM PDT 24 |
103376731 ps |
| T940 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.947337142 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
35537003 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.64437552 |
|
|
Jun 07 07:28:08 PM PDT 24 |
Jun 07 07:28:13 PM PDT 24 |
575028282 ps |
| T72 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1577844441 |
|
|
Jun 07 07:28:56 PM PDT 24 |
Jun 07 07:29:01 PM PDT 24 |
29687183 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2360185146 |
|
|
Jun 07 07:28:33 PM PDT 24 |
Jun 07 07:28:40 PM PDT 24 |
130979779 ps |
| T942 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3121774361 |
|
|
Jun 07 07:28:26 PM PDT 24 |
Jun 07 07:28:31 PM PDT 24 |
23803945 ps |
| T116 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1616301128 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
96475036 ps |
| T73 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2009741146 |
|
|
Jun 07 07:28:19 PM PDT 24 |
Jun 07 07:28:26 PM PDT 24 |
20674738 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3599401814 |
|
|
Jun 07 07:29:03 PM PDT 24 |
Jun 07 07:29:11 PM PDT 24 |
452466962 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2815450619 |
|
|
Jun 07 07:28:10 PM PDT 24 |
Jun 07 07:28:14 PM PDT 24 |
30081005 ps |
| T944 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3038094076 |
|
|
Jun 07 07:28:19 PM PDT 24 |
Jun 07 07:28:24 PM PDT 24 |
17994676 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3428915032 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:19 PM PDT 24 |
52960927 ps |
| T945 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3415106728 |
|
|
Jun 07 07:28:48 PM PDT 24 |
Jun 07 07:28:51 PM PDT 24 |
50354208 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.711336654 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:54 PM PDT 24 |
29322900 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2845000542 |
|
|
Jun 07 07:28:39 PM PDT 24 |
Jun 07 07:28:44 PM PDT 24 |
145341225 ps |
| T76 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1977303623 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:54 PM PDT 24 |
50883598 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3910747369 |
|
|
Jun 07 07:28:55 PM PDT 24 |
Jun 07 07:29:00 PM PDT 24 |
362330515 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.490488015 |
|
|
Jun 07 07:28:41 PM PDT 24 |
Jun 07 07:28:47 PM PDT 24 |
167807020 ps |
| T949 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.499177103 |
|
|
Jun 07 07:28:11 PM PDT 24 |
Jun 07 07:28:17 PM PDT 24 |
56137677 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.908617085 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
37139563 ps |
| T77 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3351185717 |
|
|
Jun 07 07:28:33 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
223179595 ps |
| T951 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2863300163 |
|
|
Jun 07 07:29:00 PM PDT 24 |
Jun 07 07:29:04 PM PDT 24 |
62815656 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.843593971 |
|
|
Jun 07 07:28:56 PM PDT 24 |
Jun 07 07:29:01 PM PDT 24 |
447451404 ps |
| T112 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1850135212 |
|
|
Jun 07 07:28:38 PM PDT 24 |
Jun 07 07:28:44 PM PDT 24 |
1844615883 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1352810974 |
|
|
Jun 07 07:28:31 PM PDT 24 |
Jun 07 07:28:34 PM PDT 24 |
30216567 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3085269934 |
|
|
Jun 07 07:28:35 PM PDT 24 |
Jun 07 07:28:41 PM PDT 24 |
428146886 ps |
| T117 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3966208352 |
|
|
Jun 07 07:28:33 PM PDT 24 |
Jun 07 07:28:37 PM PDT 24 |
420231165 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1368232363 |
|
|
Jun 07 07:28:24 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
26000383 ps |
| T955 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2428845188 |
|
|
Jun 07 07:28:41 PM PDT 24 |
Jun 07 07:28:45 PM PDT 24 |
32458784 ps |
| T956 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4052505272 |
|
|
Jun 07 07:28:09 PM PDT 24 |
Jun 07 07:28:15 PM PDT 24 |
416900299 ps |
| T79 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2051917972 |
|
|
Jun 07 07:28:32 PM PDT 24 |
Jun 07 07:28:37 PM PDT 24 |
839053811 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3646672838 |
|
|
Jun 07 07:28:36 PM PDT 24 |
Jun 07 07:28:43 PM PDT 24 |
236969339 ps |
| T958 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2108276392 |
|
|
Jun 07 07:28:41 PM PDT 24 |
Jun 07 07:28:44 PM PDT 24 |
50390576 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3901304630 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:23 PM PDT 24 |
1666467275 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3148500298 |
|
|
Jun 07 07:28:26 PM PDT 24 |
Jun 07 07:28:32 PM PDT 24 |
407126423 ps |
| T959 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2610998361 |
|
|
Jun 07 07:28:38 PM PDT 24 |
Jun 07 07:28:41 PM PDT 24 |
28301664 ps |
| T960 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3713527128 |
|
|
Jun 07 07:28:57 PM PDT 24 |
Jun 07 07:29:01 PM PDT 24 |
44988958 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2254626230 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:25 PM PDT 24 |
544432942 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.396399712 |
|
|
Jun 07 07:28:38 PM PDT 24 |
Jun 07 07:28:42 PM PDT 24 |
154234038 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.417316098 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:20 PM PDT 24 |
260268297 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1239567655 |
|
|
Jun 07 07:29:30 PM PDT 24 |
Jun 07 07:29:34 PM PDT 24 |
15204299 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3690340609 |
|
|
Jun 07 07:28:34 PM PDT 24 |
Jun 07 07:28:37 PM PDT 24 |
71782282 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1846404961 |
|
|
Jun 07 07:28:26 PM PDT 24 |
Jun 07 07:28:31 PM PDT 24 |
345432657 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1415551650 |
|
|
Jun 07 07:28:35 PM PDT 24 |
Jun 07 07:28:40 PM PDT 24 |
84710921 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4150973001 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:22 PM PDT 24 |
170174142 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.924505624 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
11439129 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1231864598 |
|
|
Jun 07 07:28:59 PM PDT 24 |
Jun 07 07:29:05 PM PDT 24 |
33904886 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3255103447 |
|
|
Jun 07 07:28:08 PM PDT 24 |
Jun 07 07:28:13 PM PDT 24 |
287667731 ps |
| T119 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1368707636 |
|
|
Jun 07 07:28:59 PM PDT 24 |
Jun 07 07:29:04 PM PDT 24 |
217254545 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2685453704 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:25 PM PDT 24 |
313976511 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1915129535 |
|
|
Jun 07 07:28:39 PM PDT 24 |
Jun 07 07:28:44 PM PDT 24 |
425855902 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2664170990 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:25 PM PDT 24 |
54262599 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1606276170 |
|
|
Jun 07 07:28:36 PM PDT 24 |
Jun 07 07:28:39 PM PDT 24 |
13622942 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1299549792 |
|
|
Jun 07 07:28:24 PM PDT 24 |
Jun 07 07:28:31 PM PDT 24 |
268962190 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1686151498 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:56 PM PDT 24 |
131884119 ps |
| T973 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4183315159 |
|
|
Jun 07 07:28:36 PM PDT 24 |
Jun 07 07:28:40 PM PDT 24 |
75307513 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2486474815 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:30 PM PDT 24 |
96389543 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1362241879 |
|
|
Jun 07 07:28:58 PM PDT 24 |
Jun 07 07:29:02 PM PDT 24 |
18779721 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3159455875 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:25 PM PDT 24 |
68145996 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3990025100 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:54 PM PDT 24 |
67283059 ps |
| T978 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.709774982 |
|
|
Jun 07 07:28:57 PM PDT 24 |
Jun 07 07:29:04 PM PDT 24 |
210374730 ps |
| T979 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.634054588 |
|
|
Jun 07 07:28:48 PM PDT 24 |
Jun 07 07:28:51 PM PDT 24 |
45286221 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1045198082 |
|
|
Jun 07 07:28:55 PM PDT 24 |
Jun 07 07:29:00 PM PDT 24 |
139198968 ps |
| T120 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2303418351 |
|
|
Jun 07 07:28:48 PM PDT 24 |
Jun 07 07:28:53 PM PDT 24 |
415184825 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2491498151 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:54 PM PDT 24 |
42633796 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.960422118 |
|
|
Jun 07 07:28:59 PM PDT 24 |
Jun 07 07:29:03 PM PDT 24 |
24403147 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2018446306 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:22 PM PDT 24 |
1645756041 ps |
| T982 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2775071490 |
|
|
Jun 07 07:28:18 PM PDT 24 |
Jun 07 07:28:23 PM PDT 24 |
43030485 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2304236609 |
|
|
Jun 07 07:28:33 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
370401196 ps |
| T90 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.136796681 |
|
|
Jun 07 07:28:28 PM PDT 24 |
Jun 07 07:28:34 PM PDT 24 |
2366886912 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1701998792 |
|
|
Jun 07 07:28:08 PM PDT 24 |
Jun 07 07:28:13 PM PDT 24 |
42599918 ps |
| T985 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1910561727 |
|
|
Jun 07 07:28:48 PM PDT 24 |
Jun 07 07:28:53 PM PDT 24 |
246456943 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2895221268 |
|
|
Jun 07 07:28:16 PM PDT 24 |
Jun 07 07:28:19 PM PDT 24 |
39887978 ps |
| T987 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1645482345 |
|
|
Jun 07 07:28:41 PM PDT 24 |
Jun 07 07:28:44 PM PDT 24 |
20007498 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.174045018 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:23 PM PDT 24 |
41520355 ps |
| T91 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.426525658 |
|
|
Jun 07 07:28:36 PM PDT 24 |
Jun 07 07:28:42 PM PDT 24 |
1740050204 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3831030155 |
|
|
Jun 07 07:28:42 PM PDT 24 |
Jun 07 07:28:46 PM PDT 24 |
76954488 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4129052951 |
|
|
Jun 07 07:28:24 PM PDT 24 |
Jun 07 07:28:31 PM PDT 24 |
252691092 ps |
| T114 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2717212916 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:32 PM PDT 24 |
683848890 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3402692003 |
|
|
Jun 07 07:28:19 PM PDT 24 |
Jun 07 07:28:26 PM PDT 24 |
477908422 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1272915237 |
|
|
Jun 07 07:29:01 PM PDT 24 |
Jun 07 07:29:05 PM PDT 24 |
39466979 ps |
| T123 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.20250051 |
|
|
Jun 07 07:28:42 PM PDT 24 |
Jun 07 07:28:47 PM PDT 24 |
959677318 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.861151184 |
|
|
Jun 07 07:28:49 PM PDT 24 |
Jun 07 07:28:53 PM PDT 24 |
27929438 ps |
| T994 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.832055118 |
|
|
Jun 07 07:28:57 PM PDT 24 |
Jun 07 07:29:05 PM PDT 24 |
242448525 ps |
| T995 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.667085481 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
25401327 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3562125239 |
|
|
Jun 07 07:28:33 PM PDT 24 |
Jun 07 07:28:38 PM PDT 24 |
91548084 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3499801848 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:20 PM PDT 24 |
59483727 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3107147308 |
|
|
Jun 07 07:28:17 PM PDT 24 |
Jun 07 07:28:22 PM PDT 24 |
176629087 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1468404949 |
|
|
Jun 07 07:28:50 PM PDT 24 |
Jun 07 07:28:55 PM PDT 24 |
100650389 ps |
| T115 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3539415935 |
|
|
Jun 07 07:28:58 PM PDT 24 |
Jun 07 07:29:04 PM PDT 24 |
642897215 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3546773871 |
|
|
Jun 07 07:28:01 PM PDT 24 |
Jun 07 07:28:10 PM PDT 24 |
4245848217 ps |
| T1000 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1423474661 |
|
|
Jun 07 07:28:25 PM PDT 24 |
Jun 07 07:28:29 PM PDT 24 |
55396396 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2548203289 |
|
|
Jun 07 07:28:58 PM PDT 24 |
Jun 07 07:29:04 PM PDT 24 |
782229334 ps |