Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.36	98.99	92.48	99.31	100.00	95.26	98.38	97.07

Total test records in report: 1015

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1943041177			Jun 07 07:28:34 PM PDT 24	Jun 07 07:28:39 PM PDT 24	144937290 ps
T1002	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3764058833			Jun 07 07:28:42 PM PDT 24	Jun 07 07:28:48 PM PDT 24	238765222 ps
T1003	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1989107057			Jun 07 07:28:16 PM PDT 24	Jun 07 07:28:19 PM PDT 24	214818692 ps
T1004	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3725734307			Jun 07 07:28:09 PM PDT 24	Jun 07 07:28:12 PM PDT 24	25601100 ps
T1005	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1052242848			Jun 07 07:28:59 PM PDT 24	Jun 07 07:29:03 PM PDT 24	37198342 ps
T1006	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3534224462			Jun 07 07:28:07 PM PDT 24	Jun 07 07:28:11 PM PDT 24	26714372 ps
T1007	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.615019756			Jun 07 07:28:51 PM PDT 24	Jun 07 07:28:58 PM PDT 24	410955519 ps
T1008	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1009312988			Jun 07 07:28:39 PM PDT 24	Jun 07 07:28:42 PM PDT 24	120020880 ps
T1009	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1203537220			Jun 07 07:28:17 PM PDT 24	Jun 07 07:28:21 PM PDT 24	31024658 ps
T1010	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2850718640			Jun 07 07:28:38 PM PDT 24	Jun 07 07:28:45 PM PDT 24	689028143 ps
T1011	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4229928169			Jun 07 07:28:49 PM PDT 24	Jun 07 07:28:52 PM PDT 24	26054705 ps
T1012	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.154262560			Jun 07 07:28:17 PM PDT 24	Jun 07 07:28:23 PM PDT 24	99676759 ps
T1013	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1129094788			Jun 07 07:28:51 PM PDT 24	Jun 07 07:28:57 PM PDT 24	207201335 ps
T1014	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2860213198			Jun 07 07:28:18 PM PDT 24	Jun 07 07:28:23 PM PDT 24	38663444 ps
T1015	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2795967372			Jun 07 07:28:17 PM PDT 24	Jun 07 07:28:22 PM PDT 24	43568960 ps

Test location	/workspace/coverage/default/31.sram_ctrl_access_during_key_req.2085843677
Short name	T3
Test name
Test status
Simulation time	8091135790 ps
CPU time	648.16 seconds
Started	Jun 07 07:37:42 PM PDT 24
Finished	Jun 07 07:48:34 PM PDT 24
Peak memory	367500 kb
Host	smart-d1add203-7ee6-4114-ab2d-536db756a65e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085843677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.2085843677
Directory	/workspace/31.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.923678891
Short name	T24
Test name
Test status
Simulation time	1711742554 ps
CPU time	116.95 seconds
Started	Jun 07 07:34:22 PM PDT 24
Finished	Jun 07 07:36:24 PM PDT 24
Peak memory	361104 kb
Host	smart-b82bb252-cf36-417c-af71-57e3e8aa48f5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=923678891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.923678891
Directory	/workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_all.2161475187
Short name	T22
Test name
Test status
Simulation time	70322882121 ps
CPU time	1153.88 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 08:00:00 PM PDT 24
Peak memory	366616 kb
Host	smart-fd81209b-90ce-4c93-a759-fe8dab1e8f86
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161475187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.2161475187
Directory	/workspace/45.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all.3970699397
Short name	T126
Test name
Test status
Simulation time	8862706206 ps
CPU time	2785.32 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 08:21:10 PM PDT 24
Peak memory	376440 kb
Host	smart-b2af3301-e108-42d8-a223-348abca80c00
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970699397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.3970699397
Directory	/workspace/16.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3792241791
Short name	T51
Test name
Test status
Simulation time	182917730 ps
CPU time	2.52 seconds
Started	Jun 07 07:28:38 PM PDT 24
Finished	Jun 07 07:28:43 PM PDT 24
Peak memory	210556 kb
Host	smart-8df8aa9f-716e-496b-9c99-e131312ed9d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792241791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3792241791
Directory	/workspace/10.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/33.sram_ctrl_lc_escalation.1189583308
Short name	T6
Test name
Test status
Simulation time	721719872 ps
CPU time	6.43 seconds
Started	Jun 07 07:38:04 PM PDT 24
Finished	Jun 07 07:38:12 PM PDT 24
Peak memory	202896 kb
Host	smart-77a175a5-5d47-49fa-8557-b79d6560e314
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189583308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.1189583308
Directory	/workspace/33.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2281427382
Short name	T40
Test name
Test status
Simulation time	615601905 ps
CPU time	166.07 seconds
Started	Jun 07 07:33:51 PM PDT 24
Finished	Jun 07 07:36:40 PM PDT 24
Peak memory	359552 kb
Host	smart-018ffd18-ca39-4a74-b554-7d5c9bf54947
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2281427382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2281427382
Directory	/workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3466639288
Short name	T101
Test name
Test status
Simulation time	103638295494 ps
CPU time	329.26 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:40:13 PM PDT 24
Peak memory	202964 kb
Host	smart-51364d8f-a4c1-41e8-8a92-7b3f0b57a343
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466639288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.3466639288
Directory	/workspace/15.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.52996491
Short name	T69
Test name
Test status
Simulation time	239822652 ps
CPU time	2.08 seconds
Started	Jun 07 07:28:56 PM PDT 24
Finished	Jun 07 07:29:02 PM PDT 24
Peak memory	202364 kb
Host	smart-8b6f1c9f-dd68-4678-beb4-af6f6f4d261d
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52996491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base _test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.52996491
Directory	/workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/default/3.sram_ctrl_alert_test.1007976245
Short name	T13
Test name
Test status
Simulation time	52338282 ps
CPU time	0.67 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:48 PM PDT 24
Peak memory	202508 kb
Host	smart-a7ab0bd1-fce1-4891-bd8b-a14a7af72d5d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007976245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1007976245
Directory	/workspace/3.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_ram_cfg.2708542114
Short name	T26
Test name
Test status
Simulation time	28770995 ps
CPU time	0.81 seconds
Started	Jun 07 07:38:58 PM PDT 24
Finished	Jun 07 07:39:01 PM PDT 24
Peak memory	202900 kb
Host	smart-0ee25055-e8ce-4d49-941e-66936fd841b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708542114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2708542114
Directory	/workspace/37.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.20250051
Short name	T123
Test name
Test status
Simulation time	959677318 ps
CPU time	2.38 seconds
Started	Jun 07 07:28:42 PM PDT 24
Finished	Jun 07 07:28:47 PM PDT 24
Peak memory	210568 kb
Host	smart-7a463f85-e69e-4a61-894e-70b0f028089d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.sram_ctrl_tl_intg_err.20250051
Directory	/workspace/12.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3539415935
Short name	T115
Test name
Test status
Simulation time	642897215 ps
CPU time	2.63 seconds
Started	Jun 07 07:28:58 PM PDT 24
Finished	Jun 07 07:29:04 PM PDT 24
Peak memory	210576 kb
Host	smart-d6a410e4-8586-4e79-ab33-457f0c4959f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539415935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.3539415935
Directory	/workspace/19.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/11.sram_ctrl_regwen.3223843501
Short name	T16
Test name
Test status
Simulation time	1443202191 ps
CPU time	22.98 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	202932 kb
Host	smart-097f63cb-0ccc-49ca-89f5-0c810d556aae
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223843501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3223843501
Directory	/workspace/11.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_executable.3812500232
Short name	T357
Test name
Test status
Simulation time	13438097345 ps
CPU time	1294.71 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:55:23 PM PDT 24
Peak memory	372504 kb
Host	smart-fb488ddc-8142-4d15-be4c-b1add57c5010
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812500232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.3812500232
Directory	/workspace/1.sram_ctrl_executable/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1850135212
Short name	T112
Test name
Test status
Simulation time	1844615883 ps
CPU time	2.91 seconds
Started	Jun 07 07:28:38 PM PDT 24
Finished	Jun 07 07:28:44 PM PDT 24
Peak memory	210588 kb
Host	smart-1be8ccff-a729-4827-9e55-d381c7fe1ae1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850135212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.1850135212
Directory	/workspace/11.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2303418351
Short name	T120
Test name
Test status
Simulation time	415184825 ps
CPU time	1.68 seconds
Started	Jun 07 07:28:48 PM PDT 24
Finished	Jun 07 07:28:53 PM PDT 24
Peak memory	210604 kb
Host	smart-97c762da-de6e-4bb2-88d1-544c629af13c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303418351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.2303418351
Directory	/workspace/15.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.709774982
Short name	T978
Test name
Test status
Simulation time	210374730 ps
CPU time	2.71 seconds
Started	Jun 07 07:28:57 PM PDT 24
Finished	Jun 07 07:29:04 PM PDT 24
Peak memory	210536 kb
Host	smart-cd14038a-3855-46bf-b63c-ea1bb56bc63e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709774982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sram_ctrl_tl_intg_err.709774982
Directory	/workspace/18.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.502630131
Short name	T1
Test name
Test status
Simulation time	16157566081 ps
CPU time	273.08 seconds
Started	Jun 07 07:34:25 PM PDT 24
Finished	Jun 07 07:39:02 PM PDT 24
Peak memory	203048 kb
Host	smart-0e149237-a269-4a3b-8b51-a8d629196f7b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502630131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.sram_ctrl_partial_access_b2b.502630131
Directory	/workspace/11.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3534224462
Short name	T1006
Test name
Test status
Simulation time	26714372 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:07 PM PDT 24
Finished	Jun 07 07:28:11 PM PDT 24
Peak memory	201588 kb
Host	smart-71889e60-975d-4201-8022-1a8479ff3aab
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534224462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.3534224462
Directory	/workspace/0.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1701998792
Short name	T984
Test name
Test status
Simulation time	42599918 ps
CPU time	1.89 seconds
Started	Jun 07 07:28:08 PM PDT 24
Finished	Jun 07 07:28:13 PM PDT 24
Peak memory	202400 kb
Host	smart-7da80417-ec1b-462d-91f0-4b0a7f6ee0f2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701998792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1701998792
Directory	/workspace/0.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1125199786
Short name	T939
Test name
Test status
Simulation time	21537120 ps
CPU time	0.62 seconds
Started	Jun 07 07:28:10 PM PDT 24
Finished	Jun 07 07:28:14 PM PDT 24
Peak memory	202132 kb
Host	smart-c10c8427-33f7-4295-a980-3bcfad7a5573
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125199786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1125199786
Directory	/workspace/0.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.776087790
Short name	T935
Test name
Test status
Simulation time	123633322 ps
CPU time	1.06 seconds
Started	Jun 07 07:28:07 PM PDT 24
Finished	Jun 07 07:28:12 PM PDT 24
Peak memory	210460 kb
Host	smart-f33c4158-cdfe-422f-bb65-ae570246ee52
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776087790 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.776087790
Directory	/workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3725734307
Short name	T1004
Test name
Test status
Simulation time	25601100 ps
CPU time	0.61 seconds
Started	Jun 07 07:28:09 PM PDT 24
Finished	Jun 07 07:28:12 PM PDT 24
Peak memory	202220 kb
Host	smart-b9f48f8a-19f1-4172-a949-d722f6bd1849
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725734307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.3725734307
Directory	/workspace/0.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3546773871
Short name	T92
Test name
Test status
Simulation time	4245848217 ps
CPU time	4.45 seconds
Started	Jun 07 07:28:01 PM PDT 24
Finished	Jun 07 07:28:10 PM PDT 24
Peak memory	202588 kb
Host	smart-ca6d3f63-e6fb-407f-8446-41872e833dcf
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546773871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.3546773871
Directory	/workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2815450619
Short name	T943
Test name
Test status
Simulation time	30081005 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:10 PM PDT 24
Finished	Jun 07 07:28:14 PM PDT 24
Peak memory	202252 kb
Host	smart-96a71ded-0dc6-4f8b-8596-f1bcaeda24f8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815450619 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.2815450619
Directory	/workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.499177103
Short name	T949
Test name
Test status
Simulation time	56137677 ps
CPU time	2.71 seconds
Started	Jun 07 07:28:11 PM PDT 24
Finished	Jun 07 07:28:17 PM PDT 24
Peak memory	210580 kb
Host	smart-5922e4ac-0a3f-4535-ac4d-a2a8e8430e21
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499177103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.499177103
Directory	/workspace/0.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2168188333
Short name	T50
Test name
Test status
Simulation time	377056118 ps
CPU time	2.29 seconds
Started	Jun 07 07:28:08 PM PDT 24
Finished	Jun 07 07:28:13 PM PDT 24
Peak memory	210672 kb
Host	smart-4289724b-f361-466b-8cec-9fd625e431f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168188333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.2168188333
Directory	/workspace/0.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2009741146
Short name	T73
Test name
Test status
Simulation time	20674738 ps
CPU time	0.66 seconds
Started	Jun 07 07:28:19 PM PDT 24
Finished	Jun 07 07:28:26 PM PDT 24
Peak memory	201608 kb
Host	smart-3bf0669e-270e-4001-90b3-8473eb713c87
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009741146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.2009741146
Directory	/workspace/1.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2254626230
Short name	T961
Test name
Test status
Simulation time	544432942 ps
CPU time	2.07 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:25 PM PDT 24
Peak memory	202280 kb
Host	smart-05b57024-d111-4686-a49d-fb76b158501e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254626230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2254626230
Directory	/workspace/1.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2084677363
Short name	T55
Test name
Test status
Simulation time	17978933 ps
CPU time	0.69 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	202120 kb
Host	smart-d097ece6-3d83-4f3a-878d-258f754b1b22
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084677363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2084677363
Directory	/workspace/1.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2860213198
Short name	T1014
Test name
Test status
Simulation time	38663444 ps
CPU time	1.28 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	211356 kb
Host	smart-7cc6d36b-ad7f-4041-8664-3ac8e7e194be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860213198 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2860213198
Directory	/workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1055930305
Short name	T105
Test name
Test status
Simulation time	30087016 ps
CPU time	0.65 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:20 PM PDT 24
Peak memory	202164 kb
Host	smart-e02cf923-2c94-41ad-891f-85a09bf613cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055930305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.1055930305
Directory	/workspace/1.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3255103447
Short name	T86
Test name
Test status
Simulation time	287667731 ps
CPU time	2.16 seconds
Started	Jun 07 07:28:08 PM PDT 24
Finished	Jun 07 07:28:13 PM PDT 24
Peak memory	202364 kb
Host	smart-2e0fb480-4406-4071-b152-13fd5a8e4284
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255103447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3255103447
Directory	/workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3428915032
Short name	T75
Test name
Test status
Simulation time	52960927 ps
CPU time	0.77 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:19 PM PDT 24
Peak memory	202196 kb
Host	smart-ac7c8bcb-e438-486e-b91f-6d497180b065
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428915032 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3428915032
Directory	/workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4052505272
Short name	T956
Test name
Test status
Simulation time	416900299 ps
CPU time	3.77 seconds
Started	Jun 07 07:28:09 PM PDT 24
Finished	Jun 07 07:28:15 PM PDT 24
Peak memory	202308 kb
Host	smart-5eb89c64-7428-4a2c-a2e2-2b866229bbb2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052505272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.4052505272
Directory	/workspace/1.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.64437552
Short name	T118
Test name
Test status
Simulation time	575028282 ps
CPU time	1.59 seconds
Started	Jun 07 07:28:08 PM PDT 24
Finished	Jun 07 07:28:13 PM PDT 24
Peak memory	210636 kb
Host	smart-c709aa55-8327-4317-b2a8-13b36eb8f72f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64437552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.sram_ctrl_tl_intg_err.64437552
Directory	/workspace/1.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1415551650
Short name	T965
Test name
Test status
Simulation time	84710921 ps
CPU time	1.58 seconds
Started	Jun 07 07:28:35 PM PDT 24
Finished	Jun 07 07:28:40 PM PDT 24
Peak memory	214284 kb
Host	smart-d6e94953-fb40-4caf-94c9-4a2fa92bddb3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415551650 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1415551650
Directory	/workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1606276170
Short name	T87
Test name
Test status
Simulation time	13622942 ps
CPU time	0.68 seconds
Started	Jun 07 07:28:36 PM PDT 24
Finished	Jun 07 07:28:39 PM PDT 24
Peak memory	201616 kb
Host	smart-a101eb57-7004-4a56-bbfd-dc971ff5a2c9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606276170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1606276170
Directory	/workspace/10.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2850718640
Short name	T1010
Test name
Test status
Simulation time	689028143 ps
CPU time	4.1 seconds
Started	Jun 07 07:28:38 PM PDT 24
Finished	Jun 07 07:28:45 PM PDT 24
Peak memory	202492 kb
Host	smart-09c8b7bf-c1b3-499b-ba60-c51522db928b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850718640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2850718640
Directory	/workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4183315159
Short name	T973
Test name
Test status
Simulation time	75307513 ps
CPU time	0.76 seconds
Started	Jun 07 07:28:36 PM PDT 24
Finished	Jun 07 07:28:40 PM PDT 24
Peak memory	202224 kb
Host	smart-dccacdea-54d0-4781-b23c-e88286da34b5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183315159 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.4183315159
Directory	/workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3646672838
Short name	T957
Test name
Test status
Simulation time	236969339 ps
CPU time	4.41 seconds
Started	Jun 07 07:28:36 PM PDT 24
Finished	Jun 07 07:28:43 PM PDT 24
Peak memory	211524 kb
Host	smart-8a41fc41-dd2e-4d55-8ac8-db47d63920c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646672838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3646672838
Directory	/workspace/10.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3831030155
Short name	T989
Test name
Test status
Simulation time	76954488 ps
CPU time	1.29 seconds
Started	Jun 07 07:28:42 PM PDT 24
Finished	Jun 07 07:28:46 PM PDT 24
Peak memory	210476 kb
Host	smart-b5f0644f-2fce-4290-b2ba-5de35cd0f638
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831030155 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3831030155
Directory	/workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1645482345
Short name	T987
Test name
Test status
Simulation time	20007498 ps
CPU time	0.64 seconds
Started	Jun 07 07:28:41 PM PDT 24
Finished	Jun 07 07:28:44 PM PDT 24
Peak memory	201660 kb
Host	smart-a04a719d-68b8-4038-b17b-45e9e7fd04a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645482345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.1645482345
Directory	/workspace/11.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.426525658
Short name	T91
Test name
Test status
Simulation time	1740050204 ps
CPU time	3.44 seconds
Started	Jun 07 07:28:36 PM PDT 24
Finished	Jun 07 07:28:42 PM PDT 24
Peak memory	202476 kb
Host	smart-152f67be-f77a-4b50-8f24-7e4c95098b8e
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426525658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.426525658
Directory	/workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2108276392
Short name	T958
Test name
Test status
Simulation time	50390576 ps
CPU time	0.68 seconds
Started	Jun 07 07:28:41 PM PDT 24
Finished	Jun 07 07:28:44 PM PDT 24
Peak memory	202232 kb
Host	smart-f98310c6-b2b6-4834-bfd8-bd42e3b6c766
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108276392 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2108276392
Directory	/workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2845000542
Short name	T947
Test name
Test status
Simulation time	145341225 ps
CPU time	2.59 seconds
Started	Jun 07 07:28:39 PM PDT 24
Finished	Jun 07 07:28:44 PM PDT 24
Peak memory	202336 kb
Host	smart-de671c09-5221-471f-b3ee-61c825802c80
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845000542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.2845000542
Directory	/workspace/11.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1009312988
Short name	T1008
Test name
Test status
Simulation time	120020880 ps
CPU time	1.12 seconds
Started	Jun 07 07:28:39 PM PDT 24
Finished	Jun 07 07:28:42 PM PDT 24
Peak memory	210468 kb
Host	smart-894fb9c3-0807-48cd-9a2c-df0ee8cf9ee0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009312988 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1009312988
Directory	/workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2751070005
Short name	T54
Test name
Test status
Simulation time	42748318 ps
CPU time	0.65 seconds
Started	Jun 07 07:28:41 PM PDT 24
Finished	Jun 07 07:28:43 PM PDT 24
Peak memory	202260 kb
Host	smart-5844a2fe-4c05-4b8b-9612-b3575ae4125a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751070005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.2751070005
Directory	/workspace/12.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1915129535
Short name	T969
Test name
Test status
Simulation time	425855902 ps
CPU time	1.98 seconds
Started	Jun 07 07:28:39 PM PDT 24
Finished	Jun 07 07:28:44 PM PDT 24
Peak memory	202368 kb
Host	smart-c740caac-befd-417d-a189-e81b073eda47
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915129535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1915129535
Directory	/workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2428845188
Short name	T955
Test name
Test status
Simulation time	32458784 ps
CPU time	0.75 seconds
Started	Jun 07 07:28:41 PM PDT 24
Finished	Jun 07 07:28:45 PM PDT 24
Peak memory	202212 kb
Host	smart-abfd6219-557d-4979-95b7-f3de65ab5eb6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428845188 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2428845188
Directory	/workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.490488015
Short name	T948
Test name
Test status
Simulation time	167807020 ps
CPU time	2.34 seconds
Started	Jun 07 07:28:41 PM PDT 24
Finished	Jun 07 07:28:47 PM PDT 24
Peak memory	202376 kb
Host	smart-6c946871-cb96-4aaa-be10-e292e32d994f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490488015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.490488015
Directory	/workspace/12.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1468404949
Short name	T999
Test name
Test status
Simulation time	100650389 ps
CPU time	0.96 seconds
Started	Jun 07 07:28:50 PM PDT 24
Finished	Jun 07 07:28:55 PM PDT 24
Peak memory	210444 kb
Host	smart-418cd03c-9819-4265-b1d9-138f32f855bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468404949 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1468404949
Directory	/workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4229928169
Short name	T1011
Test name
Test status
Simulation time	26054705 ps
CPU time	0.67 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:52 PM PDT 24
Peak memory	201620 kb
Host	smart-19c1d86f-9176-4050-bfb4-ec099f322761
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229928169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.4229928169
Directory	/workspace/13.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4045923048
Short name	T67
Test name
Test status
Simulation time	1974514568 ps
CPU time	3.36 seconds
Started	Jun 07 07:28:39 PM PDT 24
Finished	Jun 07 07:28:45 PM PDT 24
Peak memory	202496 kb
Host	smart-eb430413-5c44-4c1f-891e-74119c692643
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045923048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.4045923048
Directory	/workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.634054588
Short name	T979
Test name
Test status
Simulation time	45286221 ps
CPU time	0.73 seconds
Started	Jun 07 07:28:48 PM PDT 24
Finished	Jun 07 07:28:51 PM PDT 24
Peak memory	202200 kb
Host	smart-6729a9eb-2900-44ba-9382-4cebaef2d343
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634054588 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.634054588
Directory	/workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3764058833
Short name	T1002
Test name
Test status
Simulation time	238765222 ps
CPU time	2.57 seconds
Started	Jun 07 07:28:42 PM PDT 24
Finished	Jun 07 07:28:48 PM PDT 24
Peak memory	211040 kb
Host	smart-d1e5d6dd-7ebb-4ed1-980c-26107696ac81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764058833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3764058833
Directory	/workspace/13.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.195617949
Short name	T52
Test name
Test status
Simulation time	103376731 ps
CPU time	1.61 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:53 PM PDT 24
Peak memory	210620 kb
Host	smart-3c7b4f27-2006-4e0a-9852-b430b9ff385c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195617949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sram_ctrl_tl_intg_err.195617949
Directory	/workspace/13.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3415106728
Short name	T945
Test name
Test status
Simulation time	50354208 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:48 PM PDT 24
Finished	Jun 07 07:28:51 PM PDT 24
Peak memory	202188 kb
Host	smart-664170ac-d6e6-4012-a268-e7a5ce43cf65
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415106728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.3415106728
Directory	/workspace/14.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.569154161
Short name	T71
Test name
Test status
Simulation time	414248061 ps
CPU time	3.32 seconds
Started	Jun 07 07:28:47 PM PDT 24
Finished	Jun 07 07:28:53 PM PDT 24
Peak memory	202496 kb
Host	smart-4740d93f-c050-43e5-91c9-409cc0cd532b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569154161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.569154161
Directory	/workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.915362156
Short name	T94
Test name
Test status
Simulation time	20991910 ps
CPU time	0.72 seconds
Started	Jun 07 07:28:48 PM PDT 24
Finished	Jun 07 07:28:51 PM PDT 24
Peak memory	202244 kb
Host	smart-e13a7d87-80ae-4a9e-a5a2-3b18c1c4cb24
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915362156 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.915362156
Directory	/workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1686151498
Short name	T972
Test name
Test status
Simulation time	131884119 ps
CPU time	4.44 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:56 PM PDT 24
Peak memory	210532 kb
Host	smart-86acaf18-edfd-4eb3-a034-8dacab26919a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686151498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.1686151498
Directory	/workspace/14.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1910561727
Short name	T985
Test name
Test status
Simulation time	246456943 ps
CPU time	1.84 seconds
Started	Jun 07 07:28:48 PM PDT 24
Finished	Jun 07 07:28:53 PM PDT 24
Peak memory	202360 kb
Host	smart-3c7afe77-6cc8-4bf7-9cae-391a96f18f4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910561727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1910561727
Directory	/workspace/14.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.861151184
Short name	T993
Test name
Test status
Simulation time	27929438 ps
CPU time	1.24 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:53 PM PDT 24
Peak memory	210428 kb
Host	smart-afb98504-247c-4807-8e1f-c5585600fab5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861151184 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.861151184
Directory	/workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1977303623
Short name	T76
Test name
Test status
Simulation time	50883598 ps
CPU time	0.68 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:54 PM PDT 24
Peak memory	202148 kb
Host	smart-90e00c67-4313-4ade-9d90-db7a6310e54c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977303623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.1977303623
Directory	/workspace/15.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.615019756
Short name	T1007
Test name
Test status
Simulation time	410955519 ps
CPU time	3.39 seconds
Started	Jun 07 07:28:51 PM PDT 24
Finished	Jun 07 07:28:58 PM PDT 24
Peak memory	202464 kb
Host	smart-67eeb763-2115-4a98-b0d3-14bb55eae363
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615019756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.615019756
Directory	/workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2491498151
Short name	T981
Test name
Test status
Simulation time	42633796 ps
CPU time	0.78 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:54 PM PDT 24
Peak memory	202232 kb
Host	smart-b261e463-a6ce-4cf7-95fe-8e1af944077b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491498151 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2491498151
Directory	/workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3990025100
Short name	T977
Test name
Test status
Simulation time	67283059 ps
CPU time	2.09 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:54 PM PDT 24
Peak memory	202424 kb
Host	smart-2e7c2a1c-5e23-44e6-ab60-bcfce0c1b564
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990025100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.3990025100
Directory	/workspace/15.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1045198082
Short name	T980
Test name
Test status
Simulation time	139198968 ps
CPU time	1.48 seconds
Started	Jun 07 07:28:55 PM PDT 24
Finished	Jun 07 07:29:00 PM PDT 24
Peak memory	210568 kb
Host	smart-f1e4c9c6-4c48-4fb3-a61b-97426aae35a2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045198082 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1045198082
Directory	/workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1239567655
Short name	T963
Test name
Test status
Simulation time	15204299 ps
CPU time	0.68 seconds
Started	Jun 07 07:29:30 PM PDT 24
Finished	Jun 07 07:29:34 PM PDT 24
Peak memory	202252 kb
Host	smart-f1c8805f-347b-4c3e-8f8c-298ef3380297
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239567655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1239567655
Directory	/workspace/16.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1129094788
Short name	T1013
Test name
Test status
Simulation time	207201335 ps
CPU time	2.18 seconds
Started	Jun 07 07:28:51 PM PDT 24
Finished	Jun 07 07:28:57 PM PDT 24
Peak memory	202360 kb
Host	smart-eabdbd21-4598-4628-bc91-ea4376404efb
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129094788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1129094788
Directory	/workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1052242848
Short name	T1005
Test name
Test status
Simulation time	37198342 ps
CPU time	0.86 seconds
Started	Jun 07 07:28:59 PM PDT 24
Finished	Jun 07 07:29:03 PM PDT 24
Peak memory	202260 kb
Host	smart-faa8ff54-bbd3-4a13-acc4-6aff2349cd7a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052242848 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1052242848
Directory	/workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.711336654
Short name	T946
Test name
Test status
Simulation time	29322900 ps
CPU time	2.02 seconds
Started	Jun 07 07:28:49 PM PDT 24
Finished	Jun 07 07:28:54 PM PDT 24
Peak memory	202328 kb
Host	smart-48f22e19-5652-4320-b9b2-cd8e215f215c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711336654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.711336654
Directory	/workspace/16.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3910747369
Short name	T121
Test name
Test status
Simulation time	362330515 ps
CPU time	1.54 seconds
Started	Jun 07 07:28:55 PM PDT 24
Finished	Jun 07 07:29:00 PM PDT 24
Peak memory	210628 kb
Host	smart-7a546950-d9c7-4a5f-a311-9f794538faf6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910747369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.3910747369
Directory	/workspace/16.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.843593971
Short name	T952
Test name
Test status
Simulation time	447451404 ps
CPU time	1.78 seconds
Started	Jun 07 07:28:56 PM PDT 24
Finished	Jun 07 07:29:01 PM PDT 24
Peak memory	211640 kb
Host	smart-2a70c8f7-506f-48b4-86f7-0b59036a57d8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843593971 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.843593971
Directory	/workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3713527128
Short name	T960
Test name
Test status
Simulation time	44988958 ps
CPU time	0.65 seconds
Started	Jun 07 07:28:57 PM PDT 24
Finished	Jun 07 07:29:01 PM PDT 24
Peak memory	201680 kb
Host	smart-7212e63d-b4c6-4057-b375-d994e0f49ea6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713527128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.3713527128
Directory	/workspace/17.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3599401814
Short name	T74
Test name
Test status
Simulation time	452466962 ps
CPU time	3.11 seconds
Started	Jun 07 07:29:03 PM PDT 24
Finished	Jun 07 07:29:11 PM PDT 24
Peak memory	202496 kb
Host	smart-480c9c81-9aaa-4cad-b8e4-f4d3de1a8de4
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599401814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.3599401814
Directory	/workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1362241879
Short name	T975
Test name
Test status
Simulation time	18779721 ps
CPU time	0.73 seconds
Started	Jun 07 07:28:58 PM PDT 24
Finished	Jun 07 07:29:02 PM PDT 24
Peak memory	202212 kb
Host	smart-bda429fd-13bb-40f0-8564-1b5e7492c9d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362241879 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1362241879
Directory	/workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.832055118
Short name	T994
Test name
Test status
Simulation time	242448525 ps
CPU time	4.54 seconds
Started	Jun 07 07:28:57 PM PDT 24
Finished	Jun 07 07:29:05 PM PDT 24
Peak memory	210532 kb
Host	smart-c741fbc1-1313-4439-b049-1011db933236
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832055118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.832055118
Directory	/workspace/17.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1368707636
Short name	T119
Test name
Test status
Simulation time	217254545 ps
CPU time	1.74 seconds
Started	Jun 07 07:28:59 PM PDT 24
Finished	Jun 07 07:29:04 PM PDT 24
Peak memory	210596 kb
Host	smart-d1189f4d-33fa-43f9-930b-a0cd7e9b6828
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368707636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.1368707636
Directory	/workspace/17.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1272915237
Short name	T992
Test name
Test status
Simulation time	39466979 ps
CPU time	1.37 seconds
Started	Jun 07 07:29:01 PM PDT 24
Finished	Jun 07 07:29:05 PM PDT 24
Peak memory	210476 kb
Host	smart-0474f2ce-be56-4e46-9c93-18079b4566ce
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272915237 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1272915237
Directory	/workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.960422118
Short name	T88
Test name
Test status
Simulation time	24403147 ps
CPU time	0.69 seconds
Started	Jun 07 07:28:59 PM PDT 24
Finished	Jun 07 07:29:03 PM PDT 24
Peak memory	202180 kb
Host	smart-137c8d03-aa7c-4b86-9936-3bd8ea013518
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960422118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.960422118
Directory	/workspace/18.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1577844441
Short name	T72
Test name
Test status
Simulation time	29687183 ps
CPU time	0.69 seconds
Started	Jun 07 07:28:56 PM PDT 24
Finished	Jun 07 07:29:01 PM PDT 24
Peak memory	202260 kb
Host	smart-64bf7212-49e2-414b-9e4f-da128e31358a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577844441 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1577844441
Directory	/workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3265788384
Short name	T938
Test name
Test status
Simulation time	57685003 ps
CPU time	2.24 seconds
Started	Jun 07 07:29:02 PM PDT 24
Finished	Jun 07 07:29:08 PM PDT 24
Peak memory	202372 kb
Host	smart-a4bc09ee-3e23-451d-be7e-4c8fb4b1e1c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265788384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3265788384
Directory	/workspace/18.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1231864598
Short name	T968
Test name
Test status
Simulation time	33904886 ps
CPU time	1.76 seconds
Started	Jun 07 07:28:59 PM PDT 24
Finished	Jun 07 07:29:05 PM PDT 24
Peak memory	210568 kb
Host	smart-620d7327-aaa5-4964-abb5-2b7912e39128
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231864598 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.1231864598
Directory	/workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3848529398
Short name	T125
Test name
Test status
Simulation time	41097593 ps
CPU time	0.65 seconds
Started	Jun 07 07:28:57 PM PDT 24
Finished	Jun 07 07:29:01 PM PDT 24
Peak memory	202184 kb
Host	smart-75d3c823-ee3f-4b53-9be7-1d5033a80299
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848529398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.3848529398
Directory	/workspace/19.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2548203289
Short name	T93
Test name
Test status
Simulation time	782229334 ps
CPU time	3.42 seconds
Started	Jun 07 07:28:58 PM PDT 24
Finished	Jun 07 07:29:04 PM PDT 24
Peak memory	202448 kb
Host	smart-b2904707-854e-4096-a327-9351ec8a4118
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548203289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2548203289
Directory	/workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2863300163
Short name	T951
Test name
Test status
Simulation time	62815656 ps
CPU time	0.72 seconds
Started	Jun 07 07:29:00 PM PDT 24
Finished	Jun 07 07:29:04 PM PDT 24
Peak memory	202004 kb
Host	smart-4edf13d5-e8eb-4146-aae0-e78af5c2081e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863300163 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2863300163
Directory	/workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1117391540
Short name	T934
Test name
Test status
Simulation time	299287528 ps
CPU time	2.59 seconds
Started	Jun 07 07:28:57 PM PDT 24
Finished	Jun 07 07:29:03 PM PDT 24
Peak memory	210556 kb
Host	smart-207b0192-6fe3-4218-962a-0fbfd2c14d0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117391540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1117391540
Directory	/workspace/19.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2775071490
Short name	T982
Test name
Test status
Simulation time	43030485 ps
CPU time	0.74 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	202260 kb
Host	smart-cf4cdeb0-2c5a-46dc-9963-e18d1bad541b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775071490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2775071490
Directory	/workspace/2.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3402692003
Short name	T991
Test name
Test status
Simulation time	477908422 ps
CPU time	2.19 seconds
Started	Jun 07 07:28:19 PM PDT 24
Finished	Jun 07 07:28:26 PM PDT 24
Peak memory	202300 kb
Host	smart-60f28fad-3ea6-4e37-9ad7-dfe5bbe3c54e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402692003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3402692003
Directory	/workspace/2.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3038094076
Short name	T944
Test name
Test status
Simulation time	17994676 ps
CPU time	0.68 seconds
Started	Jun 07 07:28:19 PM PDT 24
Finished	Jun 07 07:28:24 PM PDT 24
Peak memory	201740 kb
Host	smart-9b37a1c6-2395-43bc-86f8-ab701b7da130
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038094076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.3038094076
Directory	/workspace/2.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2795967372
Short name	T1015
Test name
Test status
Simulation time	43568960 ps
CPU time	1.59 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:22 PM PDT 24
Peak memory	211612 kb
Host	smart-97a43d54-57d8-48f8-b7c4-bd068fd4f805
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795967372 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2795967372
Directory	/workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2895221268
Short name	T986
Test name
Test status
Simulation time	39887978 ps
CPU time	0.69 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:19 PM PDT 24
Peak memory	202212 kb
Host	smart-15533b98-44bd-4398-92a6-738a816863ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895221268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.2895221268
Directory	/workspace/2.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3901304630
Short name	T80
Test name
Test status
Simulation time	1666467275 ps
CPU time	3.57 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	202572 kb
Host	smart-ec3a33ae-44ae-471f-aaa4-8e17706702f6
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901304630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3901304630
Directory	/workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3499801848
Short name	T997
Test name
Test status
Simulation time	59483727 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:20 PM PDT 24
Peak memory	202264 kb
Host	smart-e1bb9ea0-117c-4ef0-8b9d-c71355c062e6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499801848 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3499801848
Directory	/workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.174045018
Short name	T988
Test name
Test status
Simulation time	41520355 ps
CPU time	1.6 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	202496 kb
Host	smart-5937854d-4532-461d-b94e-43a48ba33139
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174045018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.174045018
Directory	/workspace/2.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.417316098
Short name	T113
Test name
Test status
Simulation time	260268297 ps
CPU time	2.55 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:20 PM PDT 24
Peak memory	210620 kb
Host	smart-6369847b-997c-4853-90b2-b28e121ad219
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417316098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sram_ctrl_tl_intg_err.417316098
Directory	/workspace/2.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1203537220
Short name	T1009
Test name
Test status
Simulation time	31024658 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:21 PM PDT 24
Peak memory	201428 kb
Host	smart-243b2a19-18af-4ea2-b227-cf75dc87a9f3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203537220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_aliasing.1203537220
Directory	/workspace/3.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3107147308
Short name	T998
Test name
Test status
Simulation time	176629087 ps
CPU time	2.34 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:22 PM PDT 24
Peak memory	202340 kb
Host	smart-a7a3c13e-d9ea-40f4-9aa4-143182c32b03
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107147308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3107147308
Directory	/workspace/3.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1989107057
Short name	T1003
Test name
Test status
Simulation time	214818692 ps
CPU time	0.67 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:19 PM PDT 24
Peak memory	201948 kb
Host	smart-c881656a-eae5-4f51-84d5-a6df500e20aa
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989107057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1989107057
Directory	/workspace/3.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2664170990
Short name	T970
Test name
Test status
Simulation time	54262599 ps
CPU time	1.29 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:25 PM PDT 24
Peak memory	210572 kb
Host	smart-0dc51bf1-c791-441d-b62c-14afcb804c40
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664170990 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2664170990
Directory	/workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1416713747
Short name	T97
Test name
Test status
Simulation time	16315273 ps
CPU time	0.64 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:22 PM PDT 24
Peak memory	201584 kb
Host	smart-2ae985c5-7dc9-4ac6-be88-02c48a21dc40
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416713747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.1416713747
Directory	/workspace/3.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2018446306
Short name	T89
Test name
Test status
Simulation time	1645756041 ps
CPU time	3.28 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:22 PM PDT 24
Peak memory	202540 kb
Host	smart-32b1dd71-629c-4894-99bb-1c21df0d1e6b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018446306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.2018446306
Directory	/workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1584549279
Short name	T95
Test name
Test status
Simulation time	22491410 ps
CPU time	0.67 seconds
Started	Jun 07 07:28:16 PM PDT 24
Finished	Jun 07 07:28:18 PM PDT 24
Peak memory	202268 kb
Host	smart-af9d5bd5-b828-43aa-aab3-a4c2ff27d46a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584549279 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1584549279
Directory	/workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3159455875
Short name	T976
Test name
Test status
Simulation time	68145996 ps
CPU time	2.41 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:25 PM PDT 24
Peak memory	210628 kb
Host	smart-64b056a0-cb96-4530-adf5-e7fb969801c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159455875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.3159455875
Directory	/workspace/3.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4150973001
Short name	T966
Test name
Test status
Simulation time	170174142 ps
CPU time	1.57 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:22 PM PDT 24
Peak memory	210616 kb
Host	smart-0743a345-31a0-45c7-bc33-df6b38c1d9ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150973001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.4150973001
Directory	/workspace/3.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.667085481
Short name	T995
Test name
Test status
Simulation time	25401327 ps
CPU time	0.66 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	201420 kb
Host	smart-1a118136-8e2d-4033-ae80-bd38a70dbaf2
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667085481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_aliasing.667085481
Directory	/workspace/4.sram_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1299549792
Short name	T971
Test name
Test status
Simulation time	268962190 ps
CPU time	2.31 seconds
Started	Jun 07 07:28:24 PM PDT 24
Finished	Jun 07 07:28:31 PM PDT 24
Peak memory	202364 kb
Host	smart-2f57cd9c-55ca-4a68-af89-45e7509d63d8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299549792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.1299549792
Directory	/workspace/4.sram_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1423474661
Short name	T1000
Test name
Test status
Simulation time	55396396 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	202208 kb
Host	smart-d5af3464-56d1-4487-b9c8-ec0de03ca626
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423474661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1423474661
Directory	/workspace/4.sram_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2486474815
Short name	T974
Test name
Test status
Simulation time	96389543 ps
CPU time	1.27 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:30 PM PDT 24
Peak memory	210636 kb
Host	smart-381aff7e-bb3c-492b-beb5-35512b6770d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486474815 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2486474815
Directory	/workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4075928563
Short name	T68
Test name
Test status
Simulation time	12055514 ps
CPU time	0.64 seconds
Started	Jun 07 07:28:27 PM PDT 24
Finished	Jun 07 07:28:31 PM PDT 24
Peak memory	202260 kb
Host	smart-8c33598c-a3c2-4bab-86f9-eca6cef25413
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075928563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.4075928563
Directory	/workspace/4.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1368232363
Short name	T954
Test name
Test status
Simulation time	26000383 ps
CPU time	0.7 seconds
Started	Jun 07 07:28:24 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	202248 kb
Host	smart-e4a45634-82fe-4e66-94ed-a1e5f06fbd49
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368232363 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1368232363
Directory	/workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.154262560
Short name	T1012
Test name
Test status
Simulation time	99676759 ps
CPU time	3.07 seconds
Started	Jun 07 07:28:17 PM PDT 24
Finished	Jun 07 07:28:23 PM PDT 24
Peak memory	202364 kb
Host	smart-b463cce9-510e-4f57-9c9b-374d3f6542ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154262560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.154262560
Directory	/workspace/4.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2685453704
Short name	T124
Test name
Test status
Simulation time	313976511 ps
CPU time	2.35 seconds
Started	Jun 07 07:28:18 PM PDT 24
Finished	Jun 07 07:28:25 PM PDT 24
Peak memory	210568 kb
Host	smart-55dd0efa-f6c8-47bf-a1b4-10bb17b73ae0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685453704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.2685453704
Directory	/workspace/4.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.924505624
Short name	T967
Test name
Test status
Simulation time	11439129 ps
CPU time	0.64 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	202172 kb
Host	smart-e193ae49-4f75-4cfc-8be0-abd3100c1478
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924505624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.924505624
Directory	/workspace/5.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3148500298
Short name	T81
Test name
Test status
Simulation time	407126423 ps
CPU time	1.92 seconds
Started	Jun 07 07:28:26 PM PDT 24
Finished	Jun 07 07:28:32 PM PDT 24
Peak memory	202348 kb
Host	smart-831f2a7b-f4ed-47ae-9d8f-7c5fec4a0744
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148500298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.3148500298
Directory	/workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3121774361
Short name	T942
Test name
Test status
Simulation time	23803945 ps
CPU time	0.8 seconds
Started	Jun 07 07:28:26 PM PDT 24
Finished	Jun 07 07:28:31 PM PDT 24
Peak memory	202208 kb
Host	smart-69ef2f38-762c-4707-ba10-44f446b5f7be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121774361 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3121774361
Directory	/workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4129052951
Short name	T990
Test name
Test status
Simulation time	252691092 ps
CPU time	2.33 seconds
Started	Jun 07 07:28:24 PM PDT 24
Finished	Jun 07 07:28:31 PM PDT 24
Peak memory	210588 kb
Host	smart-3af33f3b-0374-48ed-b54f-1c8abe75c0fe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129052951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.4129052951
Directory	/workspace/5.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2717212916
Short name	T114
Test name
Test status
Simulation time	683848890 ps
CPU time	2.45 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:32 PM PDT 24
Peak memory	210576 kb
Host	smart-51705ae2-fab8-4928-8557-2cf7542d45c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717212916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.2717212916
Directory	/workspace/5.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1545007398
Short name	T98
Test name
Test status
Simulation time	36613850 ps
CPU time	0.66 seconds
Started	Jun 07 07:28:24 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	202248 kb
Host	smart-eb6774b9-c29a-4ff1-ad01-e7bf19acdef1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545007398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.1545007398
Directory	/workspace/6.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.136796681
Short name	T90
Test name
Test status
Simulation time	2366886912 ps
CPU time	3.27 seconds
Started	Jun 07 07:28:28 PM PDT 24
Finished	Jun 07 07:28:34 PM PDT 24
Peak memory	202512 kb
Host	smart-bf4bc8d6-7ead-4b9c-873a-755cf688456c
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136796681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.136796681
Directory	/workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.513647094
Short name	T70
Test name
Test status
Simulation time	49950932 ps
CPU time	0.76 seconds
Started	Jun 07 07:28:24 PM PDT 24
Finished	Jun 07 07:28:29 PM PDT 24
Peak memory	202236 kb
Host	smart-96188ea9-45eb-4de6-83c6-cef3c17fdce0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513647094 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.513647094
Directory	/workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1624500176
Short name	T937
Test name
Test status
Simulation time	38651069 ps
CPU time	4.12 seconds
Started	Jun 07 07:28:25 PM PDT 24
Finished	Jun 07 07:28:33 PM PDT 24
Peak memory	210576 kb
Host	smart-450e43f8-a834-484a-826b-d659cdb0e62c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624500176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.1624500176
Directory	/workspace/6.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1846404961
Short name	T122
Test name
Test status
Simulation time	345432657 ps
CPU time	1.4 seconds
Started	Jun 07 07:28:26 PM PDT 24
Finished	Jun 07 07:28:31 PM PDT 24
Peak memory	202384 kb
Host	smart-b774e074-3a5d-4b17-98e7-6987fa481d74
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846404961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1846404961
Directory	/workspace/6.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1531828101
Short name	T936
Test name
Test status
Simulation time	212554253 ps
CPU time	1.45 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:39 PM PDT 24
Peak memory	210628 kb
Host	smart-85863678-6c99-4ce3-8694-6922a6910c9f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531828101 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1531828101
Directory	/workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.294444892
Short name	T104
Test name
Test status
Simulation time	42774858 ps
CPU time	0.69 seconds
Started	Jun 07 07:28:32 PM PDT 24
Finished	Jun 07 07:28:35 PM PDT 24
Peak memory	202204 kb
Host	smart-baa904fc-9d29-4edb-a428-602a69402b54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294444892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.294444892
Directory	/workspace/7.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3351185717
Short name	T77
Test name
Test status
Simulation time	223179595 ps
CPU time	1.91 seconds
Started	Jun 07 07:28:33 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	202368 kb
Host	smart-21d0547f-45c6-400b-beed-f4d1e923c54b
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351185717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3351185717
Directory	/workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3690340609
Short name	T964
Test name
Test status
Simulation time	71782282 ps
CPU time	0.74 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:37 PM PDT 24
Peak memory	202228 kb
Host	smart-fadf04d9-f49e-4aef-807b-e8d16ef2d496
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690340609 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3690340609
Directory	/workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2304236609
Short name	T983
Test name
Test status
Simulation time	370401196 ps
CPU time	2.62 seconds
Started	Jun 07 07:28:33 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	210552 kb
Host	smart-6ce53da3-51da-47ce-a1dd-a2300c1e9a5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304236609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.2304236609
Directory	/workspace/7.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3966208352
Short name	T117
Test name
Test status
Simulation time	420231165 ps
CPU time	1.45 seconds
Started	Jun 07 07:28:33 PM PDT 24
Finished	Jun 07 07:28:37 PM PDT 24
Peak memory	202356 kb
Host	smart-13f1024a-81d2-4024-8b78-dd7df56eab2a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966208352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.3966208352
Directory	/workspace/7.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.947337142
Short name	T940
Test name
Test status
Simulation time	35537003 ps
CPU time	1.41 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	211604 kb
Host	smart-eef00658-bea3-4e39-9b24-eca5db9a1b41
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947337142 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.947337142
Directory	/workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1352810974
Short name	T953
Test name
Test status
Simulation time	30216567 ps
CPU time	0.64 seconds
Started	Jun 07 07:28:31 PM PDT 24
Finished	Jun 07 07:28:34 PM PDT 24
Peak memory	202188 kb
Host	smart-c3195ee4-5749-4bfb-8f32-03707f39ef16
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352810974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.1352810974
Directory	/workspace/8.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2051917972
Short name	T79
Test name
Test status
Simulation time	839053811 ps
CPU time	2.02 seconds
Started	Jun 07 07:28:32 PM PDT 24
Finished	Jun 07 07:28:37 PM PDT 24
Peak memory	202240 kb
Host	smart-aae17ca9-09e4-497e-b911-41783f6a8c21
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051917972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.2051917972
Directory	/workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.836018195
Short name	T96
Test name
Test status
Simulation time	29487758 ps
CPU time	0.72 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	202220 kb
Host	smart-8b99daaa-1b80-4f3c-be20-e9ab14987704
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836018195 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.836018195
Directory	/workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2360185146
Short name	T941
Test name
Test status
Simulation time	130979779 ps
CPU time	4.14 seconds
Started	Jun 07 07:28:33 PM PDT 24
Finished	Jun 07 07:28:40 PM PDT 24
Peak memory	202372 kb
Host	smart-46e61ed4-653f-4ec4-bf29-395d149015e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360185146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2360185146
Directory	/workspace/8.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1943041177
Short name	T1001
Test name
Test status
Simulation time	144937290 ps
CPU time	2.03 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:39 PM PDT 24
Peak memory	210508 kb
Host	smart-776309c9-9928-4ef0-8bdb-661725f58aab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943041177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.1943041177
Directory	/workspace/8.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.396399712
Short name	T962
Test name
Test status
Simulation time	154234038 ps
CPU time	1.47 seconds
Started	Jun 07 07:28:38 PM PDT 24
Finished	Jun 07 07:28:42 PM PDT 24
Peak memory	210540 kb
Host	smart-76f842b7-16a5-40c2-b7cd-aeff6a44f4eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396399712 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.396399712
Directory	/workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.908617085
Short name	T950
Test name
Test status
Simulation time	37139563 ps
CPU time	0.67 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	202216 kb
Host	smart-f7350122-a55c-4665-a893-9582691be829
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908617085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 9.sram_ctrl_csr_rw.908617085
Directory	/workspace/9.sram_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3085269934
Short name	T78
Test name
Test status
Simulation time	428146886 ps
CPU time	3.32 seconds
Started	Jun 07 07:28:35 PM PDT 24
Finished	Jun 07 07:28:41 PM PDT 24
Peak memory	202492 kb
Host	smart-39f1986f-4554-4b1a-b5d9-e6bc0c7fa055
User	root
Command	/workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085269934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.3085269934
Directory	/workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2610998361
Short name	T959
Test name
Test status
Simulation time	28301664 ps
CPU time	0.71 seconds
Started	Jun 07 07:28:38 PM PDT 24
Finished	Jun 07 07:28:41 PM PDT 24
Peak memory	202260 kb
Host	smart-0f9f6813-ddbc-4816-b30c-7f211db551e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610998361 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2610998361
Directory	/workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3562125239
Short name	T996
Test name
Test status
Simulation time	91548084 ps
CPU time	2.35 seconds
Started	Jun 07 07:28:33 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	202472 kb
Host	smart-b10ccc33-a66f-4922-82f8-eea51f964978
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562125239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3562125239
Directory	/workspace/9.sram_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1616301128
Short name	T116
Test name
Test status
Simulation time	96475036 ps
CPU time	1.53 seconds
Started	Jun 07 07:28:34 PM PDT 24
Finished	Jun 07 07:28:38 PM PDT 24
Peak memory	210576 kb
Host	smart-d6bd87c8-4618-41e2-af08-3ec75d10f4af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616301128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.1616301128
Directory	/workspace/9.sram_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.sram_ctrl_access_during_key_req.3067006490
Short name	T291
Test name
Test status
Simulation time	14255258434 ps
CPU time	611.08 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:43:47 PM PDT 24
Peak memory	353088 kb
Host	smart-8db93f58-e70c-479a-9824-faaf9cb1f3a2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067006490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3067006490
Directory	/workspace/0.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/0.sram_ctrl_alert_test.1651850069
Short name	T197
Test name
Test status
Simulation time	93102003 ps
CPU time	0.61 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:33:39 PM PDT 24
Peak memory	202564 kb
Host	smart-9ecaabba-1eb2-4828-8eb1-5bc079c1598b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651850069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1651850069
Directory	/workspace/0.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.sram_ctrl_bijection.1804105681
Short name	T782
Test name
Test status
Simulation time	1182791786 ps
CPU time	43.71 seconds
Started	Jun 07 07:33:30 PM PDT 24
Finished	Jun 07 07:34:17 PM PDT 24
Peak memory	202856 kb
Host	smart-f72d1ef2-50fa-4caa-8bcd-7400c25db34f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804105681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 1804105681
Directory	/workspace/0.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/0.sram_ctrl_executable.2507319138
Short name	T142
Test name
Test status
Simulation time	28281161169 ps
CPU time	1253.29 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:54:30 PM PDT 24
Peak memory	368652 kb
Host	smart-89c53245-cbb6-4430-b0b1-ba8e998b0da2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507319138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2507319138
Directory	/workspace/0.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/0.sram_ctrl_lc_escalation.3347908365
Short name	T222
Test name
Test status
Simulation time	1148123462 ps
CPU time	6.36 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:33:41 PM PDT 24
Peak memory	202848 kb
Host	smart-9fda033e-2339-4083-9ad3-dcf6c53ef94e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347908365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3347908365
Directory	/workspace/0.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/0.sram_ctrl_max_throughput.3721239474
Short name	T815
Test name
Test status
Simulation time	679560539 ps
CPU time	8.31 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:33:48 PM PDT 24
Peak memory	243624 kb
Host	smart-d8d08d99-0242-4bec-8d2d-b7d7bc0ee8df
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721239474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.3721239474
Directory	/workspace/0.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2259281334
Short name	T35
Test name
Test status
Simulation time	736016932 ps
CPU time	6 seconds
Started	Jun 07 07:33:29 PM PDT 24
Finished	Jun 07 07:33:38 PM PDT 24
Peak memory	211080 kb
Host	smart-691e7a51-cada-48f5-bc95-90672ac353a5
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259281334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.2259281334
Directory	/workspace/0.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_mem_walk.2194673753
Short name	T251
Test name
Test status
Simulation time	343817915 ps
CPU time	5.69 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:33:42 PM PDT 24
Peak memory	210996 kb
Host	smart-27c97527-7a2d-413e-aeff-741f9f36e25e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194673753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2194673753
Directory	/workspace/0.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/0.sram_ctrl_multiple_keys.1635934911
Short name	T336
Test name
Test status
Simulation time	1414688812 ps
CPU time	446.64 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:41:05 PM PDT 24
Peak memory	361420 kb
Host	smart-472c54af-0e34-4039-809b-0806b049647c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635934911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.1635934911
Directory	/workspace/0.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access.1619548969
Short name	T694
Test name
Test status
Simulation time	264087110 ps
CPU time	40.35 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:34:17 PM PDT 24
Peak memory	304940 kb
Host	smart-5bf966a0-7f71-4012-8fa1-f6a2c1f67c02
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619548969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.1619548969
Directory	/workspace/0.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3185197599
Short name	T904
Test name
Test status
Simulation time	14419573133 ps
CPU time	333.16 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:39:10 PM PDT 24
Peak memory	202936 kb
Host	smart-0605e1a4-0f80-4298-b7e4-dad3c0d0f2d5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185197599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3185197599
Directory	/workspace/0.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/0.sram_ctrl_ram_cfg.354007303
Short name	T832
Test name
Test status
Simulation time	90378476 ps
CPU time	0.77 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:33:38 PM PDT 24
Peak memory	202884 kb
Host	smart-cd9076b2-ef7a-4111-b10d-de4bfc37cbd9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354007303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.354007303
Directory	/workspace/0.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/0.sram_ctrl_regwen.2097591958
Short name	T397
Test name
Test status
Simulation time	1805054552 ps
CPU time	43.64 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:34:23 PM PDT 24
Peak memory	276548 kb
Host	smart-45862340-bc70-49de-b163-c6bff4785d64
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097591958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2097591958
Directory	/workspace/0.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/0.sram_ctrl_smoke.2462693253
Short name	T860
Test name
Test status
Simulation time	370559065 ps
CPU time	13.43 seconds
Started	Jun 07 07:33:30 PM PDT 24
Finished	Jun 07 07:33:47 PM PDT 24
Peak memory	202916 kb
Host	smart-081fd244-10c7-4006-99fe-5d0aa4d020a4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462693253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2462693253
Directory	/workspace/0.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3783113766
Short name	T870
Test name
Test status
Simulation time	3847985930 ps
CPU time	13.47 seconds
Started	Jun 07 07:33:30 PM PDT 24
Finished	Jun 07 07:33:47 PM PDT 24
Peak memory	211232 kb
Host	smart-1838cd7d-339e-40f9-b414-3cec32705afa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3783113766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3783113766
Directory	/workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3052583920
Short name	T664
Test name
Test status
Simulation time	8013280593 ps
CPU time	356.87 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:39:32 PM PDT 24
Peak memory	202964 kb
Host	smart-0b2a7108-8f3f-414d-b98b-e38226e80cfa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052583920 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.3052583920
Directory	/workspace/0.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3017763273
Short name	T545
Test name
Test status
Simulation time	455306038 ps
CPU time	46.11 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:34:23 PM PDT 24
Peak memory	314220 kb
Host	smart-74351a91-09a6-46fc-93a8-d3e582b7eb17
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017763273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.3017763273
Directory	/workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3739671963
Short name	T773
Test name
Test status
Simulation time	5386074981 ps
CPU time	929.83 seconds
Started	Jun 07 07:33:37 PM PDT 24
Finished	Jun 07 07:49:12 PM PDT 24
Peak memory	368588 kb
Host	smart-7c56ab98-bd25-4830-b159-3815702ea7d6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739671963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3739671963
Directory	/workspace/1.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/1.sram_ctrl_alert_test.705084368
Short name	T476
Test name
Test status
Simulation time	17195063 ps
CPU time	0.66 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:48 PM PDT 24
Peak memory	202676 kb
Host	smart-3df347b2-9a7f-4f57-84f3-47b62f2d4c80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705084368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.705084368
Directory	/workspace/1.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.sram_ctrl_bijection.3535304731
Short name	T911
Test name
Test status
Simulation time	16314830845 ps
CPU time	61.76 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:34:50 PM PDT 24
Peak memory	202880 kb
Host	smart-3b61e71d-4c07-4613-97df-c9f85cb1ccbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535304731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 3535304731
Directory	/workspace/1.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/1.sram_ctrl_lc_escalation.271336306
Short name	T56
Test name
Test status
Simulation time	112809859 ps
CPU time	2.07 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:33:39 PM PDT 24
Peak memory	202948 kb
Host	smart-c2d1bfdc-bf51-4aa1-8085-7c569aa1b158
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271336306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca lation.271336306
Directory	/workspace/1.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/1.sram_ctrl_max_throughput.34547499
Short name	T435
Test name
Test status
Simulation time	141747180 ps
CPU time	103.36 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:35:19 PM PDT 24
Peak memory	370320 kb
Host	smart-ce5c8e2f-98f7-405f-a357-abae3c4cc685
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34547499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_max_throughput.34547499
Directory	/workspace/1.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_partial_access.104133872
Short name	T83
Test name
Test status
Simulation time	58101398 ps
CPU time	3 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:33:52 PM PDT 24
Peak memory	211208 kb
Host	smart-1d7934a1-3e09-4e23-a854-1afb17f3cf7b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104133872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. sram_ctrl_mem_partial_access.104133872
Directory	/workspace/1.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_mem_walk.3495478308
Short name	T436
Test name
Test status
Simulation time	3413231775 ps
CPU time	11.28 seconds
Started	Jun 07 07:33:36 PM PDT 24
Finished	Jun 07 07:33:52 PM PDT 24
Peak memory	211124 kb
Host	smart-1a90e0c7-e69b-43ab-95e8-525667011326
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495478308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3495478308
Directory	/workspace/1.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/1.sram_ctrl_multiple_keys.2197609391
Short name	T362
Test name
Test status
Simulation time	18118858204 ps
CPU time	907.59 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:48:43 PM PDT 24
Peak memory	375776 kb
Host	smart-a7c501b7-d309-45db-ae52-8cde1db81467
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197609391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.2197609391
Directory	/workspace/1.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access.1764658431
Short name	T474
Test name
Test status
Simulation time	523040124 ps
CPU time	64.74 seconds
Started	Jun 07 07:33:35 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	312860 kb
Host	smart-a37ac4ad-b60b-4ab4-823e-d69baea6e55d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764658431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.1764658431
Directory	/workspace/1.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.704042551
Short name	T776
Test name
Test status
Simulation time	21078441111 ps
CPU time	302.35 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:38:39 PM PDT 24
Peak memory	203008 kb
Host	smart-480882e9-caa3-4e1b-810a-6360957897d1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704042551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.sram_ctrl_partial_access_b2b.704042551
Directory	/workspace/1.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/1.sram_ctrl_ram_cfg.3820113332
Short name	T339
Test name
Test status
Simulation time	362872003 ps
CPU time	0.78 seconds
Started	Jun 07 07:33:38 PM PDT 24
Finished	Jun 07 07:33:43 PM PDT 24
Peak memory	202932 kb
Host	smart-af7a2acb-f755-493c-b0db-d2307bac27a7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820113332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3820113332
Directory	/workspace/1.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/1.sram_ctrl_regwen.1913086496
Short name	T129
Test name
Test status
Simulation time	61776952889 ps
CPU time	1498.94 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:58:47 PM PDT 24
Peak memory	374636 kb
Host	smart-455d34b9-79b0-454f-8539-ca562f04f0ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913086496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1913086496
Directory	/workspace/1.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/1.sram_ctrl_smoke.4161793211
Short name	T503
Test name
Test status
Simulation time	1560304000 ps
CPU time	15.27 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:34:04 PM PDT 24
Peak memory	202864 kb
Host	smart-0c3fbfb9-1af8-48e0-a0b9-c16bb75f0ea9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161793211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.4161793211
Directory	/workspace/1.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.445443125
Short name	T37
Test name
Test status
Simulation time	5207113242 ps
CPU time	233.86 seconds
Started	Jun 07 07:33:48 PM PDT 24
Finished	Jun 07 07:37:45 PM PDT 24
Peak memory	382912 kb
Host	smart-4ba070bb-fd9e-4c32-986d-fb3b11e90942
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=445443125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.445443125
Directory	/workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.sram_ctrl_stress_pipeline.3651018226
Short name	T205
Test name
Test status
Simulation time	7660741990 ps
CPU time	370.14 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:39:56 PM PDT 24
Peak memory	202928 kb
Host	smart-03327d5e-55a2-44d5-a136-84ff3fbd9f76
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651018226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.3651018226
Directory	/workspace/1.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.396573591
Short name	T750
Test name
Test status
Simulation time	543368765 ps
CPU time	18.52 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:33:58 PM PDT 24
Peak memory	271388 kb
Host	smart-842d87c4-9edf-48e8-9e36-a11362de2f5f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396573591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.396573591
Directory	/workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/10.sram_ctrl_access_during_key_req.74033652
Short name	T675
Test name
Test status
Simulation time	2050514654 ps
CPU time	360.16 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:40:28 PM PDT 24
Peak memory	373456 kb
Host	smart-6edc43fe-98fe-4b02-bbb7-9c4e97a12423
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74033652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.sram_ctrl_access_during_key_req.74033652
Directory	/workspace/10.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/10.sram_ctrl_alert_test.3154748842
Short name	T14
Test name
Test status
Simulation time	12056980 ps
CPU time	0.63 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:34:28 PM PDT 24
Peak memory	202604 kb
Host	smart-647d8ddd-42bd-4783-a17c-0914d4a8df6a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154748842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3154748842
Directory	/workspace/10.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.sram_ctrl_bijection.3288108383
Short name	T412
Test name
Test status
Simulation time	10345987628 ps
CPU time	85.42 seconds
Started	Jun 07 07:34:14 PM PDT 24
Finished	Jun 07 07:35:41 PM PDT 24
Peak memory	203008 kb
Host	smart-f121b000-16ad-4864-a990-7cb94542a4ca
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288108383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .3288108383
Directory	/workspace/10.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/10.sram_ctrl_executable.2981007528
Short name	T267
Test name
Test status
Simulation time	9239471002 ps
CPU time	321.57 seconds
Started	Jun 07 07:34:25 PM PDT 24
Finished	Jun 07 07:39:51 PM PDT 24
Peak memory	374464 kb
Host	smart-ec8df1f4-3200-4771-8236-a828b500c453
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981007528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2981007528
Directory	/workspace/10.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/10.sram_ctrl_lc_escalation.649818099
Short name	T274
Test name
Test status
Simulation time	2994377060 ps
CPU time	8.34 seconds
Started	Jun 07 07:34:33 PM PDT 24
Finished	Jun 07 07:34:46 PM PDT 24
Peak memory	202984 kb
Host	smart-02a629c1-587b-4401-a80d-8ad601d10eaa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649818099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc alation.649818099
Directory	/workspace/10.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/10.sram_ctrl_max_throughput.2205890890
Short name	T498
Test name
Test status
Simulation time	142835720 ps
CPU time	19.63 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:34:47 PM PDT 24
Peak memory	269312 kb
Host	smart-d922aa28-451b-48a0-92f9-646a24eec43d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205890890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.2205890890
Directory	/workspace/10.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_partial_access.4061563557
Short name	T195
Test name
Test status
Simulation time	333777709 ps
CPU time	3 seconds
Started	Jun 07 07:34:33 PM PDT 24
Finished	Jun 07 07:34:41 PM PDT 24
Peak memory	211060 kb
Host	smart-4919787d-7200-4fcf-831b-e17538a6db09
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061563557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.4061563557
Directory	/workspace/10.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_mem_walk.3376413243
Short name	T513
Test name
Test status
Simulation time	686645823 ps
CPU time	6.45 seconds
Started	Jun 07 07:34:26 PM PDT 24
Finished	Jun 07 07:34:36 PM PDT 24
Peak memory	211060 kb
Host	smart-4c5188f4-04a3-41cb-b8c6-bc94368cba21
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376413243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.3376413243
Directory	/workspace/10.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/10.sram_ctrl_multiple_keys.1248219432
Short name	T470
Test name
Test status
Simulation time	16074792964 ps
CPU time	1308.47 seconds
Started	Jun 07 07:34:14 PM PDT 24
Finished	Jun 07 07:56:05 PM PDT 24
Peak memory	373232 kb
Host	smart-30670798-3c13-4565-8b80-b2bcd8a692b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248219432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.1248219432
Directory	/workspace/10.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access.3811245218
Short name	T179
Test name
Test status
Simulation time	2537818583 ps
CPU time	137.28 seconds
Started	Jun 07 07:34:16 PM PDT 24
Finished	Jun 07 07:36:35 PM PDT 24
Peak memory	367092 kb
Host	smart-b38b4a32-0154-48b6-a602-46ec1cc93447
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811245218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.3811245218
Directory	/workspace/10.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2747089079
Short name	T509
Test name
Test status
Simulation time	10921353737 ps
CPU time	219.62 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:38:07 PM PDT 24
Peak memory	203004 kb
Host	smart-331ff6c3-72ea-4d9c-8a8f-f1bcd2360735
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747089079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.2747089079
Directory	/workspace/10.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/10.sram_ctrl_ram_cfg.295032753
Short name	T178
Test name
Test status
Simulation time	55907708 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:34:29 PM PDT 24
Peak memory	202912 kb
Host	smart-612a8596-173a-4904-b710-e79e959cdd60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295032753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.295032753
Directory	/workspace/10.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/10.sram_ctrl_regwen.1657440472
Short name	T548
Test name
Test status
Simulation time	1785052142 ps
CPU time	573.14 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:44:01 PM PDT 24
Peak memory	374116 kb
Host	smart-be2bf029-7ca5-431a-aa1e-9f11671b467f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657440472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1657440472
Directory	/workspace/10.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/10.sram_ctrl_smoke.4072396563
Short name	T203
Test name
Test status
Simulation time	657775939 ps
CPU time	10.45 seconds
Started	Jun 07 07:34:18 PM PDT 24
Finished	Jun 07 07:34:31 PM PDT 24
Peak memory	202932 kb
Host	smart-3ad7313e-cb15-45a1-8889-20daebace1e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072396563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.4072396563
Directory	/workspace/10.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all.3981494122
Short name	T783
Test name
Test status
Simulation time	6265757676 ps
CPU time	335.9 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:40:04 PM PDT 24
Peak memory	363260 kb
Host	smart-cb1fd091-675f-48b6-856f-7a34603eab51
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981494122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.3981494122
Directory	/workspace/10.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1482405849
Short name	T318
Test name
Test status
Simulation time	708829457 ps
CPU time	55.28 seconds
Started	Jun 07 07:34:35 PM PDT 24
Finished	Jun 07 07:35:34 PM PDT 24
Peak memory	325320 kb
Host	smart-e06702dd-db7d-46da-8780-1011f2ee04b8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1482405849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1482405849
Directory	/workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2303767991
Short name	T540
Test name
Test status
Simulation time	13636532663 ps
CPU time	339.22 seconds
Started	Jun 07 07:34:16 PM PDT 24
Finished	Jun 07 07:39:58 PM PDT 24
Peak memory	202972 kb
Host	smart-dd805adf-bba5-4e34-8966-acf1c8af0028
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303767991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2303767991
Directory	/workspace/10.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4166798354
Short name	T840
Test name
Test status
Simulation time	167050030 ps
CPU time	147.74 seconds
Started	Jun 07 07:34:22 PM PDT 24
Finished	Jun 07 07:36:54 PM PDT 24
Peak memory	370276 kb
Host	smart-9ebc96c3-0b6c-41e3-9f89-c4a126213feb
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166798354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.4166798354
Directory	/workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/11.sram_ctrl_access_during_key_req.3792527204
Short name	T82
Test name
Test status
Simulation time	8126084336 ps
CPU time	1295.31 seconds
Started	Jun 07 07:34:34 PM PDT 24
Finished	Jun 07 07:56:14 PM PDT 24
Peak memory	374724 kb
Host	smart-1bba3f48-c235-4cab-8cf7-11ce728144bb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792527204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3792527204
Directory	/workspace/11.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/11.sram_ctrl_alert_test.702403361
Short name	T685
Test name
Test status
Simulation time	22903145 ps
CPU time	0.67 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:34:28 PM PDT 24
Peak memory	202160 kb
Host	smart-332d5731-e3c9-41ef-87ad-fc3d937f6633
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702403361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.702403361
Directory	/workspace/11.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.sram_ctrl_bijection.3592218919
Short name	T156
Test name
Test status
Simulation time	1537867513 ps
CPU time	64.55 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:35:32 PM PDT 24
Peak memory	202860 kb
Host	smart-cdd7fee2-b27c-4e82-9890-ceae7500ffba
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592218919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3592218919
Directory	/workspace/11.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/11.sram_ctrl_executable.985991115
Short name	T228
Test name
Test status
Simulation time	2470362060 ps
CPU time	79.7 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:35:48 PM PDT 24
Peak memory	317888 kb
Host	smart-fbb00935-b8e1-4aa2-9143-a64f47c32b9e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985991115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executabl e.985991115
Directory	/workspace/11.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/11.sram_ctrl_lc_escalation.3985379620
Short name	T198
Test name
Test status
Simulation time	105032926 ps
CPU time	1.69 seconds
Started	Jun 07 07:34:26 PM PDT 24
Finished	Jun 07 07:34:31 PM PDT 24
Peak memory	202964 kb
Host	smart-4ba05fa3-efef-4876-9d52-2ebeca569779
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985379620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.3985379620
Directory	/workspace/11.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/11.sram_ctrl_max_throughput.3410416952
Short name	T560
Test name
Test status
Simulation time	716880156 ps
CPU time	3.87 seconds
Started	Jun 07 07:34:25 PM PDT 24
Finished	Jun 07 07:34:33 PM PDT 24
Peak memory	221048 kb
Host	smart-fd908208-3d78-4171-9364-dbfe87485158
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410416952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.3410416952
Directory	/workspace/11.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_partial_access.201785770
Short name	T510
Test name
Test status
Simulation time	88325130 ps
CPU time	2.96 seconds
Started	Jun 07 07:34:22 PM PDT 24
Finished	Jun 07 07:34:29 PM PDT 24
Peak memory	211024 kb
Host	smart-530b9a37-8e88-487b-a4ff-18b8bfcc28f7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201785770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sram_ctrl_mem_partial_access.201785770
Directory	/workspace/11.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_mem_walk.2336551522
Short name	T302
Test name
Test status
Simulation time	2616365566 ps
CPU time	11.44 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:34:40 PM PDT 24
Peak memory	211120 kb
Host	smart-3dbe0ab3-16ed-4b72-98af-d33919cdce56
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336551522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.2336551522
Directory	/workspace/11.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/11.sram_ctrl_multiple_keys.3896242402
Short name	T237
Test name
Test status
Simulation time	51905505219 ps
CPU time	1132.08 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:53:20 PM PDT 24
Peak memory	375160 kb
Host	smart-d170b050-6e68-4cd3-8fd3-b1c5d4716924
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896242402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.3896242402
Directory	/workspace/11.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/11.sram_ctrl_partial_access.26207618
Short name	T788
Test name
Test status
Simulation time	758987834 ps
CPU time	111.54 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:36:19 PM PDT 24
Peak memory	368120 kb
Host	smart-2ed75299-8475-4faf-b781-8cb6cd5a91a8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26207618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sr am_ctrl_partial_access.26207618
Directory	/workspace/11.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/11.sram_ctrl_ram_cfg.1292319270
Short name	T565
Test name
Test status
Simulation time	28923176 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:34:29 PM PDT 24
Peak memory	202928 kb
Host	smart-93789381-41d1-48af-aca9-0acb4f59037f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292319270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1292319270
Directory	/workspace/11.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/11.sram_ctrl_smoke.109666505
Short name	T769
Test name
Test status
Simulation time	548989977 ps
CPU time	77.4 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:35:46 PM PDT 24
Peak memory	344032 kb
Host	smart-5852e423-b5b1-41fb-99ea-a5b801cbdb9f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109666505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.109666505
Directory	/workspace/11.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_all.205826567
Short name	T856
Test name
Test status
Simulation time	100653065951 ps
CPU time	721.91 seconds
Started	Jun 07 07:34:24 PM PDT 24
Finished	Jun 07 07:46:31 PM PDT 24
Peak memory	375492 kb
Host	smart-3714f385-915f-4202-b944-bfa253449fff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205826567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_stress_all.205826567
Directory	/workspace/11.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1804820567
Short name	T328
Test name
Test status
Simulation time	5570084249 ps
CPU time	259.58 seconds
Started	Jun 07 07:34:22 PM PDT 24
Finished	Jun 07 07:38:46 PM PDT 24
Peak memory	202908 kb
Host	smart-b2a546fd-cc8a-47d4-80cd-0ca5544f1441
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804820567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1804820567
Directory	/workspace/11.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.394947904
Short name	T259
Test name
Test status
Simulation time	601641237 ps
CPU time	84.82 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:35:52 PM PDT 24
Peak memory	367420 kb
Host	smart-4f3d937a-d521-4a0c-88b8-9b389657e638
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394947904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.394947904
Directory	/workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/12.sram_ctrl_access_during_key_req.157997546
Short name	T30
Test name
Test status
Simulation time	1709426730 ps
CPU time	439.54 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:41:57 PM PDT 24
Peak memory	373460 kb
Host	smart-d80aa7a5-e523-4fb7-80e8-aef4d36a2430
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157997546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sram_ctrl_access_during_key_req.157997546
Directory	/workspace/12.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/12.sram_ctrl_alert_test.4253925581
Short name	T793
Test name
Test status
Simulation time	42524609 ps
CPU time	0.64 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:34:38 PM PDT 24
Peak memory	202636 kb
Host	smart-f3ad8360-99a2-4baa-9d84-0c9afb66ad85
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253925581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.4253925581
Directory	/workspace/12.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.sram_ctrl_bijection.1260004825
Short name	T157
Test name
Test status
Simulation time	1899430365 ps
CPU time	32.99 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:35:09 PM PDT 24
Peak memory	202944 kb
Host	smart-2a1faf89-6530-4a14-bba1-9cf9427d04b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260004825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .1260004825
Directory	/workspace/12.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/12.sram_ctrl_executable.2103701970
Short name	T861
Test name
Test status
Simulation time	30317986324 ps
CPU time	200.38 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:37:58 PM PDT 24
Peak memory	319664 kb
Host	smart-e470990e-2477-4dc5-9cd5-9e989839bdd3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103701970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.2103701970
Directory	/workspace/12.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/12.sram_ctrl_lc_escalation.1460948420
Short name	T255
Test name
Test status
Simulation time	1466424489 ps
CPU time	3.59 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:39 PM PDT 24
Peak memory	202896 kb
Host	smart-781dc9d7-2e11-44b8-adcd-8caf53c2aa30
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460948420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1460948420
Directory	/workspace/12.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/12.sram_ctrl_max_throughput.3297605602
Short name	T639
Test name
Test status
Simulation time	531605313 ps
CPU time	172.46 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:37:28 PM PDT 24
Peak memory	367468 kb
Host	smart-a4fb45a8-2559-4897-bdb5-a8843bc05d1f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297605602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3297605602
Directory	/workspace/12.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3159336971
Short name	T902
Test name
Test status
Simulation time	1119493431 ps
CPU time	5.63 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:34:39 PM PDT 24
Peak memory	210988 kb
Host	smart-cef56ede-743c-4d77-9577-4ea660033df3
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159336971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3159336971
Directory	/workspace/12.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_mem_walk.2137653928
Short name	T394
Test name
Test status
Simulation time	361932275 ps
CPU time	4.44 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:34:37 PM PDT 24
Peak memory	211104 kb
Host	smart-8355a459-a6cd-438e-b818-3fbe4a4592ba
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137653928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.2137653928
Directory	/workspace/12.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/12.sram_ctrl_multiple_keys.3777119994
Short name	T158
Test name
Test status
Simulation time	12170309991 ps
CPU time	698.71 seconds
Started	Jun 07 07:34:23 PM PDT 24
Finished	Jun 07 07:46:07 PM PDT 24
Peak memory	366536 kb
Host	smart-f53646c7-f6ab-42e8-93b2-6301545226b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777119994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.3777119994
Directory	/workspace/12.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access.3515965663
Short name	T613
Test name
Test status
Simulation time	925149949 ps
CPU time	13.4 seconds
Started	Jun 07 07:34:29 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	202984 kb
Host	smart-5e288c05-17de-4c28-9c4b-cff913338c66
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515965663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.3515965663
Directory	/workspace/12.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.522230217
Short name	T725
Test name
Test status
Simulation time	27316288603 ps
CPU time	596.49 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:44:30 PM PDT 24
Peak memory	202940 kb
Host	smart-19a9ff42-bb64-4413-a76c-09397e985d47
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522230217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 12.sram_ctrl_partial_access_b2b.522230217
Directory	/workspace/12.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/12.sram_ctrl_ram_cfg.2155775133
Short name	T167
Test name
Test status
Simulation time	32209261 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:34:37 PM PDT 24
Peak memory	202804 kb
Host	smart-de47e2d2-370b-46d3-8df0-9eefa85ef2bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155775133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2155775133
Directory	/workspace/12.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/12.sram_ctrl_regwen.481255386
Short name	T932
Test name
Test status
Simulation time	30832837968 ps
CPU time	637.38 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:45:13 PM PDT 24
Peak memory	373748 kb
Host	smart-c99e8323-0b89-4866-8816-f8d78fa5859f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481255386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.481255386
Directory	/workspace/12.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/12.sram_ctrl_smoke.2626341220
Short name	T630
Test name
Test status
Simulation time	2376831365 ps
CPU time	15.04 seconds
Started	Jun 07 07:34:22 PM PDT 24
Finished	Jun 07 07:34:42 PM PDT 24
Peak memory	202948 kb
Host	smart-b9c33b29-21f5-4cc0-bc0f-7f4b969080da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626341220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2626341220
Directory	/workspace/12.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all.649601368
Short name	T876
Test name
Test status
Simulation time	64818967167 ps
CPU time	1485.45 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:59:18 PM PDT 24
Peak memory	375864 kb
Host	smart-6811260a-6fe8-4a7b-ab04-8b79fc551420
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649601368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.649601368
Directory	/workspace/12.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.314530468
Short name	T839
Test name
Test status
Simulation time	355350501 ps
CPU time	155.86 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:37:09 PM PDT 24
Peak memory	362048 kb
Host	smart-759be726-92c6-482a-804b-e30137a6ace0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=314530468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.314530468
Directory	/workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1128307009
Short name	T243
Test name
Test status
Simulation time	3210557955 ps
CPU time	254.8 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:38:49 PM PDT 24
Peak memory	202964 kb
Host	smart-3282603f-a61f-45fe-9025-e970fc4cd981
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128307009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.1128307009
Directory	/workspace/12.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1201245857
Short name	T276
Test name
Test status
Simulation time	327052781 ps
CPU time	116.91 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:36:34 PM PDT 24
Peak memory	363452 kb
Host	smart-036bf530-288d-4824-bc12-1a0d2f413379
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201245857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1201245857
Directory	/workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/13.sram_ctrl_access_during_key_req.2364072061
Short name	T329
Test name
Test status
Simulation time	22586580002 ps
CPU time	1586.04 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 08:01:03 PM PDT 24
Peak memory	374204 kb
Host	smart-4e80e707-20d5-436d-8247-bc62dfd473fb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364072061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_access_during_key_req.2364072061
Directory	/workspace/13.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/13.sram_ctrl_alert_test.3944877164
Short name	T775
Test name
Test status
Simulation time	35675293 ps
CPU time	0.61 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:34:33 PM PDT 24
Peak memory	202664 kb
Host	smart-dd400fa6-1918-4093-b2b4-1c208d02f4f6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944877164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3944877164
Directory	/workspace/13.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.sram_ctrl_bijection.3818183512
Short name	T218
Test name
Test status
Simulation time	9101602388 ps
CPU time	51.28 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:35:28 PM PDT 24
Peak memory	203008 kb
Host	smart-79806c85-e6c3-46f2-8def-d3d9b8b45107
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818183512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .3818183512
Directory	/workspace/13.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/13.sram_ctrl_executable.1555899784
Short name	T665
Test name
Test status
Simulation time	4025548282 ps
CPU time	1154.8 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:53:51 PM PDT 24
Peak memory	367840 kb
Host	smart-20e1b25f-def1-460c-ba3c-7ab4f9dc338b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555899784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1555899784
Directory	/workspace/13.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/13.sram_ctrl_lc_escalation.1588998301
Short name	T835
Test name
Test status
Simulation time	833356089 ps
CPU time	7.92 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:43 PM PDT 24
Peak memory	202932 kb
Host	smart-5c3c5c65-8fe4-4b45-9125-6fb97d922d4f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588998301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.1588998301
Directory	/workspace/13.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/13.sram_ctrl_max_throughput.1282611542
Short name	T506
Test name
Test status
Simulation time	39512180 ps
CPU time	1.59 seconds
Started	Jun 07 07:34:36 PM PDT 24
Finished	Jun 07 07:34:42 PM PDT 24
Peak memory	211124 kb
Host	smart-04d1b0c3-7799-42aa-a2b8-42608f2e58ff
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282611542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1282611542
Directory	/workspace/13.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2287551563
Short name	T648
Test name
Test status
Simulation time	66848385 ps
CPU time	4.69 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:40 PM PDT 24
Peak memory	211088 kb
Host	smart-019f58e8-2f62-4730-8956-c54859a07526
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287551563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.2287551563
Directory	/workspace/13.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_mem_walk.622367727
Short name	T288
Test name
Test status
Simulation time	252038737 ps
CPU time	5.2 seconds
Started	Jun 07 07:34:33 PM PDT 24
Finished	Jun 07 07:34:43 PM PDT 24
Peak memory	211036 kb
Host	smart-795d1882-96d1-4be7-9b40-b6d42fcaf275
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622367727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.622367727
Directory	/workspace/13.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/13.sram_ctrl_multiple_keys.1994408843
Short name	T408
Test name
Test status
Simulation time	4808671763 ps
CPU time	1122.93 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:53:18 PM PDT 24
Peak memory	374812 kb
Host	smart-11ef0e52-4573-46be-a79f-d844aaab136f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994408843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1994408843
Directory	/workspace/13.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access.3871605711
Short name	T754
Test name
Test status
Simulation time	383931334 ps
CPU time	2.97 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:34:39 PM PDT 24
Peak memory	210424 kb
Host	smart-d5a24221-11b1-477b-bffd-339dc73040a8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871605711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.3871605711
Directory	/workspace/13.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.839810146
Short name	T680
Test name
Test status
Simulation time	14405052041 ps
CPU time	345.57 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:40:22 PM PDT 24
Peak memory	203016 kb
Host	smart-2568793f-68aa-432b-b9ea-eb2adce83cb2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839810146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.sram_ctrl_partial_access_b2b.839810146
Directory	/workspace/13.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/13.sram_ctrl_ram_cfg.2691674849
Short name	T309
Test name
Test status
Simulation time	29627107 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:34:37 PM PDT 24
Peak memory	202916 kb
Host	smart-eb3c6300-9a0b-4f2f-981c-a4ea9eef31b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691674849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2691674849
Directory	/workspace/13.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/13.sram_ctrl_regwen.3836703727
Short name	T209
Test name
Test status
Simulation time	62042516360 ps
CPU time	1174.75 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:54:09 PM PDT 24
Peak memory	374544 kb
Host	smart-efecfb1a-f9a0-419d-8759-278f4ceea114
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836703727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3836703727
Directory	/workspace/13.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/13.sram_ctrl_smoke.195525055
Short name	T853
Test name
Test status
Simulation time	619320469 ps
CPU time	7.53 seconds
Started	Jun 07 07:34:33 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	202876 kb
Host	smart-f88ec013-0e73-4fb4-9ac3-a506452db35b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195525055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.195525055
Directory	/workspace/13.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all.1655977960
Short name	T837
Test name
Test status
Simulation time	74409803356 ps
CPU time	2949.94 seconds
Started	Jun 07 07:34:28 PM PDT 24
Finished	Jun 07 08:23:41 PM PDT 24
Peak memory	382904 kb
Host	smart-4d891a38-b07c-4226-8aca-920d17ca50ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655977960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.1655977960
Directory	/workspace/13.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1905087275
Short name	T770
Test name
Test status
Simulation time	329131892 ps
CPU time	7.25 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:43 PM PDT 24
Peak memory	212920 kb
Host	smart-192c4a70-4f39-43e0-b194-7ceaf627e063
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1905087275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.1905087275
Directory	/workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1285436702
Short name	T370
Test name
Test status
Simulation time	3815098781 ps
CPU time	179.61 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:37:34 PM PDT 24
Peak memory	202988 kb
Host	smart-43b84285-e81a-4d0f-8f54-2c6feac8f684
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285436702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1285436702
Directory	/workspace/13.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1074655252
Short name	T382
Test name
Test status
Simulation time	166385962 ps
CPU time	19.84 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:55 PM PDT 24
Peak memory	275088 kb
Host	smart-65193c88-338f-4d9a-97fd-07a5e0e6f6a7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074655252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1074655252
Directory	/workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3358934983
Short name	T423
Test name
Test status
Simulation time	2615507195 ps
CPU time	650.09 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:45:27 PM PDT 24
Peak memory	372696 kb
Host	smart-f63014e3-af5b-4052-b76c-c408e94f3987
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358934983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.3358934983
Directory	/workspace/14.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/14.sram_ctrl_alert_test.1995302940
Short name	T418
Test name
Test status
Simulation time	12897062 ps
CPU time	0.64 seconds
Started	Jun 07 07:34:36 PM PDT 24
Finished	Jun 07 07:34:41 PM PDT 24
Peak memory	202632 kb
Host	smart-6ef1642d-589a-4f6f-a9ce-65b7b62f1b9c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995302940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1995302940
Directory	/workspace/14.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.sram_ctrl_bijection.970896187
Short name	T699
Test name
Test status
Simulation time	18375088900 ps
CPU time	67.94 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:35:41 PM PDT 24
Peak memory	203000 kb
Host	smart-2da20591-8fa6-4475-bc4d-361db1f0682e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970896187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection. 970896187
Directory	/workspace/14.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/14.sram_ctrl_executable.1071351375
Short name	T319
Test name
Test status
Simulation time	15841004386 ps
CPU time	943.56 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:50:19 PM PDT 24
Peak memory	375328 kb
Host	smart-2157c055-8960-4ce4-8508-1b56d1ebcfaf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071351375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.1071351375
Directory	/workspace/14.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/14.sram_ctrl_lc_escalation.2763058481
Short name	T701
Test name
Test status
Simulation time	2099375107 ps
CPU time	7.97 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:43 PM PDT 24
Peak memory	211092 kb
Host	smart-7991f735-d23e-4325-80ae-e42af6c0a5cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763058481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.2763058481
Directory	/workspace/14.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/14.sram_ctrl_max_throughput.1259985607
Short name	T663
Test name
Test status
Simulation time	158692087 ps
CPU time	120.39 seconds
Started	Jun 07 07:34:37 PM PDT 24
Finished	Jun 07 07:36:41 PM PDT 24
Peak memory	369540 kb
Host	smart-1b252c6e-e75a-4a00-a181-0e5ada87f952
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259985607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.1259985607
Directory	/workspace/14.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1472050697
Short name	T829
Test name
Test status
Simulation time	119002674 ps
CPU time	3.25 seconds
Started	Jun 07 07:34:29 PM PDT 24
Finished	Jun 07 07:34:35 PM PDT 24
Peak memory	211108 kb
Host	smart-ab8e0a6e-d8b0-4998-80b0-0f7e0c0875ea
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472050697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.1472050697
Directory	/workspace/14.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_mem_walk.2426331244
Short name	T582
Test name
Test status
Simulation time	192277998 ps
CPU time	10.4 seconds
Started	Jun 07 07:34:37 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	211076 kb
Host	smart-74b000c2-141f-4abb-a74a-be264ae61f02
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426331244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.2426331244
Directory	/workspace/14.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/14.sram_ctrl_multiple_keys.3696372304
Short name	T395
Test name
Test status
Simulation time	3597480631 ps
CPU time	327.1 seconds
Started	Jun 07 07:34:33 PM PDT 24
Finished	Jun 07 07:40:05 PM PDT 24
Peak memory	362444 kb
Host	smart-8717729d-8f76-49e9-a9f8-efeba492fc29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696372304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3696372304
Directory	/workspace/14.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access.740664810
Short name	T658
Test name
Test status
Simulation time	190060144 ps
CPU time	107.78 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:36:25 PM PDT 24
Peak memory	354116 kb
Host	smart-d8a7411f-1f12-4348-8473-f74fa3e01680
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740664810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.740664810
Directory	/workspace/14.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3131103239
Short name	T242
Test name
Test status
Simulation time	12255703829 ps
CPU time	216.9 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:38:10 PM PDT 24
Peak memory	202952 kb
Host	smart-49a263e9-622b-4e46-9dd3-df561f208551
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131103239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.3131103239
Directory	/workspace/14.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/14.sram_ctrl_ram_cfg.265505275
Short name	T416
Test name
Test status
Simulation time	33963700 ps
CPU time	0.78 seconds
Started	Jun 07 07:34:34 PM PDT 24
Finished	Jun 07 07:34:39 PM PDT 24
Peak memory	202928 kb
Host	smart-3b759fd2-3ac3-4783-90a9-0c04f6dea904
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265505275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.265505275
Directory	/workspace/14.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/14.sram_ctrl_regwen.775361304
Short name	T644
Test name
Test status
Simulation time	9132721687 ps
CPU time	930.08 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:50:07 PM PDT 24
Peak memory	375112 kb
Host	smart-d3ebc861-7379-404b-be14-cbd1a332eb88
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775361304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.775361304
Directory	/workspace/14.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/14.sram_ctrl_smoke.4269403384
Short name	T919
Test name
Test status
Simulation time	12008917841 ps
CPU time	22.2 seconds
Started	Jun 07 07:34:30 PM PDT 24
Finished	Jun 07 07:34:54 PM PDT 24
Peak memory	202976 kb
Host	smart-6f67709f-fff6-46df-bc5c-a12c268439ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269403384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.4269403384
Directory	/workspace/14.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all.4082389749
Short name	T17
Test name
Test status
Simulation time	33323074962 ps
CPU time	3301.67 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 08:29:36 PM PDT 24
Peak memory	374776 kb
Host	smart-e85f8664-5b76-49be-9a46-144a4e9eb2f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082389749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.4082389749
Directory	/workspace/14.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4232107791
Short name	T110
Test name
Test status
Simulation time	834597215 ps
CPU time	15.5 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	211252 kb
Host	smart-22e51fc9-2956-4350-9f37-8e425aa1a740
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4232107791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.4232107791
Directory	/workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.sram_ctrl_stress_pipeline.1355075759
Short name	T275
Test name
Test status
Simulation time	7449749459 ps
CPU time	177.32 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:37:32 PM PDT 24
Peak memory	202944 kb
Host	smart-5e58b345-aa1e-4776-a5e3-a6e49085a583
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355075759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.1355075759
Directory	/workspace/14.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.148977124
Short name	T739
Test name
Test status
Simulation time	139558849 ps
CPU time	65.15 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:35:41 PM PDT 24
Peak memory	335312 kb
Host	smart-7aecfd04-c090-402c-a795-6bac0929a850
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148977124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_throughput_w_partial_write.148977124
Directory	/workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1315811781
Short name	T786
Test name
Test status
Simulation time	21787783633 ps
CPU time	1617.18 seconds
Started	Jun 07 07:34:42 PM PDT 24
Finished	Jun 07 08:01:44 PM PDT 24
Peak memory	372916 kb
Host	smart-826fcc3c-34c4-4f2f-aa91-a6255f8ce8a3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315811781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.1315811781
Directory	/workspace/15.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/15.sram_ctrl_alert_test.236336790
Short name	T622
Test name
Test status
Simulation time	25947981 ps
CPU time	0.65 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	202600 kb
Host	smart-ef83f8c3-408a-4ee8-bb53-67e139fffd39
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236336790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.236336790
Directory	/workspace/15.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.sram_ctrl_bijection.3073388874
Short name	T811
Test name
Test status
Simulation time	6602006762 ps
CPU time	25.37 seconds
Started	Jun 07 07:34:31 PM PDT 24
Finished	Jun 07 07:35:01 PM PDT 24
Peak memory	202984 kb
Host	smart-da0a8ed8-f0b3-4869-a949-456ce46d5d47
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073388874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .3073388874
Directory	/workspace/15.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/15.sram_ctrl_executable.4099891613
Short name	T480
Test name
Test status
Simulation time	70704003408 ps
CPU time	553.67 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:43:59 PM PDT 24
Peak memory	374440 kb
Host	smart-286edfd2-389f-40b7-9a8f-23ca582cc969
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099891613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.4099891613
Directory	/workspace/15.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/15.sram_ctrl_lc_escalation.2372777389
Short name	T240
Test name
Test status
Simulation time	834853842 ps
CPU time	4.49 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:34:49 PM PDT 24
Peak memory	202900 kb
Host	smart-a51dfa2f-d65f-47df-ba57-f13ca5909bc2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372777389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2372777389
Directory	/workspace/15.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/15.sram_ctrl_max_throughput.2419885880
Short name	T645
Test name
Test status
Simulation time	422997878 ps
CPU time	20.12 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:35:06 PM PDT 24
Peak memory	273488 kb
Host	smart-4aba6c96-6b89-4e9a-913a-d0ba37aa0545
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419885880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_max_throughput.2419885880
Directory	/workspace/15.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2193029082
Short name	T353
Test name
Test status
Simulation time	73390069 ps
CPU time	2.8 seconds
Started	Jun 07 07:34:38 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	211180 kb
Host	smart-25356d12-1d22-47b5-b197-106600178c79
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193029082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.2193029082
Directory	/workspace/15.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_mem_walk.69854060
Short name	T894
Test name
Test status
Simulation time	1645911229 ps
CPU time	6.1 seconds
Started	Jun 07 07:34:42 PM PDT 24
Finished	Jun 07 07:34:52 PM PDT 24
Peak memory	211092 kb
Host	smart-ab68472c-6425-4094-a3ba-6a1280078c3f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69854060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ mem_walk.69854060
Directory	/workspace/15.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/15.sram_ctrl_multiple_keys.103951037
Short name	T207
Test name
Test status
Simulation time	12827831255 ps
CPU time	1272.08 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:55:49 PM PDT 24
Peak memory	369552 kb
Host	smart-d9d356ca-310c-42e1-b427-b7d0e5b35cc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103951037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip le_keys.103951037
Directory	/workspace/15.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/15.sram_ctrl_partial_access.3580264584
Short name	T217
Test name
Test status
Simulation time	821119741 ps
CPU time	16.02 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:35:01 PM PDT 24
Peak memory	202916 kb
Host	smart-1e753beb-23fc-477a-a71a-793a4837d870
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580264584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3580264584
Directory	/workspace/15.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/15.sram_ctrl_ram_cfg.4281429762
Short name	T617
Test name
Test status
Simulation time	85764593 ps
CPU time	0.74 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	202812 kb
Host	smart-72ea3187-2a94-426a-9ae3-946f0a2173dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281429762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4281429762
Directory	/workspace/15.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/15.sram_ctrl_regwen.1563655782
Short name	T707
Test name
Test status
Simulation time	8174455591 ps
CPU time	625.28 seconds
Started	Jun 07 07:34:38 PM PDT 24
Finished	Jun 07 07:45:08 PM PDT 24
Peak memory	374116 kb
Host	smart-ff29f5fb-b7b4-41cc-a2df-5d084c4314de
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563655782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1563655782
Directory	/workspace/15.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/15.sram_ctrl_smoke.3090651124
Short name	T585
Test name
Test status
Simulation time	121544154 ps
CPU time	53.98 seconds
Started	Jun 07 07:34:32 PM PDT 24
Finished	Jun 07 07:35:31 PM PDT 24
Peak memory	322508 kb
Host	smart-13b24200-dcc2-43ef-8757-1408b1a3b4b3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090651124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3090651124
Directory	/workspace/15.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all.2214868679
Short name	T747
Test name
Test status
Simulation time	49198510845 ps
CPU time	3153.3 seconds
Started	Jun 07 07:34:38 PM PDT 24
Finished	Jun 07 08:27:16 PM PDT 24
Peak memory	376904 kb
Host	smart-15353614-cc3f-43f3-93bd-f80d80b82d44
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214868679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.2214868679
Directory	/workspace/15.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.627316776
Short name	T756
Test name
Test status
Simulation time	1128330111 ps
CPU time	25.97 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:35:11 PM PDT 24
Peak memory	211340 kb
Host	smart-8d907e48-611c-4fbf-bbbe-eee2321c98a5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=627316776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.627316776
Directory	/workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3993916293
Short name	T235
Test name
Test status
Simulation time	4358069936 ps
CPU time	181.82 seconds
Started	Jun 07 07:34:34 PM PDT 24
Finished	Jun 07 07:37:40 PM PDT 24
Peak memory	203032 kb
Host	smart-163b8ec7-7d6b-4fb9-a4f7-1f081be0506a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993916293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.3993916293
Directory	/workspace/15.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.424873078
Short name	T287
Test name
Test status
Simulation time	609863368 ps
CPU time	124.91 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:36:50 PM PDT 24
Peak memory	371292 kb
Host	smart-f7182a63-9024-4f5d-afe2-c92c0a11843f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424873078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 15.sram_ctrl_throughput_w_partial_write.424873078
Directory	/workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3787991939
Short name	T482
Test name
Test status
Simulation time	9023792586 ps
CPU time	648.84 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:45:34 PM PDT 24
Peak memory	360452 kb
Host	smart-c57bc813-6be1-44fd-bef9-393b21af023c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787991939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.3787991939
Directory	/workspace/16.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/16.sram_ctrl_alert_test.2112983200
Short name	T265
Test name
Test status
Simulation time	31822521 ps
CPU time	0.66 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:34:47 PM PDT 24
Peak memory	202608 kb
Host	smart-0e3250fc-2ab0-449f-9a89-329e8c465fde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112983200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2112983200
Directory	/workspace/16.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.sram_ctrl_bijection.425370057
Short name	T460
Test name
Test status
Simulation time	4187185613 ps
CPU time	51.28 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:35:35 PM PDT 24
Peak memory	203052 kb
Host	smart-b57d0206-a727-4029-9c39-45e457a810e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425370057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection. 425370057
Directory	/workspace/16.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/16.sram_ctrl_executable.1922245662
Short name	T464
Test name
Test status
Simulation time	45061023333 ps
CPU time	676.59 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:46:02 PM PDT 24
Peak memory	374364 kb
Host	smart-45ad35ed-f8a6-4cde-b1c0-3c23abb3b33b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922245662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.1922245662
Directory	/workspace/16.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/16.sram_ctrl_lc_escalation.3193778111
Short name	T761
Test name
Test status
Simulation time	447337227 ps
CPU time	6.74 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:34:53 PM PDT 24
Peak memory	214992 kb
Host	smart-815538ad-d8ce-4767-8a97-05a85e6a328f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193778111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.3193778111
Directory	/workspace/16.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/16.sram_ctrl_max_throughput.3617686635
Short name	T538
Test name
Test status
Simulation time	199719681 ps
CPU time	5.35 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	235604 kb
Host	smart-07355b3b-3af0-4335-ae76-cb371a86ead1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617686635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.3617686635
Directory	/workspace/16.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_partial_access.4129231754
Short name	T34
Test name
Test status
Simulation time	377863437 ps
CPU time	3.31 seconds
Started	Jun 07 07:34:43 PM PDT 24
Finished	Jun 07 07:34:50 PM PDT 24
Peak memory	211148 kb
Host	smart-37a5c3b2-4f59-42ac-806b-a137699ce2a7
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129231754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.4129231754
Directory	/workspace/16.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_mem_walk.1235070946
Short name	T236
Test name
Test status
Simulation time	551551844 ps
CPU time	8.48 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:34:53 PM PDT 24
Peak memory	211064 kb
Host	smart-480b2c3c-e747-4fa6-a54b-4a6612976e80
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235070946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.1235070946
Directory	/workspace/16.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/16.sram_ctrl_multiple_keys.3305854074
Short name	T137
Test name
Test status
Simulation time	9442303863 ps
CPU time	760.67 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:47:25 PM PDT 24
Peak memory	371168 kb
Host	smart-01899473-7876-4f22-b52d-dbadd2094019
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305854074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.3305854074
Directory	/workspace/16.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access.3573931803
Short name	T910
Test name
Test status
Simulation time	404212633 ps
CPU time	19.81 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:35:05 PM PDT 24
Peak memory	268212 kb
Host	smart-d191fd91-5246-468a-8cb6-a92fce9046f0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573931803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3573931803
Directory	/workspace/16.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1428803530
Short name	T841
Test name
Test status
Simulation time	15712100534 ps
CPU time	407.12 seconds
Started	Jun 07 07:34:38 PM PDT 24
Finished	Jun 07 07:41:29 PM PDT 24
Peak memory	202952 kb
Host	smart-c4d32258-bb76-4ab6-9e13-29b5bb859257
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428803530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.1428803530
Directory	/workspace/16.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/16.sram_ctrl_ram_cfg.2540649747
Short name	T496
Test name
Test status
Simulation time	86265970 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:34:47 PM PDT 24
Peak memory	202896 kb
Host	smart-c7258cbc-9ba5-4760-832b-78f1578131b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540649747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2540649747
Directory	/workspace/16.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/16.sram_ctrl_regwen.3941162801
Short name	T687
Test name
Test status
Simulation time	1860816307 ps
CPU time	247.35 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:38:52 PM PDT 24
Peak memory	367524 kb
Host	smart-dfc8532a-e8e8-4dd9-8929-af0c4c38a4d2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941162801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3941162801
Directory	/workspace/16.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/16.sram_ctrl_smoke.1667888540
Short name	T682
Test name
Test status
Simulation time	1162438062 ps
CPU time	73.1 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:35:58 PM PDT 24
Peak memory	332668 kb
Host	smart-0ff28cdb-b75d-4059-8b82-9426cecd04fd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667888540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1667888540
Directory	/workspace/16.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3296385171
Short name	T49
Test name
Test status
Simulation time	1828268035 ps
CPU time	267.47 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:39:12 PM PDT 24
Peak memory	377444 kb
Host	smart-64a5c114-6ce7-45a4-8590-73310ae76278
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3296385171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3296385171
Directory	/workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3353918955
Short name	T529
Test name
Test status
Simulation time	30272849844 ps
CPU time	189.01 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:37:55 PM PDT 24
Peak memory	202924 kb
Host	smart-45968351-d296-423d-ae7a-44ca8086c8b7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353918955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.3353918955
Directory	/workspace/16.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2466112619
Short name	T343
Test name
Test status
Simulation time	176881699 ps
CPU time	2.55 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:34:48 PM PDT 24
Peak memory	218592 kb
Host	smart-b61713e8-e579-49c9-a90c-47cbd4e60360
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466112619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2466112619
Directory	/workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3771786892
Short name	T153
Test name
Test status
Simulation time	1100149616 ps
CPU time	94.3 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:36:18 PM PDT 24
Peak memory	285968 kb
Host	smart-7b6da350-6cc3-488d-9803-228ed129a28b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771786892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.3771786892
Directory	/workspace/17.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/17.sram_ctrl_alert_test.3006483997
Short name	T889
Test name
Test status
Simulation time	16424084 ps
CPU time	0.67 seconds
Started	Jun 07 07:34:44 PM PDT 24
Finished	Jun 07 07:34:48 PM PDT 24
Peak memory	202556 kb
Host	smart-4616c2a9-c7c8-46a9-8cf1-88d311a54b26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006483997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3006483997
Directory	/workspace/17.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.sram_ctrl_bijection.968319904
Short name	T335
Test name
Test status
Simulation time	5960372465 ps
CPU time	42.23 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:35:28 PM PDT 24
Peak memory	203036 kb
Host	smart-84e36726-8ad5-436c-9343-8fd7a4e821b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968319904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection. 968319904
Directory	/workspace/17.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/17.sram_ctrl_executable.1880603296
Short name	T475
Test name
Test status
Simulation time	2761880935 ps
CPU time	78.84 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:36:04 PM PDT 24
Peak memory	265264 kb
Host	smart-5db28f55-7456-4129-a3ae-10104fb40187
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880603296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.1880603296
Directory	/workspace/17.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/17.sram_ctrl_lc_escalation.1280735105
Short name	T391
Test name
Test status
Simulation time	1022301422 ps
CPU time	6.3 seconds
Started	Jun 07 07:34:38 PM PDT 24
Finished	Jun 07 07:34:49 PM PDT 24
Peak memory	214360 kb
Host	smart-8fcb4d72-fe12-421f-b8b0-89456ecf3e4a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280735105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1280735105
Directory	/workspace/17.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/17.sram_ctrl_max_throughput.1603666827
Short name	T887
Test name
Test status
Simulation time	500492953 ps
CPU time	35.65 seconds
Started	Jun 07 07:34:39 PM PDT 24
Finished	Jun 07 07:35:18 PM PDT 24
Peak memory	290064 kb
Host	smart-56b61038-4c41-4a2a-bc37-445b499fd37b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603666827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.1603666827
Directory	/workspace/17.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_partial_access.414431302
Short name	T146
Test name
Test status
Simulation time	63665426 ps
CPU time	4.5 seconds
Started	Jun 07 07:34:48 PM PDT 24
Finished	Jun 07 07:34:55 PM PDT 24
Peak memory	211060 kb
Host	smart-42b71ad8-1099-4943-ab62-26d6a41856be
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414431302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sram_ctrl_mem_partial_access.414431302
Directory	/workspace/17.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_mem_walk.1501136196
Short name	T405
Test name
Test status
Simulation time	336225029 ps
CPU time	6.1 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:34:56 PM PDT 24
Peak memory	211072 kb
Host	smart-0b4d605f-b619-49f2-835a-fe35ec29ccfa
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501136196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.1501136196
Directory	/workspace/17.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/17.sram_ctrl_multiple_keys.1206198715
Short name	T777
Test name
Test status
Simulation time	2336106865 ps
CPU time	217.75 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:38:24 PM PDT 24
Peak memory	334916 kb
Host	smart-f6276732-ed81-4aba-afa7-4e799c9f7edf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206198715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.1206198715
Directory	/workspace/17.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access.1244404666
Short name	T342
Test name
Test status
Simulation time	1300864389 ps
CPU time	143.36 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:37:09 PM PDT 24
Peak memory	367372 kb
Host	smart-13f883a2-9b63-4554-8773-087a228d8c48
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244404666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_partial_access.1244404666
Directory	/workspace/17.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2482733293
Short name	T888
Test name
Test status
Simulation time	41395596645 ps
CPU time	568.11 seconds
Started	Jun 07 07:34:44 PM PDT 24
Finished	Jun 07 07:44:16 PM PDT 24
Peak memory	203012 kb
Host	smart-587cc1b2-b711-4dbb-97f7-7fc6379942ff
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482733293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.2482733293
Directory	/workspace/17.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/17.sram_ctrl_ram_cfg.394661272
Short name	T742
Test name
Test status
Simulation time	48645854 ps
CPU time	0.8 seconds
Started	Jun 07 07:34:48 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	202900 kb
Host	smart-212af904-f929-4253-95ea-15879d237c11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394661272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.394661272
Directory	/workspace/17.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/17.sram_ctrl_regwen.2119107581
Short name	T552
Test name
Test status
Simulation time	6102289215 ps
CPU time	779.95 seconds
Started	Jun 07 07:34:43 PM PDT 24
Finished	Jun 07 07:47:47 PM PDT 24
Peak memory	374212 kb
Host	smart-3ea74e1a-4431-48c0-a121-68172363d8ff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119107581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2119107581
Directory	/workspace/17.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/17.sram_ctrl_smoke.3330043310
Short name	T794
Test name
Test status
Simulation time	477087674 ps
CPU time	68.62 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:35:53 PM PDT 24
Peak memory	322532 kb
Host	smart-6230a963-f0c1-401e-9751-d08233f5b4bf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330043310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3330043310
Directory	/workspace/17.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all.3144684419
Short name	T400
Test name
Test status
Simulation time	6626424240 ps
CPU time	108.31 seconds
Started	Jun 07 07:34:46 PM PDT 24
Finished	Jun 07 07:36:37 PM PDT 24
Peak memory	301728 kb
Host	smart-68f54c49-5dbd-4771-8686-e432162dc5d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144684419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.3144684419
Directory	/workspace/17.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.797570841
Short name	T59
Test name
Test status
Simulation time	16055565727 ps
CPU time	501.59 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:43:11 PM PDT 24
Peak memory	374696 kb
Host	smart-fee5bf97-97e0-4f93-a9c2-7ff43537038c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=797570841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.797570841
Directory	/workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3202974073
Short name	T312
Test name
Test status
Simulation time	13254928085 ps
CPU time	330.64 seconds
Started	Jun 07 07:34:40 PM PDT 24
Finished	Jun 07 07:40:16 PM PDT 24
Peak memory	203000 kb
Host	smart-788a40fe-01e3-48f1-8c6e-40ff3a7e6ecf
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202974073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.3202974073
Directory	/workspace/17.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1677271969
Short name	T653
Test name
Test status
Simulation time	122000219 ps
CPU time	50.18 seconds
Started	Jun 07 07:34:41 PM PDT 24
Finished	Jun 07 07:35:36 PM PDT 24
Peak memory	303204 kb
Host	smart-9f73210e-a9c2-49bb-978b-0b29d762c279
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677271969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1677271969
Directory	/workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2906643020
Short name	T31
Test name
Test status
Simulation time	515068672 ps
CPU time	22.56 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:35:12 PM PDT 24
Peak memory	246448 kb
Host	smart-f691179c-bc1e-4e8f-adc5-6d0fb4ac2d77
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906643020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.2906643020
Directory	/workspace/18.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/18.sram_ctrl_alert_test.4141971400
Short name	T584
Test name
Test status
Simulation time	15592321 ps
CPU time	0.64 seconds
Started	Jun 07 07:34:48 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	202624 kb
Host	smart-64cac722-066c-4e7f-800f-dab620f26c18
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141971400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.4141971400
Directory	/workspace/18.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.sram_ctrl_bijection.465795837
Short name	T924
Test name
Test status
Simulation time	6599429481 ps
CPU time	65.66 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:35:55 PM PDT 24
Peak memory	202964 kb
Host	smart-3ecc9ce6-249f-4956-927e-25547bee05d2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465795837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection. 465795837
Directory	/workspace/18.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/18.sram_ctrl_executable.2239127624
Short name	T654
Test name
Test status
Simulation time	59895292019 ps
CPU time	1634.25 seconds
Started	Jun 07 07:34:49 PM PDT 24
Finished	Jun 07 08:02:05 PM PDT 24
Peak memory	372756 kb
Host	smart-f2fab439-0371-478f-b75f-1c2689cc9159
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239127624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.2239127624
Directory	/workspace/18.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/18.sram_ctrl_lc_escalation.2331984639
Short name	T708
Test name
Test status
Simulation time	344398817 ps
CPU time	4.92 seconds
Started	Jun 07 07:34:46 PM PDT 24
Finished	Jun 07 07:34:54 PM PDT 24
Peak memory	202892 kb
Host	smart-65c34352-5a91-4f86-83d4-b8a6b06d3b4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331984639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es calation.2331984639
Directory	/workspace/18.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/18.sram_ctrl_max_throughput.1354796469
Short name	T262
Test name
Test status
Simulation time	139232639 ps
CPU time	160.51 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:37:30 PM PDT 24
Peak memory	370272 kb
Host	smart-c32f34b9-095e-4427-a60f-107748d4a502
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354796469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1354796469
Directory	/workspace/18.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_partial_access.543983468
Short name	T19
Test name
Test status
Simulation time	601363202 ps
CPU time	5.93 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:34:55 PM PDT 24
Peak memory	211116 kb
Host	smart-9f59ae13-74bf-4f6e-a99f-e1a01eb48693
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543983468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_mem_partial_access.543983468
Directory	/workspace/18.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_mem_walk.746482196
Short name	T787
Test name
Test status
Simulation time	543005428 ps
CPU time	8.96 seconds
Started	Jun 07 07:34:45 PM PDT 24
Finished	Jun 07 07:34:57 PM PDT 24
Peak memory	202784 kb
Host	smart-723440f2-3c8b-4316-a46f-bd7d40d72030
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746482196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _mem_walk.746482196
Directory	/workspace/18.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/18.sram_ctrl_multiple_keys.79387596
Short name	T375
Test name
Test status
Simulation time	56244667502 ps
CPU time	1486.36 seconds
Started	Jun 07 07:34:49 PM PDT 24
Finished	Jun 07 07:59:38 PM PDT 24
Peak memory	376068 kb
Host	smart-72dec4eb-2e8f-4665-b8a5-41a2e3e8bc90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79387596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multipl e_keys.79387596
Directory	/workspace/18.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access.3005407516
Short name	T173
Test name
Test status
Simulation time	3639037498 ps
CPU time	19.73 seconds
Started	Jun 07 07:34:48 PM PDT 24
Finished	Jun 07 07:35:10 PM PDT 24
Peak memory	202916 kb
Host	smart-0d34538f-d7cf-4861-9ea4-f1bc76f8202c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005407516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.3005407516
Directory	/workspace/18.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1254450152
Short name	T717
Test name
Test status
Simulation time	64316115053 ps
CPU time	265.92 seconds
Started	Jun 07 07:34:45 PM PDT 24
Finished	Jun 07 07:39:14 PM PDT 24
Peak memory	202980 kb
Host	smart-fb58e9e7-c1d1-4eab-979f-18cb39226e6a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254450152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.1254450152
Directory	/workspace/18.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/18.sram_ctrl_ram_cfg.823755510
Short name	T810
Test name
Test status
Simulation time	78438104 ps
CPU time	0.75 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:34:50 PM PDT 24
Peak memory	202916 kb
Host	smart-8143a257-5003-41c8-822c-59df188584a9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823755510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.823755510
Directory	/workspace/18.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/18.sram_ctrl_regwen.931395561
Short name	T359
Test name
Test status
Simulation time	7291359266 ps
CPU time	428.97 seconds
Started	Jun 07 07:34:45 PM PDT 24
Finished	Jun 07 07:41:57 PM PDT 24
Peak memory	363864 kb
Host	smart-d8786538-c890-4dba-bee7-fc2b18875df5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931395561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.931395561
Directory	/workspace/18.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/18.sram_ctrl_smoke.1586456938
Short name	T595
Test name
Test status
Simulation time	46122161 ps
CPU time	1.65 seconds
Started	Jun 07 07:34:47 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	202944 kb
Host	smart-c9f5be79-df44-4000-9275-9095bc0b8bfe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586456938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1586456938
Directory	/workspace/18.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_all.160526939
Short name	T495
Test name
Test status
Simulation time	35438387237 ps
CPU time	1545.75 seconds
Started	Jun 07 07:34:49 PM PDT 24
Finished	Jun 07 08:00:37 PM PDT 24
Peak memory	372792 kb
Host	smart-83c2f792-3eea-4564-9b56-f3e93b78c43d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160526939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_stress_all.160526939
Directory	/workspace/18.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.sram_ctrl_stress_pipeline.795814212
Short name	T437
Test name
Test status
Simulation time	5242959618 ps
CPU time	262.24 seconds
Started	Jun 07 07:34:45 PM PDT 24
Finished	Jun 07 07:39:11 PM PDT 24
Peak memory	202984 kb
Host	smart-97559b4b-dec2-44ec-a7bf-97bc73f3a7d7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795814212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_stress_pipeline.795814212
Directory	/workspace/18.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.481644200
Short name	T897
Test name
Test status
Simulation time	124299012 ps
CPU time	1.39 seconds
Started	Jun 07 07:34:48 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	211124 kb
Host	smart-bf0c63a5-546e-4f49-a003-e1d9c617eb80
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481644200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.481644200
Directory	/workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/19.sram_ctrl_access_during_key_req.434946970
Short name	T358
Test name
Test status
Simulation time	6162555066 ps
CPU time	1038.73 seconds
Started	Jun 07 07:34:55 PM PDT 24
Finished	Jun 07 07:52:15 PM PDT 24
Peak memory	375612 kb
Host	smart-5bb1a7b1-6d6f-4e7d-ae6d-1742aba6cff0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434946970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.434946970
Directory	/workspace/19.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/19.sram_ctrl_alert_test.1618284465
Short name	T522
Test name
Test status
Simulation time	12781254 ps
CPU time	0.66 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:35:04 PM PDT 24
Peak memory	202632 kb
Host	smart-68b1b5e8-9c3f-4e14-b0e0-2faa4984f47e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618284465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1618284465
Directory	/workspace/19.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.sram_ctrl_bijection.4254066833
Short name	T736
Test name
Test status
Simulation time	11478506404 ps
CPU time	66 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:36:08 PM PDT 24
Peak memory	203000 kb
Host	smart-dd239131-61b1-45df-b94d-7e8b6636dc07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254066833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .4254066833
Directory	/workspace/19.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/19.sram_ctrl_executable.990509970
Short name	T337
Test name
Test status
Simulation time	10589174472 ps
CPU time	312 seconds
Started	Jun 07 07:34:52 PM PDT 24
Finished	Jun 07 07:40:06 PM PDT 24
Peak memory	344104 kb
Host	smart-8633a5c2-e028-407d-bd22-1010cc07b4f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990509970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.990509970
Directory	/workspace/19.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/19.sram_ctrl_lc_escalation.1990161389
Short name	T686
Test name
Test status
Simulation time	657299571 ps
CPU time	4 seconds
Started	Jun 07 07:35:00 PM PDT 24
Finished	Jun 07 07:35:05 PM PDT 24
Peak memory	202980 kb
Host	smart-005a342d-28b7-4ea4-b60d-a78c9a1193fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990161389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.1990161389
Directory	/workspace/19.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/19.sram_ctrl_max_throughput.3794298092
Short name	T182
Test name
Test status
Simulation time	93331643 ps
CPU time	33.08 seconds
Started	Jun 07 07:34:54 PM PDT 24
Finished	Jun 07 07:35:29 PM PDT 24
Peak memory	289780 kb
Host	smart-eb1d18cb-50f4-4497-9f11-ddd3f8eb50ed
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794298092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.3794298092
Directory	/workspace/19.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_partial_access.505408998
Short name	T908
Test name
Test status
Simulation time	233325859 ps
CPU time	3.29 seconds
Started	Jun 07 07:35:00 PM PDT 24
Finished	Jun 07 07:35:05 PM PDT 24
Peak memory	211092 kb
Host	smart-83100214-fd44-48c7-aed3-f896ea331fdc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505408998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sram_ctrl_mem_partial_access.505408998
Directory	/workspace/19.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_mem_walk.3005917624
Short name	T563
Test name
Test status
Simulation time	92994245 ps
CPU time	5.11 seconds
Started	Jun 07 07:34:51 PM PDT 24
Finished	Jun 07 07:34:58 PM PDT 24
Peak memory	211064 kb
Host	smart-7967fcf9-3bf6-44d1-a208-cef585f6a715
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005917624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3005917624
Directory	/workspace/19.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/19.sram_ctrl_multiple_keys.827219450
Short name	T851
Test name
Test status
Simulation time	16339930214 ps
CPU time	439.44 seconds
Started	Jun 07 07:34:53 PM PDT 24
Finished	Jun 07 07:42:14 PM PDT 24
Peak memory	361432 kb
Host	smart-efedb1ed-e70a-4f10-8d33-352770d43ce9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827219450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip le_keys.827219450
Directory	/workspace/19.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access.3397793986
Short name	T558
Test name
Test status
Simulation time	4002993805 ps
CPU time	20.46 seconds
Started	Jun 07 07:34:54 PM PDT 24
Finished	Jun 07 07:35:16 PM PDT 24
Peak memory	202932 kb
Host	smart-a5d25fd5-1779-4b73-bebe-f3aa7c2fdc26
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397793986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3397793986
Directory	/workspace/19.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.3767689517
Short name	T103
Test name
Test status
Simulation time	150106672558 ps
CPU time	562.34 seconds
Started	Jun 07 07:34:55 PM PDT 24
Finished	Jun 07 07:44:19 PM PDT 24
Peak memory	203028 kb
Host	smart-162058d6-4f86-427c-8175-b4d15baee0e9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767689517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.3767689517
Directory	/workspace/19.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/19.sram_ctrl_ram_cfg.942870032
Short name	T554
Test name
Test status
Simulation time	48652289 ps
CPU time	0.77 seconds
Started	Jun 07 07:34:51 PM PDT 24
Finished	Jun 07 07:34:53 PM PDT 24
Peak memory	202912 kb
Host	smart-382b2f84-19c5-4752-932c-4353d8498ae6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942870032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.942870032
Directory	/workspace/19.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/19.sram_ctrl_regwen.579242959
Short name	T616
Test name
Test status
Simulation time	11908214963 ps
CPU time	774.75 seconds
Started	Jun 07 07:34:54 PM PDT 24
Finished	Jun 07 07:47:51 PM PDT 24
Peak memory	374744 kb
Host	smart-53024dd0-35dd-459b-835a-4696dfaeaefb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579242959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.579242959
Directory	/workspace/19.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/19.sram_ctrl_smoke.2148928636
Short name	T857
Test name
Test status
Simulation time	499811916 ps
CPU time	60.06 seconds
Started	Jun 07 07:34:53 PM PDT 24
Finished	Jun 07 07:35:55 PM PDT 24
Peak memory	323332 kb
Host	smart-f9a5ea88-79e9-47ce-9a5b-deafa43c27c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148928636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2148928636
Directory	/workspace/19.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all.380035574
Short name	T514
Test name
Test status
Simulation time	20720067919 ps
CPU time	1128.5 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:53:52 PM PDT 24
Peak memory	375916 kb
Host	smart-c668012d-e762-4122-a392-49f97025d548
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380035574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_stress_all.380035574
Directory	/workspace/19.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1871827109
Short name	T830
Test name
Test status
Simulation time	4254862305 ps
CPU time	51.35 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:35:55 PM PDT 24
Peak memory	244420 kb
Host	smart-66b544c7-5373-4d6a-9cd7-e1cbabf7bfa9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1871827109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1871827109
Directory	/workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1456957628
Short name	T450
Test name
Test status
Simulation time	6952541733 ps
CPU time	171.28 seconds
Started	Jun 07 07:34:52 PM PDT 24
Finished	Jun 07 07:37:45 PM PDT 24
Peak memory	202892 kb
Host	smart-d4171278-c009-4c00-927b-12513703a42f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456957628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.1456957628
Directory	/workspace/19.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1494251402
Short name	T410
Test name
Test status
Simulation time	762404448 ps
CPU time	70.29 seconds
Started	Jun 07 07:34:52 PM PDT 24
Finished	Jun 07 07:36:04 PM PDT 24
Peak memory	317260 kb
Host	smart-72683796-2b24-473d-91d6-535a75162472
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494251402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1494251402
Directory	/workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3589323840
Short name	T757
Test name
Test status
Simulation time	2665584153 ps
CPU time	605.64 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:43:41 PM PDT 24
Peak memory	372648 kb
Host	smart-54cfbbbf-0f00-4f91-a70e-8a140d4f51f7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589323840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.3589323840
Directory	/workspace/2.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/2.sram_ctrl_alert_test.3863555865
Short name	T481
Test name
Test status
Simulation time	22512345 ps
CPU time	0.68 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:33:38 PM PDT 24
Peak memory	202632 kb
Host	smart-78891b1a-b55c-4085-9916-30aa098de8e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863555865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3863555865
Directory	/workspace/2.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.sram_ctrl_bijection.1841240742
Short name	T279
Test name
Test status
Simulation time	12639106119 ps
CPU time	71.75 seconds
Started	Jun 07 07:33:34 PM PDT 24
Finished	Jun 07 07:34:51 PM PDT 24
Peak memory	202984 kb
Host	smart-69868a36-19e0-4a4f-84b8-2e468ca76501
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841240742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 1841240742
Directory	/workspace/2.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/2.sram_ctrl_executable.2791131954
Short name	T130
Test name
Test status
Simulation time	51153358027 ps
CPU time	1319.33 seconds
Started	Jun 07 07:33:31 PM PDT 24
Finished	Jun 07 07:55:34 PM PDT 24
Peak memory	375464 kb
Host	smart-57373a78-760b-46b8-a437-c54967e50c42
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791131954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2791131954
Directory	/workspace/2.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/2.sram_ctrl_lc_escalation.3793317973
Short name	T145
Test name
Test status
Simulation time	428943613 ps
CPU time	4.52 seconds
Started	Jun 07 07:33:29 PM PDT 24
Finished	Jun 07 07:33:36 PM PDT 24
Peak memory	211136 kb
Host	smart-5035c27a-f484-47e1-a1fe-6434ce5dd5d0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793317973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.3793317973
Directory	/workspace/2.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/2.sram_ctrl_max_throughput.3114201687
Short name	T771
Test name
Test status
Simulation time	627257708 ps
CPU time	19.34 seconds
Started	Jun 07 07:33:28 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	261924 kb
Host	smart-e3c45f9e-085e-406f-ae66-67237e7cd9b6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114201687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3114201687
Directory	/workspace/2.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1573309298
Short name	T246
Test name
Test status
Simulation time	66114631 ps
CPU time	4.66 seconds
Started	Jun 07 07:33:33 PM PDT 24
Finished	Jun 07 07:33:42 PM PDT 24
Peak memory	211056 kb
Host	smart-27f9e813-fb95-48a7-9f5a-e07b635c2dd4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573309298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1573309298
Directory	/workspace/2.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_mem_walk.4130967380
Short name	T745
Test name
Test status
Simulation time	363322628 ps
CPU time	9.34 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:33:45 PM PDT 24
Peak memory	211124 kb
Host	smart-22883d3c-81c1-4e30-ad7e-df751d5a53be
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130967380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.4130967380
Directory	/workspace/2.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/2.sram_ctrl_multiple_keys.763779885
Short name	T230
Test name
Test status
Simulation time	40424876336 ps
CPU time	1063.45 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:51:31 PM PDT 24
Peak memory	357436 kb
Host	smart-7451a785-1d27-46e6-8e7f-47af9d5f8a78
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763779885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multipl e_keys.763779885
Directory	/workspace/2.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access.3770455205
Short name	T376
Test name
Test status
Simulation time	2150914668 ps
CPU time	76.03 seconds
Started	Jun 07 07:33:35 PM PDT 24
Finished	Jun 07 07:34:56 PM PDT 24
Peak memory	343232 kb
Host	smart-137258cd-bed7-40cc-963c-8ee2ad3cc9cb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770455205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.3770455205
Directory	/workspace/2.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1206285385
Short name	T515
Test name
Test status
Simulation time	19230133448 ps
CPU time	349.95 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:39:25 PM PDT 24
Peak memory	203024 kb
Host	smart-191e2dfa-efdc-4b88-935d-82edab11426f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206285385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.1206285385
Directory	/workspace/2.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/2.sram_ctrl_ram_cfg.2010479349
Short name	T323
Test name
Test status
Simulation time	137803574 ps
CPU time	0.76 seconds
Started	Jun 07 07:33:27 PM PDT 24
Finished	Jun 07 07:33:31 PM PDT 24
Peak memory	202888 kb
Host	smart-adb98ad3-3881-4cb7-8a6b-aeecbd86499c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010479349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2010479349
Directory	/workspace/2.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/2.sram_ctrl_regwen.4164418122
Short name	T196
Test name
Test status
Simulation time	67726979321 ps
CPU time	930.59 seconds
Started	Jun 07 07:33:32 PM PDT 24
Finished	Jun 07 07:49:06 PM PDT 24
Peak memory	376780 kb
Host	smart-6183a9b1-63c5-41df-9b11-e74a3e215fe8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164418122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.4164418122
Directory	/workspace/2.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/2.sram_ctrl_smoke.38267538
Short name	T511
Test name
Test status
Simulation time	1600263120 ps
CPU time	9.99 seconds
Started	Jun 07 07:33:47 PM PDT 24
Finished	Jun 07 07:34:01 PM PDT 24
Peak memory	202960 kb
Host	smart-bf8a31cb-f11d-46fd-8705-1e718cd5fd5a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.38267538
Directory	/workspace/2.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all.943500772
Short name	T7
Test name
Test status
Simulation time	3823096037 ps
CPU time	72.56 seconds
Started	Jun 07 07:33:31 PM PDT 24
Finished	Jun 07 07:34:47 PM PDT 24
Peak memory	211168 kb
Host	smart-86330597-7c03-4811-b25d-e62e5fe10b59
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943500772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.943500772
Directory	/workspace/2.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2884932167
Short name	T365
Test name
Test status
Simulation time	2451185300 ps
CPU time	278.34 seconds
Started	Jun 07 07:33:35 PM PDT 24
Finished	Jun 07 07:38:18 PM PDT 24
Peak memory	370148 kb
Host	smart-3f542638-3233-4086-9eee-a800f935088b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2884932167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2884932167
Directory	/workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1025272648
Short name	T189
Test name
Test status
Simulation time	12229183537 ps
CPU time	268.75 seconds
Started	Jun 07 07:33:47 PM PDT 24
Finished	Jun 07 07:38:19 PM PDT 24
Peak memory	202984 kb
Host	smart-031da936-8478-4358-b72d-c237c44dcdea
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025272648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1025272648
Directory	/workspace/2.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3412619833
Short name	T598
Test name
Test status
Simulation time	117046923 ps
CPU time	54.04 seconds
Started	Jun 07 07:33:47 PM PDT 24
Finished	Jun 07 07:34:45 PM PDT 24
Peak memory	302716 kb
Host	smart-cafb4b73-3fdc-41eb-9e44-9cbe8e0648c0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412619833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3412619833
Directory	/workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/20.sram_ctrl_access_during_key_req.203361383
Short name	T162
Test name
Test status
Simulation time	8213436335 ps
CPU time	763.57 seconds
Started	Jun 07 07:35:02 PM PDT 24
Finished	Jun 07 07:47:47 PM PDT 24
Peak memory	369032 kb
Host	smart-23887582-0af0-4be2-a0a8-09918773885f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203361383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.sram_ctrl_access_during_key_req.203361383
Directory	/workspace/20.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/20.sram_ctrl_alert_test.1925839898
Short name	T305
Test name
Test status
Simulation time	85364537 ps
CPU time	0.66 seconds
Started	Jun 07 07:35:12 PM PDT 24
Finished	Jun 07 07:35:14 PM PDT 24
Peak memory	202620 kb
Host	smart-3fa2959c-94c9-4355-a2e7-524af27acdde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925839898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1925839898
Directory	/workspace/20.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.sram_ctrl_bijection.1100039726
Short name	T448
Test name
Test status
Simulation time	5738852107 ps
CPU time	47.09 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:35:49 PM PDT 24
Peak memory	203000 kb
Host	smart-d5607f3f-d51a-45f1-83a1-3a9ee054a5af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100039726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection .1100039726
Directory	/workspace/20.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/20.sram_ctrl_lc_escalation.1253651404
Short name	T386
Test name
Test status
Simulation time	1553007599 ps
CPU time	6.48 seconds
Started	Jun 07 07:35:04 PM PDT 24
Finished	Jun 07 07:35:11 PM PDT 24
Peak memory	214600 kb
Host	smart-64cb88e6-dea7-4df2-b53f-d59ca6d49798
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253651404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.1253651404
Directory	/workspace/20.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/20.sram_ctrl_max_throughput.938145013
Short name	T347
Test name
Test status
Simulation time	185300877 ps
CPU time	91.5 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:36:35 PM PDT 24
Peak memory	345040 kb
Host	smart-9079c407-2b65-4502-9388-bfd84f1037d3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938145013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.sram_ctrl_max_throughput.938145013
Directory	/workspace/20.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_partial_access.1454890392
Short name	T84
Test name
Test status
Simulation time	193863471 ps
CPU time	4.92 seconds
Started	Jun 07 07:35:08 PM PDT 24
Finished	Jun 07 07:35:14 PM PDT 24
Peak memory	211100 kb
Host	smart-f07844c4-c74a-4112-b3a8-02b0276d454b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454890392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.1454890392
Directory	/workspace/20.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_mem_walk.3217510151
Short name	T38
Test name
Test status
Simulation time	1136046161 ps
CPU time	7.04 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 07:35:18 PM PDT 24
Peak memory	211020 kb
Host	smart-fb7f159e-cc0a-4b1a-aa4e-e0190ff24435
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217510151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3217510151
Directory	/workspace/20.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/20.sram_ctrl_multiple_keys.1878461677
Short name	T269
Test name
Test status
Simulation time	2124725440 ps
CPU time	731.1 seconds
Started	Jun 07 07:35:04 PM PDT 24
Finished	Jun 07 07:47:16 PM PDT 24
Peak memory	374328 kb
Host	smart-bfc0a78d-6910-4995-a65f-75b3f004aca1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878461677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.1878461677
Directory	/workspace/20.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access.1669069942
Short name	T367
Test name
Test status
Simulation time	156645130 ps
CPU time	8.33 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:35:12 PM PDT 24
Peak memory	234332 kb
Host	smart-ce0816fd-7f68-4943-bdff-59a00de6ebe5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669069942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1669069942
Directory	/workspace/20.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2139141566
Short name	T324
Test name
Test status
Simulation time	42673721919 ps
CPU time	433.71 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:42:16 PM PDT 24
Peak memory	202976 kb
Host	smart-5853df34-51ae-4fbb-9a00-12715fdf671e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139141566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.2139141566
Directory	/workspace/20.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/20.sram_ctrl_ram_cfg.3925360477
Short name	T254
Test name
Test status
Simulation time	56061450 ps
CPU time	0.79 seconds
Started	Jun 07 07:35:01 PM PDT 24
Finished	Jun 07 07:35:04 PM PDT 24
Peak memory	202916 kb
Host	smart-b19c1476-3933-4585-a108-ab4995855255
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925360477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3925360477
Directory	/workspace/20.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/20.sram_ctrl_regwen.3020258022
Short name	T920
Test name
Test status
Simulation time	4210580494 ps
CPU time	1928.63 seconds
Started	Jun 07 07:35:02 PM PDT 24
Finished	Jun 07 08:07:12 PM PDT 24
Peak memory	371744 kb
Host	smart-515f770f-9326-4a31-94c1-ad4f1b627d16
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020258022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3020258022
Directory	/workspace/20.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/20.sram_ctrl_smoke.2869459054
Short name	T828
Test name
Test status
Simulation time	95939950 ps
CPU time	5.45 seconds
Started	Jun 07 07:35:04 PM PDT 24
Finished	Jun 07 07:35:11 PM PDT 24
Peak memory	231428 kb
Host	smart-5899eb29-46fd-4fad-be5a-c65e80a8df02
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869459054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2869459054
Directory	/workspace/20.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all.302557812
Short name	T283
Test name
Test status
Simulation time	15252366914 ps
CPU time	2828.09 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 08:22:19 PM PDT 24
Peak memory	376232 kb
Host	smart-ef8e0ca1-5fc4-429c-8d7b-a8f115dbe5be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302557812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_stress_all.302557812
Directory	/workspace/20.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3710879590
Short name	T536
Test name
Test status
Simulation time	5846397588 ps
CPU time	215.78 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 07:38:46 PM PDT 24
Peak memory	326752 kb
Host	smart-4fd3b263-daf2-447b-be83-162840a20ea6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3710879590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3710879590
Directory	/workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1624117870
Short name	T452
Test name
Test status
Simulation time	3189102235 ps
CPU time	168.83 seconds
Started	Jun 07 07:35:00 PM PDT 24
Finished	Jun 07 07:37:51 PM PDT 24
Peak memory	202936 kb
Host	smart-fe76b8f3-909e-4a24-88d6-eb384cb47126
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624117870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.1624117870
Directory	/workspace/20.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1395642294
Short name	T401
Test name
Test status
Simulation time	153904253 ps
CPU time	156.56 seconds
Started	Jun 07 07:35:02 PM PDT 24
Finished	Jun 07 07:37:41 PM PDT 24
Peak memory	369384 kb
Host	smart-bb690441-c5b9-4dcd-9c9e-a3d381da5897
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395642294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1395642294
Directory	/workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2655447645
Short name	T854
Test name
Test status
Simulation time	8508319236 ps
CPU time	737.07 seconds
Started	Jun 07 07:35:08 PM PDT 24
Finished	Jun 07 07:47:26 PM PDT 24
Peak memory	373772 kb
Host	smart-79c58114-f9a1-438a-b462-db82db36ad07
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655447645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 21.sram_ctrl_access_during_key_req.2655447645
Directory	/workspace/21.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/21.sram_ctrl_alert_test.2148224710
Short name	T253
Test name
Test status
Simulation time	25009053 ps
CPU time	0.64 seconds
Started	Jun 07 07:35:15 PM PDT 24
Finished	Jun 07 07:35:17 PM PDT 24
Peak memory	202632 kb
Host	smart-8172cdbb-f9f6-4c8a-a399-994aad250145
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148224710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2148224710
Directory	/workspace/21.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.sram_ctrl_bijection.2920720905
Short name	T546
Test name
Test status
Simulation time	3683047081 ps
CPU time	65.34 seconds
Started	Jun 07 07:35:07 PM PDT 24
Finished	Jun 07 07:36:13 PM PDT 24
Peak memory	202992 kb
Host	smart-8538012b-9bab-479a-9b07-262bbe1af61f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920720905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .2920720905
Directory	/workspace/21.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/21.sram_ctrl_executable.4288027875
Short name	T743
Test name
Test status
Simulation time	35654320395 ps
CPU time	387.55 seconds
Started	Jun 07 07:35:07 PM PDT 24
Finished	Jun 07 07:41:36 PM PDT 24
Peak memory	374392 kb
Host	smart-62548bb3-47b5-4986-bdce-1f8612ed92bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288027875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.4288027875
Directory	/workspace/21.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/21.sram_ctrl_lc_escalation.2029054980
Short name	T683
Test name
Test status
Simulation time	1473628410 ps
CPU time	5.84 seconds
Started	Jun 07 07:35:12 PM PDT 24
Finished	Jun 07 07:35:19 PM PDT 24
Peak memory	202924 kb
Host	smart-64783d1c-651f-49fc-92bf-2def5f960e87
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029054980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.2029054980
Directory	/workspace/21.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/21.sram_ctrl_max_throughput.1833458250
Short name	T610
Test name
Test status
Simulation time	54548102 ps
CPU time	4.66 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 07:35:15 PM PDT 24
Peak memory	227276 kb
Host	smart-f90518f2-c799-4545-b7ca-d21b8d851a6d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833458250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.1833458250
Directory	/workspace/21.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2481882588
Short name	T719
Test name
Test status
Simulation time	214845511 ps
CPU time	2.8 seconds
Started	Jun 07 07:35:21 PM PDT 24
Finished	Jun 07 07:35:25 PM PDT 24
Peak memory	211128 kb
Host	smart-9a604ef0-9399-4cc0-921c-608f1cd393cd
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481882588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.2481882588
Directory	/workspace/21.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_mem_walk.708437249
Short name	T191
Test name
Test status
Simulation time	927211358 ps
CPU time	5.93 seconds
Started	Jun 07 07:35:16 PM PDT 24
Finished	Jun 07 07:35:23 PM PDT 24
Peak memory	211072 kb
Host	smart-325ad40a-fb10-4d1b-8cad-9ba9f20417fd
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708437249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _mem_walk.708437249
Directory	/workspace/21.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/21.sram_ctrl_multiple_keys.2172180672
Short name	T881
Test name
Test status
Simulation time	2262310030 ps
CPU time	474.12 seconds
Started	Jun 07 07:35:10 PM PDT 24
Finished	Jun 07 07:43:06 PM PDT 24
Peak memory	360288 kb
Host	smart-ba880e1c-c853-4e88-882d-05c7aa352a76
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172180672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2172180672
Directory	/workspace/21.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access.2381534810
Short name	T344
Test name
Test status
Simulation time	201147735 ps
CPU time	75.18 seconds
Started	Jun 07 07:35:08 PM PDT 24
Finished	Jun 07 07:36:25 PM PDT 24
Peak memory	348648 kb
Host	smart-86261c52-2322-4c18-b56f-540a5bd9e6ac
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381534810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2381534810
Directory	/workspace/21.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2982763149
Short name	T373
Test name
Test status
Simulation time	36326358829 ps
CPU time	336.56 seconds
Started	Jun 07 07:35:07 PM PDT 24
Finished	Jun 07 07:40:45 PM PDT 24
Peak memory	202996 kb
Host	smart-3bfea6a5-cae9-47a6-bd33-45413959610d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982763149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.2982763149
Directory	/workspace/21.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/21.sram_ctrl_ram_cfg.2778710529
Short name	T484
Test name
Test status
Simulation time	93548292 ps
CPU time	0.8 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 07:35:12 PM PDT 24
Peak memory	202972 kb
Host	smart-7549b68f-e632-4d0e-8a81-99fee9a31c7f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778710529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2778710529
Directory	/workspace/21.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/21.sram_ctrl_regwen.2324010498
Short name	T520
Test name
Test status
Simulation time	4618838341 ps
CPU time	482.11 seconds
Started	Jun 07 07:35:10 PM PDT 24
Finished	Jun 07 07:43:14 PM PDT 24
Peak memory	368516 kb
Host	smart-9462d89c-730f-452b-bce9-bd392af11a6c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324010498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2324010498
Directory	/workspace/21.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/21.sram_ctrl_smoke.916817195
Short name	T303
Test name
Test status
Simulation time	512506011 ps
CPU time	81.35 seconds
Started	Jun 07 07:35:11 PM PDT 24
Finished	Jun 07 07:36:34 PM PDT 24
Peak memory	326896 kb
Host	smart-43560ae6-e2a5-4cb6-9b90-39df9ad61134
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916817195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.916817195
Directory	/workspace/21.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.82087694
Short name	T23
Test name
Test status
Simulation time	9249167799 ps
CPU time	43.29 seconds
Started	Jun 07 07:35:21 PM PDT 24
Finished	Jun 07 07:36:05 PM PDT 24
Peak memory	211264 kb
Host	smart-15ee31ba-9d91-4b14-a030-6f66f6208b57
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=82087694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.82087694
Directory	/workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.sram_ctrl_stress_pipeline.208314289
Short name	T144
Test name
Test status
Simulation time	9627270671 ps
CPU time	250.16 seconds
Started	Jun 07 07:35:10 PM PDT 24
Finished	Jun 07 07:39:23 PM PDT 24
Peak memory	203008 kb
Host	smart-f7effa22-daf2-49cb-861d-6009f8ac0333
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208314289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sram_ctrl_stress_pipeline.208314289
Directory	/workspace/21.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3805766297
Short name	T165
Test name
Test status
Simulation time	213397137 ps
CPU time	55.22 seconds
Started	Jun 07 07:35:09 PM PDT 24
Finished	Jun 07 07:36:07 PM PDT 24
Peak memory	303132 kb
Host	smart-28267818-27a3-4c1f-859d-3dcc9096cc30
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805766297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3805766297
Directory	/workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/22.sram_ctrl_access_during_key_req.1947676209
Short name	T635
Test name
Test status
Simulation time	9833667413 ps
CPU time	1008.23 seconds
Started	Jun 07 07:35:33 PM PDT 24
Finished	Jun 07 07:52:24 PM PDT 24
Peak memory	372744 kb
Host	smart-7c37424e-8dc5-4067-b049-2b9ee2e12b4b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947676209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.1947676209
Directory	/workspace/22.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/22.sram_ctrl_alert_test.740405635
Short name	T804
Test name
Test status
Simulation time	13325364 ps
CPU time	0.67 seconds
Started	Jun 07 07:35:33 PM PDT 24
Finished	Jun 07 07:35:35 PM PDT 24
Peak memory	202524 kb
Host	smart-eadda090-4438-4788-b392-255d41be6198
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740405635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.740405635
Directory	/workspace/22.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.sram_ctrl_bijection.2052975052
Short name	T518
Test name
Test status
Simulation time	3359977038 ps
CPU time	74.76 seconds
Started	Jun 07 07:35:26 PM PDT 24
Finished	Jun 07 07:36:43 PM PDT 24
Peak memory	203004 kb
Host	smart-f0fd6b64-0a15-49af-8741-b0c7179246ac
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052975052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2052975052
Directory	/workspace/22.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/22.sram_ctrl_executable.1786570485
Short name	T669
Test name
Test status
Simulation time	43110027950 ps
CPU time	571.72 seconds
Started	Jun 07 07:35:31 PM PDT 24
Finished	Jun 07 07:45:04 PM PDT 24
Peak memory	335928 kb
Host	smart-f68966c3-ae6f-4552-9886-740fb312f66e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786570485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.1786570485
Directory	/workspace/22.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/22.sram_ctrl_lc_escalation.1609865887
Short name	T528
Test name
Test status
Simulation time	158667437 ps
CPU time	2.22 seconds
Started	Jun 07 07:35:25 PM PDT 24
Finished	Jun 07 07:35:29 PM PDT 24
Peak memory	202816 kb
Host	smart-624a68c0-eeec-4780-bef2-20da4d1d8873
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609865887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.1609865887
Directory	/workspace/22.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/22.sram_ctrl_max_throughput.193036661
Short name	T150
Test name
Test status
Simulation time	103285170 ps
CPU time	36.12 seconds
Started	Jun 07 07:35:27 PM PDT 24
Finished	Jun 07 07:36:05 PM PDT 24
Peak memory	294256 kb
Host	smart-871034e1-b8b7-4412-bd4a-7b2b77843dd4
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193036661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_max_throughput.193036661
Directory	/workspace/22.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3170572890
Short name	T883
Test name
Test status
Simulation time	66022353 ps
CPU time	4.26 seconds
Started	Jun 07 07:35:41 PM PDT 24
Finished	Jun 07 07:35:48 PM PDT 24
Peak memory	211120 kb
Host	smart-3272cb4b-c288-4ebc-97d0-d53b082535e1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170572890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.3170572890
Directory	/workspace/22.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_mem_walk.3487363738
Short name	T406
Test name
Test status
Simulation time	921393981 ps
CPU time	5.92 seconds
Started	Jun 07 07:35:41 PM PDT 24
Finished	Jun 07 07:35:49 PM PDT 24
Peak memory	211036 kb
Host	smart-4b7e7571-5707-411d-bf1a-87769334ca95
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487363738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.3487363738
Directory	/workspace/22.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/22.sram_ctrl_multiple_keys.973989465
Short name	T559
Test name
Test status
Simulation time	15596865035 ps
CPU time	786.23 seconds
Started	Jun 07 07:35:16 PM PDT 24
Finished	Jun 07 07:48:24 PM PDT 24
Peak memory	374724 kb
Host	smart-ce96e580-731e-487b-8292-7265e00142c1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973989465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip le_keys.973989465
Directory	/workspace/22.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access.3557335806
Short name	T557
Test name
Test status
Simulation time	538172664 ps
CPU time	4.71 seconds
Started	Jun 07 07:35:23 PM PDT 24
Finished	Jun 07 07:35:29 PM PDT 24
Peak memory	217096 kb
Host	smart-cf414e4c-c3a7-4b9e-9cac-ba723f50ecd6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557335806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3557335806
Directory	/workspace/22.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3215485879
Short name	T136
Test name
Test status
Simulation time	14987407068 ps
CPU time	289.28 seconds
Started	Jun 07 07:35:25 PM PDT 24
Finished	Jun 07 07:40:17 PM PDT 24
Peak memory	202984 kb
Host	smart-4cb04d73-2617-4ef4-872e-330b0af40bd6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215485879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_partial_access_b2b.3215485879
Directory	/workspace/22.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/22.sram_ctrl_ram_cfg.3542277318
Short name	T459
Test name
Test status
Simulation time	89564271 ps
CPU time	0.75 seconds
Started	Jun 07 07:35:33 PM PDT 24
Finished	Jun 07 07:35:36 PM PDT 24
Peak memory	202900 kb
Host	smart-ae18a009-f344-4573-9731-fbdde94cdf28
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542277318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3542277318
Directory	/workspace/22.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/22.sram_ctrl_regwen.2436194094
Short name	T334
Test name
Test status
Simulation time	10620758926 ps
CPU time	756.05 seconds
Started	Jun 07 07:35:33 PM PDT 24
Finished	Jun 07 07:48:11 PM PDT 24
Peak memory	358456 kb
Host	smart-de5648ca-5803-4a8a-8cdd-743ce95925d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436194094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2436194094
Directory	/workspace/22.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/22.sram_ctrl_smoke.4095835319
Short name	T374
Test name
Test status
Simulation time	155408970 ps
CPU time	6.19 seconds
Started	Jun 07 07:35:17 PM PDT 24
Finished	Jun 07 07:35:25 PM PDT 24
Peak memory	227704 kb
Host	smart-67d4d838-bf51-4bab-8df5-b78385d615bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095835319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.4095835319
Directory	/workspace/22.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all.263692067
Short name	T652
Test name
Test status
Simulation time	54356096599 ps
CPU time	4024.52 seconds
Started	Jun 07 07:35:32 PM PDT 24
Finished	Jun 07 08:42:38 PM PDT 24
Peak memory	376820 kb
Host	smart-8c327f2f-118b-444f-a472-e18ae97ba090
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263692067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.263692067
Directory	/workspace/22.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1334924130
Short name	T42
Test name
Test status
Simulation time	3128546663 ps
CPU time	193.27 seconds
Started	Jun 07 07:35:32 PM PDT 24
Finished	Jun 07 07:38:46 PM PDT 24
Peak memory	380416 kb
Host	smart-753a9048-c899-4041-a722-b41186e6e0cf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1334924130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1334924130
Directory	/workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.sram_ctrl_stress_pipeline.231817249
Short name	T551
Test name
Test status
Simulation time	2532816680 ps
CPU time	243.39 seconds
Started	Jun 07 07:35:25 PM PDT 24
Finished	Jun 07 07:39:30 PM PDT 24
Peak memory	202852 kb
Host	smart-708f9041-739b-4c18-8135-db523c205d71
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231817249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .sram_ctrl_stress_pipeline.231817249
Directory	/workspace/22.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2253174572
Short name	T429
Test name
Test status
Simulation time	1679065089 ps
CPU time	76.46 seconds
Started	Jun 07 07:35:25 PM PDT 24
Finished	Jun 07 07:36:43 PM PDT 24
Peak memory	354208 kb
Host	smart-7696628a-d4ae-4b97-ae08-eb47dd40378d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253174572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2253174572
Directory	/workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1712401155
Short name	T415
Test name
Test status
Simulation time	9129091182 ps
CPU time	519.52 seconds
Started	Jun 07 07:35:34 PM PDT 24
Finished	Jun 07 07:44:16 PM PDT 24
Peak memory	366584 kb
Host	smart-cbbf7108-7957-4958-b1c4-c35f31af6d65
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712401155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.1712401155
Directory	/workspace/23.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/23.sram_ctrl_alert_test.2435382197
Short name	T561
Test name
Test status
Simulation time	15535465 ps
CPU time	0.67 seconds
Started	Jun 07 07:35:50 PM PDT 24
Finished	Jun 07 07:35:53 PM PDT 24
Peak memory	202636 kb
Host	smart-b5c1422a-6a3c-4088-a133-37800a3343ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435382197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2435382197
Directory	/workspace/23.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.sram_ctrl_bijection.3513631869
Short name	T164
Test name
Test status
Simulation time	16192711549 ps
CPU time	62.94 seconds
Started	Jun 07 07:35:32 PM PDT 24
Finished	Jun 07 07:36:36 PM PDT 24
Peak memory	202992 kb
Host	smart-45f78796-2da8-478a-aee1-a07527bcd53b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513631869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .3513631869
Directory	/workspace/23.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/23.sram_ctrl_executable.1872075163
Short name	T579
Test name
Test status
Simulation time	15224246183 ps
CPU time	878.41 seconds
Started	Jun 07 07:35:40 PM PDT 24
Finished	Jun 07 07:50:21 PM PDT 24
Peak memory	374860 kb
Host	smart-8b7ea9d4-75a2-4282-beb7-dd68eca2ff01
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872075163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1872075163
Directory	/workspace/23.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/23.sram_ctrl_lc_escalation.3256917339
Short name	T281
Test name
Test status
Simulation time	915971316 ps
CPU time	5.23 seconds
Started	Jun 07 07:35:35 PM PDT 24
Finished	Jun 07 07:35:42 PM PDT 24
Peak memory	214276 kb
Host	smart-868ca044-aaf4-4fba-a5b2-63277bb5e035
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256917339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.3256917339
Directory	/workspace/23.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/23.sram_ctrl_max_throughput.2056155918
Short name	T61
Test name
Test status
Simulation time	143000743 ps
CPU time	125.29 seconds
Started	Jun 07 07:35:32 PM PDT 24
Finished	Jun 07 07:37:39 PM PDT 24
Peak memory	370324 kb
Host	smart-781f4a25-bab8-4223-829d-5aabb7acdcab
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056155918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.2056155918
Directory	/workspace/23.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3992429502
Short name	T812
Test name
Test status
Simulation time	175398331 ps
CPU time	5.44 seconds
Started	Jun 07 07:35:43 PM PDT 24
Finished	Jun 07 07:35:51 PM PDT 24
Peak memory	210928 kb
Host	smart-c1e53472-e6e2-4e37-97cb-d55283332a85
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992429502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.3992429502
Directory	/workspace/23.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_mem_walk.3558994073
Short name	T749
Test name
Test status
Simulation time	455269373 ps
CPU time	11.21 seconds
Started	Jun 07 07:35:41 PM PDT 24
Finished	Jun 07 07:35:55 PM PDT 24
Peak memory	210972 kb
Host	smart-34a80895-4056-407e-b4e9-39c8d6a8211f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558994073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3558994073
Directory	/workspace/23.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/23.sram_ctrl_multiple_keys.747311870
Short name	T346
Test name
Test status
Simulation time	1440340042 ps
CPU time	430.41 seconds
Started	Jun 07 07:35:34 PM PDT 24
Finished	Jun 07 07:42:46 PM PDT 24
Peak memory	364452 kb
Host	smart-be119626-0806-40cb-b5b7-2a42b81cb4dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747311870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.747311870
Directory	/workspace/23.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access.928402888
Short name	T66
Test name
Test status
Simulation time	397531270 ps
CPU time	7.82 seconds
Started	Jun 07 07:35:34 PM PDT 24
Finished	Jun 07 07:35:44 PM PDT 24
Peak memory	202876 kb
Host	smart-00edb309-2e80-42fe-a2fc-51495df51244
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928402888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s ram_ctrl_partial_access.928402888
Directory	/workspace/23.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2370799356
Short name	T929
Test name
Test status
Simulation time	9737635591 ps
CPU time	256.92 seconds
Started	Jun 07 07:35:34 PM PDT 24
Finished	Jun 07 07:39:54 PM PDT 24
Peak memory	202896 kb
Host	smart-7c9dd053-dfda-48be-9e35-7a28f3190332
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370799356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.2370799356
Directory	/workspace/23.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/23.sram_ctrl_ram_cfg.1695641203
Short name	T381
Test name
Test status
Simulation time	47572351 ps
CPU time	0.8 seconds
Started	Jun 07 07:35:42 PM PDT 24
Finished	Jun 07 07:35:45 PM PDT 24
Peak memory	202924 kb
Host	smart-79a9662b-636e-42ed-b5f8-de30ba06679b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695641203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1695641203
Directory	/workspace/23.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/23.sram_ctrl_regwen.1158134545
Short name	T541
Test name
Test status
Simulation time	10089835078 ps
CPU time	753.61 seconds
Started	Jun 07 07:35:43 PM PDT 24
Finished	Jun 07 07:48:19 PM PDT 24
Peak memory	357912 kb
Host	smart-739ea8bb-7a20-4cd2-b3bd-0eb9c4ac71e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158134545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1158134545
Directory	/workspace/23.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/23.sram_ctrl_smoke.3145936950
Short name	T325
Test name
Test status
Simulation time	55085846 ps
CPU time	1.53 seconds
Started	Jun 07 07:35:40 PM PDT 24
Finished	Jun 07 07:35:43 PM PDT 24
Peak memory	202936 kb
Host	smart-86f2d73f-cc3d-4ef7-9a9a-bc6ac9f18b3c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145936950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3145936950
Directory	/workspace/23.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all.1784316985
Short name	T134
Test name
Test status
Simulation time	105338819394 ps
CPU time	1027.04 seconds
Started	Jun 07 07:35:43 PM PDT 24
Finished	Jun 07 07:52:53 PM PDT 24
Peak memory	374452 kb
Host	smart-72380e50-61ce-4d47-99ec-823f9c5067dc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784316985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1784316985
Directory	/workspace/23.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3221289833
Short name	T271
Test name
Test status
Simulation time	1071968487 ps
CPU time	90.52 seconds
Started	Jun 07 07:35:43 PM PDT 24
Finished	Jun 07 07:37:16 PM PDT 24
Peak memory	307856 kb
Host	smart-3d8f0ccc-7d39-4c94-ae71-b507d21c0e04
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3221289833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3221289833
Directory	/workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.sram_ctrl_stress_pipeline.501553969
Short name	T672
Test name
Test status
Simulation time	5248163508 ps
CPU time	269.11 seconds
Started	Jun 07 07:35:32 PM PDT 24
Finished	Jun 07 07:40:03 PM PDT 24
Peak memory	203012 kb
Host	smart-68ca410a-7df6-4250-8d73-3379b62eaa6b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501553969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sram_ctrl_stress_pipeline.501553969
Directory	/workspace/23.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3675089267
Short name	T659
Test name
Test status
Simulation time	250448915 ps
CPU time	9.85 seconds
Started	Jun 07 07:35:39 PM PDT 24
Finished	Jun 07 07:35:50 PM PDT 24
Peak memory	244612 kb
Host	smart-dde13e37-e6b5-4604-aa2a-cb4950c0720c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675089267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3675089267
Directory	/workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/24.sram_ctrl_access_during_key_req.4123103939
Short name	T880
Test name
Test status
Simulation time	8389321027 ps
CPU time	385.95 seconds
Started	Jun 07 07:35:58 PM PDT 24
Finished	Jun 07 07:42:26 PM PDT 24
Peak memory	366488 kb
Host	smart-d5907cde-22ac-41bd-b616-683a67a1e11a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123103939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.4123103939
Directory	/workspace/24.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/24.sram_ctrl_alert_test.1058855552
Short name	T609
Test name
Test status
Simulation time	63984643 ps
CPU time	0.65 seconds
Started	Jun 07 07:36:04 PM PDT 24
Finished	Jun 07 07:36:06 PM PDT 24
Peak memory	202124 kb
Host	smart-4b2aefd5-1959-4869-9820-3c732d0e068f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058855552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1058855552
Directory	/workspace/24.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.sram_ctrl_bijection.2615953577
Short name	T731
Test name
Test status
Simulation time	851725604 ps
CPU time	57.93 seconds
Started	Jun 07 07:35:49 PM PDT 24
Finished	Jun 07 07:36:49 PM PDT 24
Peak memory	202948 kb
Host	smart-44a8d213-4c22-4a06-adeb-18a6a4a69430
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615953577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .2615953577
Directory	/workspace/24.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/24.sram_ctrl_executable.1427301928
Short name	T264
Test name
Test status
Simulation time	64875940979 ps
CPU time	1449.84 seconds
Started	Jun 07 07:35:56 PM PDT 24
Finished	Jun 07 08:00:08 PM PDT 24
Peak memory	375460 kb
Host	smart-0795ea6b-e2c7-4b7f-8fa7-15c683c77e61
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427301928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.1427301928
Directory	/workspace/24.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/24.sram_ctrl_lc_escalation.930300779
Short name	T643
Test name
Test status
Simulation time	719995714 ps
CPU time	9.43 seconds
Started	Jun 07 07:35:57 PM PDT 24
Finished	Jun 07 07:36:09 PM PDT 24
Peak memory	211144 kb
Host	smart-a6ba03c0-e835-48f7-bc34-63869416e119
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930300779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esc alation.930300779
Directory	/workspace/24.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/24.sram_ctrl_max_throughput.1687856873
Short name	T657
Test name
Test status
Simulation time	168820512 ps
CPU time	36 seconds
Started	Jun 07 07:35:49 PM PDT 24
Finished	Jun 07 07:36:27 PM PDT 24
Peak memory	284704 kb
Host	smart-95cda4c3-b1c5-4d1e-bb17-ebb03daa851d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687856873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.1687856873
Directory	/workspace/24.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_partial_access.2665816466
Short name	T85
Test name
Test status
Simulation time	63778268 ps
CPU time	3.08 seconds
Started	Jun 07 07:36:02 PM PDT 24
Finished	Jun 07 07:36:07 PM PDT 24
Peak memory	211128 kb
Host	smart-08675b54-4fd2-425d-be56-28a04563eaf4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665816466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.2665816466
Directory	/workspace/24.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_mem_walk.1484780455
Short name	T656
Test name
Test status
Simulation time	1570857521 ps
CPU time	10.1 seconds
Started	Jun 07 07:35:55 PM PDT 24
Finished	Jun 07 07:36:07 PM PDT 24
Peak memory	211064 kb
Host	smart-4e77a3d8-81c3-47cc-8323-5c637d63380c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484780455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.1484780455
Directory	/workspace/24.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/24.sram_ctrl_multiple_keys.2927060157
Short name	T784
Test name
Test status
Simulation time	26063894079 ps
CPU time	1764.3 seconds
Started	Jun 07 07:35:50 PM PDT 24
Finished	Jun 07 08:05:17 PM PDT 24
Peak memory	375744 kb
Host	smart-cf45f115-baaf-4c45-9715-0ae63bee1dc8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927060157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.2927060157
Directory	/workspace/24.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access.1196578462
Short name	T884
Test name
Test status
Simulation time	3350730254 ps
CPU time	18.82 seconds
Started	Jun 07 07:35:51 PM PDT 24
Finished	Jun 07 07:36:12 PM PDT 24
Peak memory	202984 kb
Host	smart-ba6cb36c-19fc-4803-acc8-0f0f6655366f
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196578462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1196578462
Directory	/workspace/24.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3914033020
Short name	T615
Test name
Test status
Simulation time	73517254054 ps
CPU time	327 seconds
Started	Jun 07 07:35:49 PM PDT 24
Finished	Jun 07 07:41:19 PM PDT 24
Peak memory	202964 kb
Host	smart-12e0eaae-d6ce-44e2-af2a-09b35040ed4e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914033020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3914033020
Directory	/workspace/24.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/24.sram_ctrl_ram_cfg.2838020395
Short name	T28
Test name
Test status
Simulation time	28778730 ps
CPU time	0.79 seconds
Started	Jun 07 07:35:56 PM PDT 24
Finished	Jun 07 07:35:59 PM PDT 24
Peak memory	202916 kb
Host	smart-019b213d-ae20-47ee-9518-0330558d41e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838020395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2838020395
Directory	/workspace/24.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/24.sram_ctrl_regwen.2516630999
Short name	T693
Test name
Test status
Simulation time	2084633026 ps
CPU time	1060.74 seconds
Started	Jun 07 07:35:58 PM PDT 24
Finished	Jun 07 07:53:41 PM PDT 24
Peak memory	374748 kb
Host	smart-323394df-6ee4-4f3f-9fbe-1e4cbcfc9863
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516630999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2516630999
Directory	/workspace/24.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/24.sram_ctrl_smoke.1266827477
Short name	T285
Test name
Test status
Simulation time	143546421 ps
CPU time	150.7 seconds
Started	Jun 07 07:35:49 PM PDT 24
Finished	Jun 07 07:38:23 PM PDT 24
Peak memory	367048 kb
Host	smart-3481abfd-fa71-4d24-b6ed-761f14686196
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266827477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1266827477
Directory	/workspace/24.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_all.3205740232
Short name	T593
Test name
Test status
Simulation time	13021013395 ps
CPU time	3689.83 seconds
Started	Jun 07 07:36:04 PM PDT 24
Finished	Jun 07 08:37:36 PM PDT 24
Peak memory	377764 kb
Host	smart-199a44f1-46a7-4484-96da-829122a6bf3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205740232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.3205740232
Directory	/workspace/24.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1442717661
Short name	T570
Test name
Test status
Simulation time	11000222959 ps
CPU time	274.63 seconds
Started	Jun 07 07:35:51 PM PDT 24
Finished	Jun 07 07:40:28 PM PDT 24
Peak memory	202992 kb
Host	smart-d2137170-58c3-451b-8a27-896ae32847c8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442717661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_stress_pipeline.1442717661
Directory	/workspace/24.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1256438968
Short name	T494
Test name
Test status
Simulation time	218155905 ps
CPU time	7.65 seconds
Started	Jun 07 07:35:55 PM PDT 24
Finished	Jun 07 07:36:04 PM PDT 24
Peak memory	235756 kb
Host	smart-08460a6e-5c47-4ca2-a7eb-3979ba00de95
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256438968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1256438968
Directory	/workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2128853061
Short name	T385
Test name
Test status
Simulation time	2615031314 ps
CPU time	763.39 seconds
Started	Jun 07 07:36:13 PM PDT 24
Finished	Jun 07 07:48:58 PM PDT 24
Peak memory	374408 kb
Host	smart-95278862-8dc1-4ee9-bb27-1b71a4ed996c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128853061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2128853061
Directory	/workspace/25.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/25.sram_ctrl_alert_test.2751239630
Short name	T465
Test name
Test status
Simulation time	42947402 ps
CPU time	0.65 seconds
Started	Jun 07 07:36:19 PM PDT 24
Finished	Jun 07 07:36:22 PM PDT 24
Peak memory	202624 kb
Host	smart-68f108d4-1ff3-4489-868e-545070be215e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751239630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2751239630
Directory	/workspace/25.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.sram_ctrl_bijection.1233524259
Short name	T517
Test name
Test status
Simulation time	1013610629 ps
CPU time	49.46 seconds
Started	Jun 07 07:36:06 PM PDT 24
Finished	Jun 07 07:36:57 PM PDT 24
Peak memory	202880 kb
Host	smart-de37a2bb-3911-44a5-a35a-ed51a887c582
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233524259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .1233524259
Directory	/workspace/25.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/25.sram_ctrl_executable.4001679394
Short name	T741
Test name
Test status
Simulation time	48458539072 ps
CPU time	758.14 seconds
Started	Jun 07 07:36:13 PM PDT 24
Finished	Jun 07 07:48:53 PM PDT 24
Peak memory	375400 kb
Host	smart-25c0d928-c3a3-4355-b67e-e0b91d7ff0dc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001679394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.4001679394
Directory	/workspace/25.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/25.sram_ctrl_lc_escalation.3849542590
Short name	T183
Test name
Test status
Simulation time	220004923 ps
CPU time	2.83 seconds
Started	Jun 07 07:36:13 PM PDT 24
Finished	Jun 07 07:36:18 PM PDT 24
Peak memory	211120 kb
Host	smart-9bef94a2-7a53-48b6-b532-b4ae524d4ac4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849542590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.3849542590
Directory	/workspace/25.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/25.sram_ctrl_max_throughput.2922032782
Short name	T471
Test name
Test status
Simulation time	104276173 ps
CPU time	53.94 seconds
Started	Jun 07 07:36:13 PM PDT 24
Finished	Jun 07 07:37:09 PM PDT 24
Peak memory	306140 kb
Host	smart-2217a15e-37c2-4d98-80ac-56c06fe21ef9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922032782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.2922032782
Directory	/workspace/25.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_partial_access.579574886
Short name	T2
Test name
Test status
Simulation time	87197169 ps
CPU time	3.24 seconds
Started	Jun 07 07:36:21 PM PDT 24
Finished	Jun 07 07:36:27 PM PDT 24
Peak memory	211084 kb
Host	smart-f2bbcf59-5354-44b9-af98-fc4db188709b
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579574886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_mem_partial_access.579574886
Directory	/workspace/25.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_mem_walk.1397329346
Short name	T315
Test name
Test status
Simulation time	1755498023 ps
CPU time	10.54 seconds
Started	Jun 07 07:36:23 PM PDT 24
Finished	Jun 07 07:36:36 PM PDT 24
Peak memory	211064 kb
Host	smart-465f593a-c63c-4fc9-8e7b-30b60658ceda
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397329346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.1397329346
Directory	/workspace/25.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/25.sram_ctrl_multiple_keys.3331170856
Short name	T818
Test name
Test status
Simulation time	38446209692 ps
CPU time	1534.13 seconds
Started	Jun 07 07:36:04 PM PDT 24
Finished	Jun 07 08:01:40 PM PDT 24
Peak memory	372340 kb
Host	smart-5783d4da-7ce6-4bbd-986e-232ed67b4784
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331170856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3331170856
Directory	/workspace/25.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access.1062814553
Short name	T268
Test name
Test status
Simulation time	205360009 ps
CPU time	2.35 seconds
Started	Jun 07 07:36:13 PM PDT 24
Finished	Jun 07 07:36:17 PM PDT 24
Peak memory	207124 kb
Host	smart-2d9d8740-76b5-4e99-aca1-29efa12edcab
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062814553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.1062814553
Directory	/workspace/25.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3338564522
Short name	T758
Test name
Test status
Simulation time	14468338298 ps
CPU time	272.74 seconds
Started	Jun 07 07:36:12 PM PDT 24
Finished	Jun 07 07:40:46 PM PDT 24
Peak memory	202968 kb
Host	smart-ce5f3ead-ec66-4d78-8906-bac429f2d7eb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338564522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.3338564522
Directory	/workspace/25.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/25.sram_ctrl_ram_cfg.2589956221
Short name	T298
Test name
Test status
Simulation time	27392003 ps
CPU time	0.75 seconds
Started	Jun 07 07:36:22 PM PDT 24
Finished	Jun 07 07:36:25 PM PDT 24
Peak memory	202876 kb
Host	smart-784bb5b2-0840-44cd-bb3a-8fedb701d361
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589956221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2589956221
Directory	/workspace/25.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/25.sram_ctrl_regwen.1248362945
Short name	T286
Test name
Test status
Simulation time	21112016977 ps
CPU time	2164.1 seconds
Started	Jun 07 07:36:22 PM PDT 24
Finished	Jun 07 08:12:29 PM PDT 24
Peak memory	376220 kb
Host	smart-8bf2159c-e6ef-4790-a5f4-4f3d53c53248
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248362945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1248362945
Directory	/workspace/25.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/25.sram_ctrl_smoke.2039636974
Short name	T677
Test name
Test status
Simulation time	660823096 ps
CPU time	114.01 seconds
Started	Jun 07 07:36:05 PM PDT 24
Finished	Jun 07 07:38:01 PM PDT 24
Peak memory	354192 kb
Host	smart-3bb0194d-7df0-407a-8382-31258dfc1262
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039636974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2039636974
Directory	/workspace/25.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_all.2809938096
Short name	T738
Test name
Test status
Simulation time	42787820055 ps
CPU time	3917.38 seconds
Started	Jun 07 07:36:21 PM PDT 24
Finished	Jun 07 08:41:41 PM PDT 24
Peak memory	376756 kb
Host	smart-48ae9fa3-b172-425f-9e2f-681fa93cf749
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809938096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.sram_ctrl_stress_all.2809938096
Directory	/workspace/25.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3604721993
Short name	T402
Test name
Test status
Simulation time	3693407614 ps
CPU time	364.32 seconds
Started	Jun 07 07:36:10 PM PDT 24
Finished	Jun 07 07:42:16 PM PDT 24
Peak memory	202800 kb
Host	smart-b323a3fc-d56e-4614-bc1f-43be7e0699a8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604721993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.3604721993
Directory	/workspace/25.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.4189419608
Short name	T316
Test name
Test status
Simulation time	587157532 ps
CPU time	143.43 seconds
Started	Jun 07 07:36:12 PM PDT 24
Finished	Jun 07 07:38:37 PM PDT 24
Peak memory	371448 kb
Host	smart-90eed8a2-0cde-413d-b47a-a2e68faa6c1f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189419608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.4189419608
Directory	/workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/26.sram_ctrl_access_during_key_req.223821763
Short name	T601
Test name
Test status
Simulation time	18061743461 ps
CPU time	940.47 seconds
Started	Jun 07 07:36:30 PM PDT 24
Finished	Jun 07 07:52:12 PM PDT 24
Peak memory	372700 kb
Host	smart-26e89b07-c3df-428c-a462-4011aa4eb7aa
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223821763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 26.sram_ctrl_access_during_key_req.223821763
Directory	/workspace/26.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/26.sram_ctrl_alert_test.170738018
Short name	T301
Test name
Test status
Simulation time	18522817 ps
CPU time	0.7 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:31 PM PDT 24
Peak memory	202612 kb
Host	smart-ee8a9b8b-c574-4da7-b821-046570bb8ae5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170738018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.170738018
Directory	/workspace/26.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.sram_ctrl_bijection.712166081
Short name	T571
Test name
Test status
Simulation time	903311026 ps
CPU time	19.92 seconds
Started	Jun 07 07:36:21 PM PDT 24
Finished	Jun 07 07:36:43 PM PDT 24
Peak memory	202980 kb
Host	smart-56b658e9-ab42-445f-aeab-f54031014745
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712166081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection. 712166081
Directory	/workspace/26.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/26.sram_ctrl_executable.990155800
Short name	T369
Test name
Test status
Simulation time	5047581285 ps
CPU time	253.29 seconds
Started	Jun 07 07:36:28 PM PDT 24
Finished	Jun 07 07:40:43 PM PDT 24
Peak memory	351780 kb
Host	smart-7efe8271-0b26-417f-b6b8-ecb35e84745f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990155800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.990155800
Directory	/workspace/26.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/26.sram_ctrl_lc_escalation.20664642
Short name	T603
Test name
Test status
Simulation time	296318747 ps
CPU time	4.41 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:35 PM PDT 24
Peak memory	202948 kb
Host	smart-c8dac97f-993b-4a24-a22c-995b0ba68264
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20664642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esca lation.20664642
Directory	/workspace/26.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/26.sram_ctrl_max_throughput.1620495620
Short name	T311
Test name
Test status
Simulation time	159905522 ps
CPU time	21.04 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:52 PM PDT 24
Peak memory	277200 kb
Host	smart-db5afe73-0ca0-4105-a937-2fdebc7f9ce8
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620495620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.1620495620
Directory	/workspace/26.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2841971669
Short name	T404
Test name
Test status
Simulation time	45543844 ps
CPU time	2.67 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:33 PM PDT 24
Peak memory	211148 kb
Host	smart-9da75dd1-3fe1-4c13-86c8-4b3e2e67e4bc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841971669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.2841971669
Directory	/workspace/26.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_mem_walk.2490476358
Short name	T896
Test name
Test status
Simulation time	290175276 ps
CPU time	5.09 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:35 PM PDT 24
Peak memory	211024 kb
Host	smart-2ad5e0a3-eef9-4be9-900d-07cece817311
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490476358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.2490476358
Directory	/workspace/26.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/26.sram_ctrl_multiple_keys.4219410729
Short name	T43
Test name
Test status
Simulation time	28967226786 ps
CPU time	507.8 seconds
Started	Jun 07 07:36:18 PM PDT 24
Finished	Jun 07 07:44:48 PM PDT 24
Peak memory	373876 kb
Host	smart-bd5d25c6-d6cd-49af-bdb4-2d696af77494
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219410729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.4219410729
Directory	/workspace/26.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access.4035498204
Short name	T487
Test name
Test status
Simulation time	949485551 ps
CPU time	19.59 seconds
Started	Jun 07 07:36:19 PM PDT 24
Finished	Jun 07 07:36:42 PM PDT 24
Peak memory	202864 kb
Host	smart-e70ad33b-f6f6-467a-97d3-4823edf40f0e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035498204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.4035498204
Directory	/workspace/26.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2969893449
Short name	T63
Test name
Test status
Simulation time	5107473946 ps
CPU time	388.49 seconds
Started	Jun 07 07:36:19 PM PDT 24
Finished	Jun 07 07:42:50 PM PDT 24
Peak memory	203000 kb
Host	smart-9079a7d4-b532-4431-b103-2f02b9c1c77b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969893449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.2969893449
Directory	/workspace/26.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/26.sram_ctrl_ram_cfg.2987095824
Short name	T380
Test name
Test status
Simulation time	80884149 ps
CPU time	0.81 seconds
Started	Jun 07 07:36:29 PM PDT 24
Finished	Jun 07 07:36:32 PM PDT 24
Peak memory	202928 kb
Host	smart-2699211c-5e17-4f11-9f23-4d165c0472f6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987095824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2987095824
Directory	/workspace/26.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/26.sram_ctrl_regwen.2016460809
Short name	T221
Test name
Test status
Simulation time	6052760436 ps
CPU time	62.28 seconds
Started	Jun 07 07:36:28 PM PDT 24
Finished	Jun 07 07:37:32 PM PDT 24
Peak memory	285408 kb
Host	smart-6795e635-cf74-4c8b-81d6-3f1056456ccc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016460809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2016460809
Directory	/workspace/26.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/26.sram_ctrl_smoke.2417691254
Short name	T139
Test name
Test status
Simulation time	880112021 ps
CPU time	83.34 seconds
Started	Jun 07 07:36:20 PM PDT 24
Finished	Jun 07 07:37:47 PM PDT 24
Peak memory	344028 kb
Host	smart-2bcad0a0-37be-4324-adac-6d702844d937
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417691254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2417691254
Directory	/workspace/26.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all.1618961188
Short name	T544
Test name
Test status
Simulation time	176629843914 ps
CPU time	3465.91 seconds
Started	Jun 07 07:36:30 PM PDT 24
Finished	Jun 07 08:34:18 PM PDT 24
Peak memory	376076 kb
Host	smart-4c871ab4-0d21-44d0-9dd0-5c4cf868cc40
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618961188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.1618961188
Directory	/workspace/26.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.372656611
Short name	T36
Test name
Test status
Simulation time	998381190 ps
CPU time	26.36 seconds
Started	Jun 07 07:36:28 PM PDT 24
Finished	Jun 07 07:36:55 PM PDT 24
Peak memory	212248 kb
Host	smart-b08d0b99-cf16-4273-90cb-3f0383587555
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=372656611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.372656611
Directory	/workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1298246674
Short name	T396
Test name
Test status
Simulation time	17872391350 ps
CPU time	336.28 seconds
Started	Jun 07 07:36:20 PM PDT 24
Finished	Jun 07 07:42:00 PM PDT 24
Peak memory	202960 kb
Host	smart-4a923b21-1127-4717-981c-8443f163f755
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298246674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.1298246674
Directory	/workspace/26.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.462588232
Short name	T695
Test name
Test status
Simulation time	217826545 ps
CPU time	6.23 seconds
Started	Jun 07 07:36:28 PM PDT 24
Finished	Jun 07 07:36:35 PM PDT 24
Peak memory	235680 kb
Host	smart-0c3da8ba-1d52-478b-88ae-747c685b5e6c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462588232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.462588232
Directory	/workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/27.sram_ctrl_access_during_key_req.870011307
Short name	T874
Test name
Test status
Simulation time	2495869939 ps
CPU time	233.23 seconds
Started	Jun 07 07:36:37 PM PDT 24
Finished	Jun 07 07:40:32 PM PDT 24
Peak memory	342028 kb
Host	smart-f08cd6e0-900b-42f3-a45d-3d274720ce7e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870011307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 27.sram_ctrl_access_during_key_req.870011307
Directory	/workspace/27.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/27.sram_ctrl_alert_test.3265012210
Short name	T379
Test name
Test status
Simulation time	12753409 ps
CPU time	0.68 seconds
Started	Jun 07 07:36:42 PM PDT 24
Finished	Jun 07 07:36:44 PM PDT 24
Peak memory	202640 kb
Host	smart-b08268a7-d222-4667-b2c4-5bdba4af346c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265012210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3265012210
Directory	/workspace/27.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.sram_ctrl_bijection.1276113513
Short name	T219
Test name
Test status
Simulation time	51404405154 ps
CPU time	83.77 seconds
Started	Jun 07 07:36:37 PM PDT 24
Finished	Jun 07 07:38:02 PM PDT 24
Peak memory	202988 kb
Host	smart-f70a1818-1796-4fc0-9222-61dee24ea77c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276113513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .1276113513
Directory	/workspace/27.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/27.sram_ctrl_executable.3916263647
Short name	T704
Test name
Test status
Simulation time	30116682306 ps
CPU time	795.59 seconds
Started	Jun 07 07:36:42 PM PDT 24
Finished	Jun 07 07:49:59 PM PDT 24
Peak memory	375448 kb
Host	smart-d8f880d1-ece8-4be9-b80e-d2496293e964
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916263647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.3916263647
Directory	/workspace/27.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/27.sram_ctrl_lc_escalation.2268019450
Short name	T313
Test name
Test status
Simulation time	883000441 ps
CPU time	8.56 seconds
Started	Jun 07 07:36:34 PM PDT 24
Finished	Jun 07 07:36:44 PM PDT 24
Peak memory	202968 kb
Host	smart-aec5971d-8c0c-4ee6-bfe5-b057c5ea0299
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268019450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.2268019450
Directory	/workspace/27.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/27.sram_ctrl_max_throughput.1275969759
Short name	T817
Test name
Test status
Simulation time	358614740 ps
CPU time	42.43 seconds
Started	Jun 07 07:36:38 PM PDT 24
Finished	Jun 07 07:37:22 PM PDT 24
Peak memory	289564 kb
Host	smart-7d5b29ca-aea5-44ee-a265-47ac1241ca8a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275969759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1275969759
Directory	/workspace/27.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1120639721
Short name	T340
Test name
Test status
Simulation time	380282510 ps
CPU time	3.53 seconds
Started	Jun 07 07:36:42 PM PDT 24
Finished	Jun 07 07:36:46 PM PDT 24
Peak memory	211052 kb
Host	smart-5d2fe8c0-9c97-46f8-a815-c101df359dbf
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120639721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.1120639721
Directory	/workspace/27.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_mem_walk.1869571878
Short name	T199
Test name
Test status
Simulation time	675307228 ps
CPU time	11.32 seconds
Started	Jun 07 07:36:41 PM PDT 24
Finished	Jun 07 07:36:54 PM PDT 24
Peak memory	202920 kb
Host	smart-c28cfc63-d9d6-4d25-9e0c-b83ce8fd1ed6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869571878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.1869571878
Directory	/workspace/27.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/27.sram_ctrl_multiple_keys.3398943339
Short name	T624
Test name
Test status
Simulation time	3663875025 ps
CPU time	473.87 seconds
Started	Jun 07 07:36:37 PM PDT 24
Finished	Jun 07 07:44:32 PM PDT 24
Peak memory	368612 kb
Host	smart-df316247-947d-40ea-a652-1ddc0ae97149
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398943339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.3398943339
Directory	/workspace/27.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access.1811936079
Short name	T177
Test name
Test status
Simulation time	45553798 ps
CPU time	1.03 seconds
Started	Jun 07 07:36:36 PM PDT 24
Finished	Jun 07 07:36:38 PM PDT 24
Peak memory	202712 kb
Host	smart-0fd570c0-ef94-43b5-b2a3-d1ff841bb338
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811936079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.1811936079
Directory	/workspace/27.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2846396068
Short name	T527
Test name
Test status
Simulation time	172732183687 ps
CPU time	537.83 seconds
Started	Jun 07 07:36:35 PM PDT 24
Finished	Jun 07 07:45:34 PM PDT 24
Peak memory	202984 kb
Host	smart-6d01cfa9-b363-4f12-80ca-4a7aa20845f1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846396068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.2846396068
Directory	/workspace/27.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/27.sram_ctrl_ram_cfg.472619462
Short name	T27
Test name
Test status
Simulation time	99012813 ps
CPU time	0.78 seconds
Started	Jun 07 07:36:43 PM PDT 24
Finished	Jun 07 07:36:45 PM PDT 24
Peak memory	202876 kb
Host	smart-300d4d8a-f120-4eb5-93dc-5e7c09e7d40c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472619462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.472619462
Directory	/workspace/27.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/27.sram_ctrl_regwen.3647170169
Short name	T903
Test name
Test status
Simulation time	7122775275 ps
CPU time	533.11 seconds
Started	Jun 07 07:36:44 PM PDT 24
Finished	Jun 07 07:45:38 PM PDT 24
Peak memory	355276 kb
Host	smart-18024b4a-dfc9-44f7-a150-fc2cddf8cea0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647170169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3647170169
Directory	/workspace/27.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/27.sram_ctrl_smoke.819115287
Short name	T523
Test name
Test status
Simulation time	207039182 ps
CPU time	12.03 seconds
Started	Jun 07 07:36:36 PM PDT 24
Finished	Jun 07 07:36:49 PM PDT 24
Peak memory	202948 kb
Host	smart-062b1d8d-df37-4fb2-ab3e-d20c21f127e3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819115287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.819115287
Directory	/workspace/27.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_all.3098722116
Short name	T799
Test name
Test status
Simulation time	8968893955 ps
CPU time	2845.46 seconds
Started	Jun 07 07:36:41 PM PDT 24
Finished	Jun 07 08:24:08 PM PDT 24
Peak memory	375852 kb
Host	smart-c0eeffc4-afd7-42f0-bff0-1f3b3615952b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098722116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.3098722116
Directory	/workspace/27.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.sram_ctrl_stress_pipeline.741096764
Short name	T99
Test name
Test status
Simulation time	2256477078 ps
CPU time	206.65 seconds
Started	Jun 07 07:36:37 PM PDT 24
Finished	Jun 07 07:40:05 PM PDT 24
Peak memory	202964 kb
Host	smart-24b57012-12b0-4196-a283-832d5623e342
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741096764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_stress_pipeline.741096764
Directory	/workspace/27.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2567898572
Short name	T900
Test name
Test status
Simulation time	132345956 ps
CPU time	93.85 seconds
Started	Jun 07 07:36:36 PM PDT 24
Finished	Jun 07 07:38:11 PM PDT 24
Peak memory	340912 kb
Host	smart-e7a428e3-e916-4abc-b925-cb9497bb7a58
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567898572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2567898572
Directory	/workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/28.sram_ctrl_access_during_key_req.4117186007
Short name	T549
Test name
Test status
Simulation time	2806530549 ps
CPU time	635.2 seconds
Started	Jun 07 07:36:53 PM PDT 24
Finished	Jun 07 07:47:30 PM PDT 24
Peak memory	366668 kb
Host	smart-3a1fd96e-195f-4fdb-a2dd-6c43f1e6c281
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117186007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.4117186007
Directory	/workspace/28.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/28.sram_ctrl_alert_test.602398157
Short name	T633
Test name
Test status
Simulation time	14398778 ps
CPU time	0.61 seconds
Started	Jun 07 07:36:56 PM PDT 24
Finished	Jun 07 07:36:57 PM PDT 24
Peak memory	202592 kb
Host	smart-418ca1c5-8b4e-4d9d-b300-182d6c58d4b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602398157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.602398157
Directory	/workspace/28.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.sram_ctrl_bijection.2609039566
Short name	T846
Test name
Test status
Simulation time	17286166772 ps
CPU time	71.9 seconds
Started	Jun 07 07:36:51 PM PDT 24
Finished	Jun 07 07:38:05 PM PDT 24
Peak memory	202964 kb
Host	smart-fe58d721-dfba-4c48-b9f4-f93da3b8a7e2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609039566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .2609039566
Directory	/workspace/28.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/28.sram_ctrl_executable.1723845009
Short name	T604
Test name
Test status
Simulation time	2587577295 ps
CPU time	751.56 seconds
Started	Jun 07 07:36:54 PM PDT 24
Finished	Jun 07 07:49:27 PM PDT 24
Peak memory	374196 kb
Host	smart-c8acb8c2-b5b7-4e63-bc4f-5c4f5c94f390
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723845009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1723845009
Directory	/workspace/28.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/28.sram_ctrl_lc_escalation.3242062553
Short name	T280
Test name
Test status
Simulation time	3912386835 ps
CPU time	5.94 seconds
Started	Jun 07 07:36:50 PM PDT 24
Finished	Jun 07 07:36:57 PM PDT 24
Peak memory	202948 kb
Host	smart-ba642dfa-4586-44fe-9013-09cb4ac0f16a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242062553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3242062553
Directory	/workspace/28.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/28.sram_ctrl_max_throughput.2589620642
Short name	T797
Test name
Test status
Simulation time	116422984 ps
CPU time	8.95 seconds
Started	Jun 07 07:36:52 PM PDT 24
Finished	Jun 07 07:37:02 PM PDT 24
Peak memory	238504 kb
Host	smart-e27925cd-dc67-4004-b5a6-3c939571e3a6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589620642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.2589620642
Directory	/workspace/28.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3372385549
Short name	T684
Test name
Test status
Simulation time	833501314 ps
CPU time	3.29 seconds
Started	Jun 07 07:36:58 PM PDT 24
Finished	Jun 07 07:37:02 PM PDT 24
Peak memory	211156 kb
Host	smart-18abd251-610d-43ac-957b-5c54a362209a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372385549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.3372385549
Directory	/workspace/28.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_mem_walk.2041215398
Short name	T424
Test name
Test status
Simulation time	366211358 ps
CPU time	10.98 seconds
Started	Jun 07 07:36:58 PM PDT 24
Finished	Jun 07 07:37:11 PM PDT 24
Peak memory	211100 kb
Host	smart-2f51339a-1d0f-43c1-afdb-e20aa8bcc61e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041215398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2041215398
Directory	/workspace/28.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/28.sram_ctrl_multiple_keys.2441252384
Short name	T706
Test name
Test status
Simulation time	1701987091 ps
CPU time	504.38 seconds
Started	Jun 07 07:36:52 PM PDT 24
Finished	Jun 07 07:45:18 PM PDT 24
Peak memory	343100 kb
Host	smart-272286cc-e024-4336-83cb-1785c55271cf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441252384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.2441252384
Directory	/workspace/28.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access.3031096488
Short name	T922
Test name
Test status
Simulation time	5104930522 ps
CPU time	84.85 seconds
Started	Jun 07 07:36:49 PM PDT 24
Finished	Jun 07 07:38:14 PM PDT 24
Peak memory	324564 kb
Host	smart-23a9f6f8-92b9-4448-af67-f5305b2713bd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031096488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28. sram_ctrl_partial_access.3031096488
Directory	/workspace/28.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1818249197
Short name	T414
Test name
Test status
Simulation time	30944970480 ps
CPU time	319.93 seconds
Started	Jun 07 07:36:51 PM PDT 24
Finished	Jun 07 07:42:13 PM PDT 24
Peak memory	202960 kb
Host	smart-25c5e30f-c9b0-4cff-b3bb-9a1af56e2f84
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818249197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.1818249197
Directory	/workspace/28.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/28.sram_ctrl_ram_cfg.4258510216
Short name	T864
Test name
Test status
Simulation time	197148166 ps
CPU time	0.78 seconds
Started	Jun 07 07:36:52 PM PDT 24
Finished	Jun 07 07:36:54 PM PDT 24
Peak memory	202796 kb
Host	smart-ff0cf590-0361-43f0-b842-ae04f83819a3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258510216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.4258510216
Directory	/workspace/28.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/28.sram_ctrl_regwen.1989869764
Short name	T244
Test name
Test status
Simulation time	2731414354 ps
CPU time	1113.34 seconds
Started	Jun 07 07:36:50 PM PDT 24
Finished	Jun 07 07:55:24 PM PDT 24
Peak memory	370988 kb
Host	smart-dcb36b4e-a91f-47db-ae07-4dc39e7d7c5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989869764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1989869764
Directory	/workspace/28.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/28.sram_ctrl_smoke.2783638810
Short name	T599
Test name
Test status
Simulation time	1802627144 ps
CPU time	47.13 seconds
Started	Jun 07 07:36:42 PM PDT 24
Finished	Jun 07 07:37:30 PM PDT 24
Peak memory	316352 kb
Host	smart-92be4311-24e2-401b-9aea-10ae00b4ec5b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783638810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2783638810
Directory	/workspace/28.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all.4013943332
Short name	T257
Test name
Test status
Simulation time	15877845173 ps
CPU time	969.39 seconds
Started	Jun 07 07:37:00 PM PDT 24
Finished	Jun 07 07:53:10 PM PDT 24
Peak memory	383900 kb
Host	smart-a3ddfc90-d999-4dc5-a16c-dcab02f76af5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013943332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.4013943332
Directory	/workspace/28.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.92776871
Short name	T575
Test name
Test status
Simulation time	935123503 ps
CPU time	16.49 seconds
Started	Jun 07 07:36:58 PM PDT 24
Finished	Jun 07 07:37:16 PM PDT 24
Peak memory	219252 kb
Host	smart-d8523acf-3145-4cb8-aa97-e5beb2dfc426
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=92776871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.92776871
Directory	/workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.sram_ctrl_stress_pipeline.889698148
Short name	T627
Test name
Test status
Simulation time	2533316336 ps
CPU time	127.7 seconds
Started	Jun 07 07:36:50 PM PDT 24
Finished	Jun 07 07:38:59 PM PDT 24
Peak memory	202980 kb
Host	smart-8122dcb6-5804-4bc4-ac3d-ebef9e3178e2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889698148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_stress_pipeline.889698148
Directory	/workspace/28.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1960926903
Short name	T502
Test name
Test status
Simulation time	144372885 ps
CPU time	101.97 seconds
Started	Jun 07 07:36:50 PM PDT 24
Finished	Jun 07 07:38:33 PM PDT 24
Peak memory	363472 kb
Host	smart-b0fba7f9-94b3-4d44-989c-3db0e31a3671
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960926903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1960926903
Directory	/workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2721636182
Short name	T530
Test name
Test status
Simulation time	1642250923 ps
CPU time	421.89 seconds
Started	Jun 07 07:37:05 PM PDT 24
Finished	Jun 07 07:44:08 PM PDT 24
Peak memory	366084 kb
Host	smart-ee2f003d-f56b-495f-9f3b-3fd798263aa2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721636182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2721636182
Directory	/workspace/29.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/29.sram_ctrl_alert_test.1817561617
Short name	T232
Test name
Test status
Simulation time	131792899 ps
CPU time	0.67 seconds
Started	Jun 07 07:37:13 PM PDT 24
Finished	Jun 07 07:37:15 PM PDT 24
Peak memory	202168 kb
Host	smart-de9d0226-bb22-4079-b545-8c125e5b6317
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817561617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1817561617
Directory	/workspace/29.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.sram_ctrl_bijection.3702197646
Short name	T388
Test name
Test status
Simulation time	14982898042 ps
CPU time	87.21 seconds
Started	Jun 07 07:36:58 PM PDT 24
Finished	Jun 07 07:38:26 PM PDT 24
Peak memory	202988 kb
Host	smart-718a79d2-7b2b-478a-82ab-5383bc112072
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702197646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .3702197646
Directory	/workspace/29.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/29.sram_ctrl_executable.2329885276
Short name	T4
Test name
Test status
Simulation time	1923142543 ps
CPU time	593.98 seconds
Started	Jun 07 07:37:04 PM PDT 24
Finished	Jun 07 07:46:59 PM PDT 24
Peak memory	373864 kb
Host	smart-88cbf36a-5fe2-4eba-9059-b0003e8e9c38
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329885276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.2329885276
Directory	/workspace/29.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/29.sram_ctrl_lc_escalation.3279733758
Short name	T726
Test name
Test status
Simulation time	496874416 ps
CPU time	6.12 seconds
Started	Jun 07 07:37:05 PM PDT 24
Finished	Jun 07 07:37:12 PM PDT 24
Peak memory	211144 kb
Host	smart-17b83ba1-26b0-4394-b9bc-472eed9a6b7c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279733758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3279733758
Directory	/workspace/29.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/29.sram_ctrl_max_throughput.3139390102
Short name	T453
Test name
Test status
Simulation time	127783106 ps
CPU time	67.28 seconds
Started	Jun 07 07:37:04 PM PDT 24
Finished	Jun 07 07:38:13 PM PDT 24
Peak memory	313768 kb
Host	smart-93c68cc4-4006-4073-a208-205c3b591ce2
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139390102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 29.sram_ctrl_max_throughput.3139390102
Directory	/workspace/29.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1268309017
Short name	T41
Test name
Test status
Simulation time	660581401 ps
CPU time	6.31 seconds
Started	Jun 07 07:37:12 PM PDT 24
Finished	Jun 07 07:37:19 PM PDT 24
Peak memory	211084 kb
Host	smart-94601b0d-e64e-4ef5-b14d-19e4d0d70ddc
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268309017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1268309017
Directory	/workspace/29.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_mem_walk.1939875633
Short name	T733
Test name
Test status
Simulation time	2462571068 ps
CPU time	6.87 seconds
Started	Jun 07 07:37:13 PM PDT 24
Finished	Jun 07 07:37:21 PM PDT 24
Peak memory	211116 kb
Host	smart-61600a05-6f3d-48bc-ac8c-904c7592f41d
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939875633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1939875633
Directory	/workspace/29.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/29.sram_ctrl_multiple_keys.3744793227
Short name	T426
Test name
Test status
Simulation time	13881530434 ps
CPU time	1110.86 seconds
Started	Jun 07 07:36:59 PM PDT 24
Finished	Jun 07 07:55:31 PM PDT 24
Peak memory	375864 kb
Host	smart-0b2c56a0-b78a-4950-8280-4da04caa1fc1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744793227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3744793227
Directory	/workspace/29.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access.533066623
Short name	T483
Test name
Test status
Simulation time	102108670 ps
CPU time	1.35 seconds
Started	Jun 07 07:37:04 PM PDT 24
Finished	Jun 07 07:37:07 PM PDT 24
Peak memory	202884 kb
Host	smart-fae940d1-0c10-4551-a921-6b14c87fd73e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533066623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s ram_ctrl_partial_access.533066623
Directory	/workspace/29.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1479067744
Short name	T728
Test name
Test status
Simulation time	42183714272 ps
CPU time	546.37 seconds
Started	Jun 07 07:37:04 PM PDT 24
Finished	Jun 07 07:46:11 PM PDT 24
Peak memory	202916 kb
Host	smart-735ada1f-4d5e-41dd-b679-697e53b94864
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479067744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.1479067744
Directory	/workspace/29.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/29.sram_ctrl_ram_cfg.2722480329
Short name	T505
Test name
Test status
Simulation time	82278737 ps
CPU time	0.76 seconds
Started	Jun 07 07:37:05 PM PDT 24
Finished	Jun 07 07:37:07 PM PDT 24
Peak memory	202932 kb
Host	smart-b6ca8ebd-b993-40b5-b0bb-39360f7d2c8a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722480329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2722480329
Directory	/workspace/29.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/29.sram_ctrl_regwen.723609881
Short name	T532
Test name
Test status
Simulation time	2245040704 ps
CPU time	1139.92 seconds
Started	Jun 07 07:37:04 PM PDT 24
Finished	Jun 07 07:56:04 PM PDT 24
Peak memory	364672 kb
Host	smart-727f85bc-1747-4410-badb-d885a8def2f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723609881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.723609881
Directory	/workspace/29.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/29.sram_ctrl_smoke.1613440070
Short name	T234
Test name
Test status
Simulation time	478126359 ps
CPU time	41.21 seconds
Started	Jun 07 07:36:57 PM PDT 24
Finished	Jun 07 07:37:40 PM PDT 24
Peak memory	327660 kb
Host	smart-18482043-f589-47e4-a2ff-53a432c92acc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613440070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1613440070
Directory	/workspace/29.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all.1070600420
Short name	T467
Test name
Test status
Simulation time	18828515129 ps
CPU time	637.45 seconds
Started	Jun 07 07:37:14 PM PDT 24
Finished	Jun 07 07:47:53 PM PDT 24
Peak memory	369324 kb
Host	smart-0e0a8c2c-acdb-4649-9003-d266eda3bcf5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070600420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.sram_ctrl_stress_all.1070600420
Directory	/workspace/29.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1371329370
Short name	T109
Test name
Test status
Simulation time	9917348764 ps
CPU time	155.37 seconds
Started	Jun 07 07:37:16 PM PDT 24
Finished	Jun 07 07:39:52 PM PDT 24
Peak memory	333940 kb
Host	smart-656fdb76-dcb8-435f-b365-0ee9cf6a600b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1371329370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1371329370
Directory	/workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3810096450
Short name	T261
Test name
Test status
Simulation time	10699652885 ps
CPU time	530.53 seconds
Started	Jun 07 07:37:05 PM PDT 24
Finished	Jun 07 07:45:57 PM PDT 24
Peak memory	202972 kb
Host	smart-310a1ae1-7736-4b3f-8047-52a9a4bfe52a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810096450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.3810096450
Directory	/workspace/29.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3021160835
Short name	T9
Test name
Test status
Simulation time	301138276 ps
CPU time	132.62 seconds
Started	Jun 07 07:37:07 PM PDT 24
Finished	Jun 07 07:39:20 PM PDT 24
Peak memory	366428 kb
Host	smart-1074ec46-bce8-4511-9cad-d12f4d9d088c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021160835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3021160835
Directory	/workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3094096500
Short name	T260
Test name
Test status
Simulation time	4056003141 ps
CPU time	502.36 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:42:12 PM PDT 24
Peak memory	343880 kb
Host	smart-b830ee22-9dd6-4fe4-8e91-f5d66dedf4c1
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094096500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3094096500
Directory	/workspace/3.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/3.sram_ctrl_bijection.3657897612
Short name	T304
Test name
Test status
Simulation time	9215935035 ps
CPU time	89.72 seconds
Started	Jun 07 07:33:40 PM PDT 24
Finished	Jun 07 07:35:15 PM PDT 24
Peak memory	202944 kb
Host	smart-dc34aa72-4eaf-43db-b11c-d009fcc01837
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657897612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3657897612
Directory	/workspace/3.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/3.sram_ctrl_executable.1062853408
Short name	T148
Test name
Test status
Simulation time	2312994093 ps
CPU time	14.03 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:34:00 PM PDT 24
Peak memory	202960 kb
Host	smart-9031c44f-79f4-4077-b6f5-ad377cd405c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062853408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1062853408
Directory	/workspace/3.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/3.sram_ctrl_lc_escalation.1898207957
Short name	T501
Test name
Test status
Simulation time	839002283 ps
CPU time	3.58 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	202984 kb
Host	smart-6f4d1c01-6de7-4957-88fb-4e4c8b2d5102
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898207957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1898207957
Directory	/workspace/3.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/3.sram_ctrl_max_throughput.203049585
Short name	T647
Test name
Test status
Simulation time	340032819 ps
CPU time	25.99 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:34:14 PM PDT 24
Peak memory	285500 kb
Host	smart-4c9a8fe9-a74a-4883-9d58-11464d61f418
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203049585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.sram_ctrl_max_throughput.203049585
Directory	/workspace/3.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_partial_access.21649914
Short name	T296
Test name
Test status
Simulation time	516935945 ps
CPU time	2.71 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:50 PM PDT 24
Peak memory	211136 kb
Host	smart-9381c7fb-7812-49c3-abbd-4dc7ccc9b291
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_mem_partial_access.21649914
Directory	/workspace/3.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_mem_walk.920951055
Short name	T469
Test name
Test status
Simulation time	666381374 ps
CPU time	6.33 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:54 PM PDT 24
Peak memory	211068 kb
Host	smart-9512a87d-cf62-469e-a85a-c53bd4e6b40b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920951055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ mem_walk.920951055
Directory	/workspace/3.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/3.sram_ctrl_multiple_keys.3085930261
Short name	T764
Test name
Test status
Simulation time	3448543895 ps
CPU time	110.69 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:35:37 PM PDT 24
Peak memory	306580 kb
Host	smart-6fce9545-f122-4ddb-8c7d-1e02ee760ff1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085930261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip le_keys.3085930261
Directory	/workspace/3.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access.1214777491
Short name	T844
Test name
Test status
Simulation time	201965562 ps
CPU time	11.61 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:33:58 PM PDT 24
Peak memory	202968 kb
Host	smart-76b2d3a7-0b1d-4fcf-8843-09777b9de216
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214777491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.1214777491
Directory	/workspace/3.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2506044634
Short name	T779
Test name
Test status
Simulation time	156482747142 ps
CPU time	499.34 seconds
Started	Jun 07 07:33:36 PM PDT 24
Finished	Jun 07 07:42:00 PM PDT 24
Peak memory	202932 kb
Host	smart-01346640-e04e-41d5-9486-50a2842704c8
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506044634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_partial_access_b2b.2506044634
Directory	/workspace/3.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/3.sram_ctrl_ram_cfg.221453423
Short name	T578
Test name
Test status
Simulation time	107331483 ps
CPU time	0.73 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:33:49 PM PDT 24
Peak memory	202932 kb
Host	smart-e68bee18-5817-43a0-bf90-d249f1964b90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221453423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.221453423
Directory	/workspace/3.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/3.sram_ctrl_regwen.2796632318
Short name	T193
Test name
Test status
Simulation time	4296722739 ps
CPU time	894.37 seconds
Started	Jun 07 07:33:38 PM PDT 24
Finished	Jun 07 07:48:37 PM PDT 24
Peak memory	368644 kb
Host	smart-41c33565-0326-41d9-beca-c04ea360ba9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796632318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2796632318
Directory	/workspace/3.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/3.sram_ctrl_smoke.2411352549
Short name	T863
Test name
Test status
Simulation time	2356315475 ps
CPU time	94.58 seconds
Started	Jun 07 07:33:39 PM PDT 24
Finished	Jun 07 07:35:18 PM PDT 24
Peak memory	356020 kb
Host	smart-4a976858-94db-49e6-bb28-f13f1c173cff
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411352549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2411352549
Directory	/workspace/3.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all.797263263
Short name	T111
Test name
Test status
Simulation time	145373900827 ps
CPU time	530.19 seconds
Started	Jun 07 07:33:36 PM PDT 24
Finished	Jun 07 07:42:31 PM PDT 24
Peak memory	357892 kb
Host	smart-d437977a-5699-4f2c-8c0a-6c2d0e516e83
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797263263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_stress_all.797263263
Directory	/workspace/3.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1207587900
Short name	T814
Test name
Test status
Simulation time	896694668 ps
CPU time	24.6 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:34:11 PM PDT 24
Peak memory	211176 kb
Host	smart-86f6bb47-d634-4888-bb60-5925ce46e6ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1207587900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.1207587900
Directory	/workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.sram_ctrl_stress_pipeline.360080528
Short name	T574
Test name
Test status
Simulation time	2248374774 ps
CPU time	219.3 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:37:28 PM PDT 24
Peak memory	203000 kb
Host	smart-0a0b6423-0126-47fe-b1b2-e77f5d2c34c6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360080528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.360080528
Directory	/workspace/3.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2990407755
Short name	T278
Test name
Test status
Simulation time	126540808 ps
CPU time	48.21 seconds
Started	Jun 07 07:33:38 PM PDT 24
Finished	Jun 07 07:34:30 PM PDT 24
Peak memory	313236 kb
Host	smart-22354012-e841-4582-a5d2-12617e25c963
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990407755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2990407755
Directory	/workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3492828945
Short name	T666
Test name
Test status
Simulation time	11284150163 ps
CPU time	1107.04 seconds
Started	Jun 07 07:37:18 PM PDT 24
Finished	Jun 07 07:55:47 PM PDT 24
Peak memory	374776 kb
Host	smart-374432be-8a07-4cdd-8044-92235827f64b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492828945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.3492828945
Directory	/workspace/30.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/30.sram_ctrl_alert_test.193747101
Short name	T925
Test name
Test status
Simulation time	36060651 ps
CPU time	0.66 seconds
Started	Jun 07 07:37:29 PM PDT 24
Finished	Jun 07 07:37:32 PM PDT 24
Peak memory	202620 kb
Host	smart-bab557e1-994a-4989-a41b-694041465a52
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193747101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.193747101
Directory	/workspace/30.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.sram_ctrl_bijection.3578021508
Short name	T64
Test name
Test status
Simulation time	4472627950 ps
CPU time	28.78 seconds
Started	Jun 07 07:37:12 PM PDT 24
Finished	Jun 07 07:37:42 PM PDT 24
Peak memory	202956 kb
Host	smart-2f73dc3f-5ec3-4585-b89a-01b146f2f495
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578021508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .3578021508
Directory	/workspace/30.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/30.sram_ctrl_executable.2476484527
Short name	T923
Test name
Test status
Simulation time	110957402675 ps
CPU time	1302.32 seconds
Started	Jun 07 07:37:19 PM PDT 24
Finished	Jun 07 07:59:03 PM PDT 24
Peak memory	374536 kb
Host	smart-29559471-ae1f-4d2e-ba1c-4c103c923b10
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476484527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2476484527
Directory	/workspace/30.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/30.sram_ctrl_lc_escalation.3862584648
Short name	T307
Test name
Test status
Simulation time	415395473 ps
CPU time	6.73 seconds
Started	Jun 07 07:37:22 PM PDT 24
Finished	Jun 07 07:37:30 PM PDT 24
Peak memory	202900 kb
Host	smart-efb99836-ff7e-4f4e-b46e-98f8fc6a7ed6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862584648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3862584648
Directory	/workspace/30.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/30.sram_ctrl_max_throughput.1479846029
Short name	T836
Test name
Test status
Simulation time	366396643 ps
CPU time	37.79 seconds
Started	Jun 07 07:37:20 PM PDT 24
Finished	Jun 07 07:38:00 PM PDT 24
Peak memory	304168 kb
Host	smart-f39f2c44-c039-4374-9720-021eb515b780
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479846029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.1479846029
Directory	/workspace/30.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_partial_access.572676960
Short name	T651
Test name
Test status
Simulation time	174912031 ps
CPU time	2.65 seconds
Started	Jun 07 07:37:20 PM PDT 24
Finished	Jun 07 07:37:25 PM PDT 24
Peak memory	211080 kb
Host	smart-acfda096-52be-4bcc-ae1e-0660c53a37b6
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572676960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_mem_partial_access.572676960
Directory	/workspace/30.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_mem_walk.3896860888
Short name	T735
Test name
Test status
Simulation time	718887696 ps
CPU time	9.74 seconds
Started	Jun 07 07:37:19 PM PDT 24
Finished	Jun 07 07:37:30 PM PDT 24
Peak memory	211004 kb
Host	smart-9a4d9ba5-3ec2-47ff-8769-185f3f952534
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896860888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3896860888
Directory	/workspace/30.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/30.sram_ctrl_multiple_keys.2738919092
Short name	T135
Test name
Test status
Simulation time	72186520579 ps
CPU time	1064.9 seconds
Started	Jun 07 07:37:13 PM PDT 24
Finished	Jun 07 07:54:59 PM PDT 24
Peak memory	373784 kb
Host	smart-289fcd82-ea53-4e49-afe7-749afee464cb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738919092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.2738919092
Directory	/workspace/30.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access.886345809
Short name	T661
Test name
Test status
Simulation time	746036349 ps
CPU time	14.06 seconds
Started	Jun 07 07:37:14 PM PDT 24
Finished	Jun 07 07:37:29 PM PDT 24
Peak memory	202892 kb
Host	smart-6ff50c0c-935c-408f-9665-57d5d2174507
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886345809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.s ram_ctrl_partial_access.886345809
Directory	/workspace/30.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3745029352
Short name	T696
Test name
Test status
Simulation time	21997747008 ps
CPU time	260.21 seconds
Started	Jun 07 07:37:21 PM PDT 24
Finished	Jun 07 07:41:43 PM PDT 24
Peak memory	202972 kb
Host	smart-871bae9c-152c-4095-a1a7-c14ddccdabf1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745029352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3745029352
Directory	/workspace/30.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/30.sram_ctrl_ram_cfg.1413278900
Short name	T451
Test name
Test status
Simulation time	239563657 ps
CPU time	0.8 seconds
Started	Jun 07 07:37:19 PM PDT 24
Finished	Jun 07 07:37:21 PM PDT 24
Peak memory	202924 kb
Host	smart-93f3abea-77b1-4322-a0d7-cbe766577fd9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413278900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.1413278900
Directory	/workspace/30.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/30.sram_ctrl_regwen.3277338314
Short name	T131
Test name
Test status
Simulation time	6998521474 ps
CPU time	316.4 seconds
Started	Jun 07 07:37:21 PM PDT 24
Finished	Jun 07 07:42:40 PM PDT 24
Peak memory	323404 kb
Host	smart-1d2c0240-b25e-4377-9886-375c2c370588
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277338314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3277338314
Directory	/workspace/30.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/30.sram_ctrl_smoke.1929131634
Short name	T314
Test name
Test status
Simulation time	35034800 ps
CPU time	1.7 seconds
Started	Jun 07 07:37:13 PM PDT 24
Finished	Jun 07 07:37:16 PM PDT 24
Peak memory	202900 kb
Host	smart-35b33ffa-e25e-486f-8030-5bbcfe078ed3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929131634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1929131634
Directory	/workspace/30.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all.79615482
Short name	T10
Test name
Test status
Simulation time	1612899272 ps
CPU time	417.98 seconds
Started	Jun 07 07:37:29 PM PDT 24
Finished	Jun 07 07:44:29 PM PDT 24
Peak memory	361224 kb
Host	smart-2c4bae94-22ba-4d39-a41f-2cb24fa1fbfc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79615482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.sram_ctrl_stress_all.79615482
Directory	/workspace/30.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.531183264
Short name	T354
Test name
Test status
Simulation time	1337250175 ps
CPU time	679.33 seconds
Started	Jun 07 07:37:22 PM PDT 24
Finished	Jun 07 07:48:44 PM PDT 24
Peak memory	369684 kb
Host	smart-32a2dd86-4dd7-49ed-b6e7-a160cba275a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=531183264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.531183264
Directory	/workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3308755040
Short name	T608
Test name
Test status
Simulation time	7109094232 ps
CPU time	337.08 seconds
Started	Jun 07 07:37:14 PM PDT 24
Finished	Jun 07 07:42:52 PM PDT 24
Peak memory	202936 kb
Host	smart-9995215a-732f-486f-8199-78411da73d59
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308755040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.3308755040
Directory	/workspace/30.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1409539109
Short name	T176
Test name
Test status
Simulation time	84903394 ps
CPU time	21.71 seconds
Started	Jun 07 07:37:20 PM PDT 24
Finished	Jun 07 07:37:44 PM PDT 24
Peak memory	268304 kb
Host	smart-74158105-a221-45fe-af2e-471e7116fa13
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409539109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1409539109
Directory	/workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/31.sram_ctrl_alert_test.3181617392
Short name	T531
Test name
Test status
Simulation time	43677835 ps
CPU time	0.66 seconds
Started	Jun 07 07:37:50 PM PDT 24
Finished	Jun 07 07:37:53 PM PDT 24
Peak memory	202628 kb
Host	smart-3b36326e-5ec2-4636-bc6a-b6b7b6e4a73e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181617392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.3181617392
Directory	/workspace/31.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.sram_ctrl_bijection.61973244
Short name	T389
Test name
Test status
Simulation time	4769938911 ps
CPU time	75.95 seconds
Started	Jun 07 07:37:30 PM PDT 24
Finished	Jun 07 07:38:49 PM PDT 24
Peak memory	203000 kb
Host	smart-e9dda833-49b1-4988-86e0-ee78ff70422d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61973244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.61973244
Directory	/workspace/31.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/31.sram_ctrl_executable.1036790726
Short name	T572
Test name
Test status
Simulation time	24221441829 ps
CPU time	716.99 seconds
Started	Jun 07 07:37:41 PM PDT 24
Finished	Jun 07 07:49:41 PM PDT 24
Peak memory	372628 kb
Host	smart-d64bc0b3-33c7-4c29-a901-e5e908e501c3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036790726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.1036790726
Directory	/workspace/31.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/31.sram_ctrl_lc_escalation.1862737382
Short name	T822
Test name
Test status
Simulation time	535898270 ps
CPU time	6.39 seconds
Started	Jun 07 07:37:40 PM PDT 24
Finished	Jun 07 07:37:50 PM PDT 24
Peak memory	202996 kb
Host	smart-42d4e5be-7ab5-43a1-a167-d7f1377293bd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862737382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.1862737382
Directory	/workspace/31.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/31.sram_ctrl_max_throughput.1757928483
Short name	T363
Test name
Test status
Simulation time	114466891 ps
CPU time	8.56 seconds
Started	Jun 07 07:37:42 PM PDT 24
Finished	Jun 07 07:37:55 PM PDT 24
Peak memory	241308 kb
Host	smart-a9269637-212f-4dfc-a292-ff9f8df02b4d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757928483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.1757928483
Directory	/workspace/31.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2433891755
Short name	T289
Test name
Test status
Simulation time	220940582 ps
CPU time	2.87 seconds
Started	Jun 07 07:37:41 PM PDT 24
Finished	Jun 07 07:37:48 PM PDT 24
Peak memory	211092 kb
Host	smart-fb2bf77c-579d-4344-b9eb-c158ed7626ec
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433891755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.2433891755
Directory	/workspace/31.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_mem_walk.2783036811
Short name	T457
Test name
Test status
Simulation time	461754896 ps
CPU time	9.15 seconds
Started	Jun 07 07:37:40 PM PDT 24
Finished	Jun 07 07:37:52 PM PDT 24
Peak memory	211140 kb
Host	smart-ad8fbc74-ed51-4963-afd1-e1279cfe8d4f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783036811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.2783036811
Directory	/workspace/31.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/31.sram_ctrl_multiple_keys.2315463088
Short name	T407
Test name
Test status
Simulation time	19005698379 ps
CPU time	943.73 seconds
Started	Jun 07 07:37:29 PM PDT 24
Finished	Jun 07 07:53:16 PM PDT 24
Peak memory	375772 kb
Host	smart-f52a151f-f49d-4c44-a696-5c71f2ca035b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315463088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.2315463088
Directory	/workspace/31.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access.1934141839
Short name	T751
Test name
Test status
Simulation time	9565989580 ps
CPU time	23.59 seconds
Started	Jun 07 07:37:42 PM PDT 24
Finished	Jun 07 07:38:10 PM PDT 24
Peak memory	202920 kb
Host	smart-cb28f28e-c02d-4225-93fd-f5e452ddc6fd
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934141839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.1934141839
Directory	/workspace/31.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.431204922
Short name	T327
Test name
Test status
Simulation time	74356884923 ps
CPU time	516.66 seconds
Started	Jun 07 07:37:41 PM PDT 24
Finished	Jun 07 07:46:21 PM PDT 24
Peak memory	202988 kb
Host	smart-f245cb73-a375-4064-9703-d36bdd8ed1c5
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431204922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.sram_ctrl_partial_access_b2b.431204922
Directory	/workspace/31.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/31.sram_ctrl_ram_cfg.2861685214
Short name	T187
Test name
Test status
Simulation time	26304424 ps
CPU time	0.8 seconds
Started	Jun 07 07:37:40 PM PDT 24
Finished	Jun 07 07:37:43 PM PDT 24
Peak memory	202928 kb
Host	smart-a12c468d-3be8-415a-b3be-c5b3c921e824
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861685214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2861685214
Directory	/workspace/31.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/31.sram_ctrl_regwen.3697655337
Short name	T587
Test name
Test status
Simulation time	43084503740 ps
CPU time	1325.02 seconds
Started	Jun 07 07:37:41 PM PDT 24
Finished	Jun 07 07:59:50 PM PDT 24
Peak memory	375880 kb
Host	smart-55b05026-27fc-490b-8201-a26260f2c2ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697655337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3697655337
Directory	/workspace/31.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/31.sram_ctrl_smoke.2877474382
Short name	T619
Test name
Test status
Simulation time	3358965993 ps
CPU time	154.23 seconds
Started	Jun 07 07:37:29 PM PDT 24
Finished	Jun 07 07:40:07 PM PDT 24
Peak memory	367128 kb
Host	smart-f41d4a20-176a-49db-b41c-ffe4f4cd7f5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877474382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2877474382
Directory	/workspace/31.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all.3294752597
Short name	T432
Test name
Test status
Simulation time	75960992372 ps
CPU time	3472.38 seconds
Started	Jun 07 07:37:41 PM PDT 24
Finished	Jun 07 08:35:37 PM PDT 24
Peak memory	382948 kb
Host	smart-f5f6123f-7c02-4e99-80c7-727583d1087e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294752597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3294752597
Directory	/workspace/31.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1727858492
Short name	T767
Test name
Test status
Simulation time	1224957165 ps
CPU time	211.91 seconds
Started	Jun 07 07:37:39 PM PDT 24
Finished	Jun 07 07:41:14 PM PDT 24
Peak memory	346828 kb
Host	smart-0889ba4e-ae2a-4aee-a37c-cdeb18b865bc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1727858492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.1727858492
Directory	/workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1719905036
Short name	T377
Test name
Test status
Simulation time	3007453177 ps
CPU time	300.39 seconds
Started	Jun 07 07:37:27 PM PDT 24
Finished	Jun 07 07:42:30 PM PDT 24
Peak memory	202920 kb
Host	smart-2a3d0967-9948-4ba2-ae1f-322e3e6056cd
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719905036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1719905036
Directory	/workspace/31.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.672333735
Short name	T712
Test name
Test status
Simulation time	104754947 ps
CPU time	53.4 seconds
Started	Jun 07 07:37:40 PM PDT 24
Finished	Jun 07 07:38:37 PM PDT 24
Peak memory	294284 kb
Host	smart-06b42de4-5d2f-475d-9252-666fe4047b69
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672333735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.672333735
Directory	/workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/32.sram_ctrl_access_during_key_req.413777788
Short name	T763
Test name
Test status
Simulation time	5320979019 ps
CPU time	1003.84 seconds
Started	Jun 07 07:37:54 PM PDT 24
Finished	Jun 07 07:54:40 PM PDT 24
Peak memory	374620 kb
Host	smart-e008362f-32a4-4f3a-ba8c-165b296b176e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413777788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sram_ctrl_access_during_key_req.413777788
Directory	/workspace/32.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/32.sram_ctrl_alert_test.3251703877
Short name	T760
Test name
Test status
Simulation time	21565008 ps
CPU time	0.65 seconds
Started	Jun 07 07:38:00 PM PDT 24
Finished	Jun 07 07:38:04 PM PDT 24
Peak memory	202628 kb
Host	smart-34b9e52e-077f-40f1-873c-54294fa0d605
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251703877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3251703877
Directory	/workspace/32.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.sram_ctrl_bijection.1087065896
Short name	T809
Test name
Test status
Simulation time	3475193649 ps
CPU time	79.92 seconds
Started	Jun 07 07:37:52 PM PDT 24
Finished	Jun 07 07:39:14 PM PDT 24
Peak memory	202964 kb
Host	smart-5308e3cc-87a9-40c9-bcfa-f24075274976
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087065896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .1087065896
Directory	/workspace/32.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/32.sram_ctrl_executable.1777393569
Short name	T466
Test name
Test status
Simulation time	2038641745 ps
CPU time	727.39 seconds
Started	Jun 07 07:37:54 PM PDT 24
Finished	Jun 07 07:50:05 PM PDT 24
Peak memory	369628 kb
Host	smart-7a9c11f4-4984-4cc9-a463-39a55ffd1590
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777393569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.1777393569
Directory	/workspace/32.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/32.sram_ctrl_lc_escalation.2739925553
Short name	T927
Test name
Test status
Simulation time	421012381 ps
CPU time	4.89 seconds
Started	Jun 07 07:37:55 PM PDT 24
Finished	Jun 07 07:38:03 PM PDT 24
Peak memory	202932 kb
Host	smart-e1a81d06-3917-4739-a77e-898493711a20
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739925553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.2739925553
Directory	/workspace/32.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/32.sram_ctrl_max_throughput.3202607526
Short name	T215
Test name
Test status
Simulation time	267196541 ps
CPU time	12.51 seconds
Started	Jun 07 07:37:53 PM PDT 24
Finished	Jun 07 07:38:07 PM PDT 24
Peak memory	251976 kb
Host	smart-c74ea046-cc79-45f1-85cb-5f0a3ebafde5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202607526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.3202607526
Directory	/workspace/32.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2398738070
Short name	T368
Test name
Test status
Simulation time	244499950 ps
CPU time	4.59 seconds
Started	Jun 07 07:37:58 PM PDT 24
Finished	Jun 07 07:38:05 PM PDT 24
Peak memory	211108 kb
Host	smart-a31c22cf-de9f-4ab1-a8d6-8d265249c11a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398738070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2398738070
Directory	/workspace/32.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_mem_walk.3206823980
Short name	T192
Test name
Test status
Simulation time	184302174 ps
CPU time	10.17 seconds
Started	Jun 07 07:37:55 PM PDT 24
Finished	Jun 07 07:38:07 PM PDT 24
Peak memory	211100 kb
Host	smart-109b7bc3-b4ad-473e-8f2f-e92cebf46b09
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206823980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3206823980
Directory	/workspace/32.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/32.sram_ctrl_multiple_keys.3973401998
Short name	T780
Test name
Test status
Simulation time	23744597758 ps
CPU time	1703.85 seconds
Started	Jun 07 07:37:51 PM PDT 24
Finished	Jun 07 08:06:17 PM PDT 24
Peak memory	375856 kb
Host	smart-0f96c292-acb9-4f5b-a822-62d11667ca4f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973401998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.3973401998
Directory	/workspace/32.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access.2758825201
Short name	T216
Test name
Test status
Simulation time	787665020 ps
CPU time	3.13 seconds
Started	Jun 07 07:37:54 PM PDT 24
Finished	Jun 07 07:38:00 PM PDT 24
Peak memory	202776 kb
Host	smart-85429b8b-30b6-417b-a83d-f7f929eab2c6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758825201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.2758825201
Directory	/workspace/32.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.344286094
Short name	T926
Test name
Test status
Simulation time	39519474397 ps
CPU time	279.69 seconds
Started	Jun 07 07:37:51 PM PDT 24
Finished	Jun 07 07:42:32 PM PDT 24
Peak memory	202996 kb
Host	smart-bce81560-8f23-4954-8947-2504cf7a2f6e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344286094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 32.sram_ctrl_partial_access_b2b.344286094
Directory	/workspace/32.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/32.sram_ctrl_ram_cfg.3829413231
Short name	T292
Test name
Test status
Simulation time	47504017 ps
CPU time	0.73 seconds
Started	Jun 07 07:37:57 PM PDT 24
Finished	Jun 07 07:38:01 PM PDT 24
Peak memory	202908 kb
Host	smart-aafa11a9-f7cc-433b-8881-132fdfb4be8d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829413231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3829413231
Directory	/workspace/32.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/32.sram_ctrl_regwen.2274796285
Short name	T886
Test name
Test status
Simulation time	25759897881 ps
CPU time	1210.35 seconds
Started	Jun 07 07:37:51 PM PDT 24
Finished	Jun 07 07:58:04 PM PDT 24
Peak memory	374636 kb
Host	smart-6b8fc9e9-5a5a-4234-a1f2-51f7640bde6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274796285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2274796285
Directory	/workspace/32.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/32.sram_ctrl_smoke.890888185
Short name	T821
Test name
Test status
Simulation time	1155568719 ps
CPU time	6.72 seconds
Started	Jun 07 07:37:50 PM PDT 24
Finished	Jun 07 07:37:59 PM PDT 24
Peak memory	202936 kb
Host	smart-e84bc96c-2697-4a07-a3d9-34ba6248204f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890888185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.890888185
Directory	/workspace/32.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_all.2364066964
Short name	T843
Test name
Test status
Simulation time	249427841230 ps
CPU time	1981.63 seconds
Started	Jun 07 07:37:58 PM PDT 24
Finished	Jun 07 08:11:03 PM PDT 24
Peak memory	375092 kb
Host	smart-fc9bcd68-3a97-4bd3-924a-eeabbfa4b180
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364066964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2364066964
Directory	/workspace/32.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1573435741
Short name	T625
Test name
Test status
Simulation time	2191865387 ps
CPU time	224.74 seconds
Started	Jun 07 07:37:54 PM PDT 24
Finished	Jun 07 07:41:42 PM PDT 24
Peak memory	202940 kb
Host	smart-e18ad3ea-6325-4915-8aa5-cde88314f53a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573435741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.1573435741
Directory	/workspace/32.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1238227934
Short name	T600
Test name
Test status
Simulation time	195008994 ps
CPU time	13.82 seconds
Started	Jun 07 07:37:53 PM PDT 24
Finished	Jun 07 07:38:09 PM PDT 24
Peak memory	257044 kb
Host	smart-02a92af1-af3d-4e69-b311-e9f589b89e90
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238227934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.1238227934
Directory	/workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/33.sram_ctrl_access_during_key_req.3919092236
Short name	T820
Test name
Test status
Simulation time	23914474164 ps
CPU time	785.7 seconds
Started	Jun 07 07:38:01 PM PDT 24
Finished	Jun 07 07:51:10 PM PDT 24
Peak memory	361452 kb
Host	smart-89569f0b-60c7-477e-a979-b886f3da9006
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919092236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.3919092236
Directory	/workspace/33.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/33.sram_ctrl_alert_test.1568558164
Short name	T555
Test name
Test status
Simulation time	14806241 ps
CPU time	0.64 seconds
Started	Jun 07 07:38:11 PM PDT 24
Finished	Jun 07 07:38:15 PM PDT 24
Peak memory	202608 kb
Host	smart-d7a2ac18-11ee-4436-afd6-edf1be650bde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568558164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.1568558164
Directory	/workspace/33.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.sram_ctrl_bijection.1913735389
Short name	T387
Test name
Test status
Simulation time	4163410638 ps
CPU time	68.3 seconds
Started	Jun 07 07:38:02 PM PDT 24
Finished	Jun 07 07:39:13 PM PDT 24
Peak memory	203012 kb
Host	smart-6a28a063-c3b6-44f4-86af-6ebada1615bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913735389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection .1913735389
Directory	/workspace/33.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/33.sram_ctrl_executable.1773646202
Short name	T227
Test name
Test status
Simulation time	26861599541 ps
CPU time	1901.85 seconds
Started	Jun 07 07:38:02 PM PDT 24
Finished	Jun 07 08:09:46 PM PDT 24
Peak memory	375404 kb
Host	smart-11593f3e-e51a-4120-9f37-a77699fbb58a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773646202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.1773646202
Directory	/workspace/33.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/33.sram_ctrl_max_throughput.4033141191
Short name	T649
Test name
Test status
Simulation time	71423973 ps
CPU time	17.35 seconds
Started	Jun 07 07:37:58 PM PDT 24
Finished	Jun 07 07:38:18 PM PDT 24
Peak memory	253992 kb
Host	smart-b62a4842-afa7-4686-8bcf-e190edeafeae
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033141191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.4033141191
Directory	/workspace/33.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2310480181
Short name	T455
Test name
Test status
Simulation time	331584781 ps
CPU time	3.04 seconds
Started	Jun 07 07:38:10 PM PDT 24
Finished	Jun 07 07:38:16 PM PDT 24
Peak memory	211120 kb
Host	smart-7e26a896-e777-4ff7-af29-d3c2e320a1f1
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310480181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2310480181
Directory	/workspace/33.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_mem_walk.1171506298
Short name	T698
Test name
Test status
Simulation time	574506764 ps
CPU time	8.35 seconds
Started	Jun 07 07:38:09 PM PDT 24
Finished	Jun 07 07:38:20 PM PDT 24
Peak memory	211068 kb
Host	smart-22480623-61a5-4e57-92b6-a5eada103b65
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171506298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.1171506298
Directory	/workspace/33.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/33.sram_ctrl_multiple_keys.1138875538
Short name	T430
Test name
Test status
Simulation time	27106693548 ps
CPU time	1864.94 seconds
Started	Jun 07 07:38:01 PM PDT 24
Finished	Jun 07 08:09:09 PM PDT 24
Peak memory	372448 kb
Host	smart-d9a747a3-3c79-4acc-abd3-cef6339d880a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138875538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.1138875538
Directory	/workspace/33.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access.2334744292
Short name	T263
Test name
Test status
Simulation time	153829541 ps
CPU time	3.4 seconds
Started	Jun 07 07:38:01 PM PDT 24
Finished	Jun 07 07:38:07 PM PDT 24
Peak memory	202912 kb
Host	smart-4ece1d9c-278b-40fd-8a88-6faee98f6db6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334744292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.2334744292
Directory	/workspace/33.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2332457047
Short name	T912
Test name
Test status
Simulation time	14542030351 ps
CPU time	364.47 seconds
Started	Jun 07 07:38:00 PM PDT 24
Finished	Jun 07 07:44:07 PM PDT 24
Peak memory	203000 kb
Host	smart-0927e25e-1137-41fc-9206-ec82f3afad1b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332457047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2332457047
Directory	/workspace/33.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/33.sram_ctrl_ram_cfg.1064868211
Short name	T553
Test name
Test status
Simulation time	47129349 ps
CPU time	0.77 seconds
Started	Jun 07 07:38:08 PM PDT 24
Finished	Jun 07 07:38:11 PM PDT 24
Peak memory	202812 kb
Host	smart-1180dd8e-71b5-4fe0-896c-ae1efb3a282d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064868211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1064868211
Directory	/workspace/33.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/33.sram_ctrl_regwen.1415877496
Short name	T768
Test name
Test status
Simulation time	15362826804 ps
CPU time	1364.36 seconds
Started	Jun 07 07:38:01 PM PDT 24
Finished	Jun 07 08:00:49 PM PDT 24
Peak memory	375784 kb
Host	smart-9a1cf9e3-c737-4875-9780-29201dc51075
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415877496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1415877496
Directory	/workspace/33.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/33.sram_ctrl_smoke.3899502712
Short name	T766
Test name
Test status
Simulation time	510839430 ps
CPU time	7.71 seconds
Started	Jun 07 07:38:02 PM PDT 24
Finished	Jun 07 07:38:12 PM PDT 24
Peak memory	202916 kb
Host	smart-1155473b-4648-4936-84f8-06c8a8e9d256
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899502712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3899502712
Directory	/workspace/33.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all.2173038366
Short name	T632
Test name
Test status
Simulation time	156248436101 ps
CPU time	3164.61 seconds
Started	Jun 07 07:38:10 PM PDT 24
Finished	Jun 07 08:30:58 PM PDT 24
Peak memory	375768 kb
Host	smart-91aa1a49-2233-4507-a898-a2d83ab06aed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173038366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.2173038366
Directory	/workspace/33.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3612897027
Short name	T106
Test name
Test status
Simulation time	1166914448 ps
CPU time	35.82 seconds
Started	Jun 07 07:38:09 PM PDT 24
Finished	Jun 07 07:38:47 PM PDT 24
Peak memory	219268 kb
Host	smart-d262c12e-df12-4b6b-b4bb-7effe0b6ed3e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3612897027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3612897027
Directory	/workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.sram_ctrl_stress_pipeline.496486196
Short name	T671
Test name
Test status
Simulation time	1380798004 ps
CPU time	138.68 seconds
Started	Jun 07 07:38:00 PM PDT 24
Finished	Jun 07 07:40:22 PM PDT 24
Peak memory	202924 kb
Host	smart-962f1754-0cb7-43d4-8edd-81bb380879cb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496486196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sram_ctrl_stress_pipeline.496486196
Directory	/workspace/33.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3145627581
Short name	T147
Test name
Test status
Simulation time	288364153 ps
CPU time	1.77 seconds
Started	Jun 07 07:37:59 PM PDT 24
Finished	Jun 07 07:38:03 PM PDT 24
Peak memory	211172 kb
Host	smart-8482fd6e-fc9a-450f-a5c8-310ac5c31fb1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145627581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.3145627581
Directory	/workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/34.sram_ctrl_access_during_key_req.227510109
Short name	T321
Test name
Test status
Simulation time	2460869341 ps
CPU time	569.62 seconds
Started	Jun 07 07:38:18 PM PDT 24
Finished	Jun 07 07:47:51 PM PDT 24
Peak memory	373260 kb
Host	smart-b980e39a-370f-49c3-a9d3-608bad5799df
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227510109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sram_ctrl_access_during_key_req.227510109
Directory	/workspace/34.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/34.sram_ctrl_alert_test.1643911001
Short name	T748
Test name
Test status
Simulation time	14000242 ps
CPU time	0.68 seconds
Started	Jun 07 07:38:28 PM PDT 24
Finished	Jun 07 07:38:31 PM PDT 24
Peak memory	202608 kb
Host	smart-9d2097a1-b42f-44b3-abcc-f4a78cd0fe47
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643911001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1643911001
Directory	/workspace/34.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.sram_ctrl_bijection.2789237289
Short name	T186
Test name
Test status
Simulation time	2975852521 ps
CPU time	34.43 seconds
Started	Jun 07 07:38:08 PM PDT 24
Finished	Jun 07 07:38:45 PM PDT 24
Peak memory	202988 kb
Host	smart-71773832-dca1-4388-8706-1d900453d612
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789237289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .2789237289
Directory	/workspace/34.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/34.sram_ctrl_executable.253258614
Short name	T638
Test name
Test status
Simulation time	3397984887 ps
CPU time	796.97 seconds
Started	Jun 07 07:38:17 PM PDT 24
Finished	Jun 07 07:51:37 PM PDT 24
Peak memory	375784 kb
Host	smart-4db36871-d6b8-49bf-b343-553a2b905b7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253258614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.253258614
Directory	/workspace/34.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/34.sram_ctrl_lc_escalation.3395943979
Short name	T181
Test name
Test status
Simulation time	1422717390 ps
CPU time	5.81 seconds
Started	Jun 07 07:38:19 PM PDT 24
Finished	Jun 07 07:38:29 PM PDT 24
Peak memory	202932 kb
Host	smart-d388f090-cb4c-4844-900b-95e3af5d4cfd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395943979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3395943979
Directory	/workspace/34.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/34.sram_ctrl_max_throughput.304547579
Short name	T722
Test name
Test status
Simulation time	267168209 ps
CPU time	52.76 seconds
Started	Jun 07 07:38:17 PM PDT 24
Finished	Jun 07 07:39:13 PM PDT 24
Peak memory	328832 kb
Host	smart-15c9e1a3-35b9-420e-bf3f-59a3353f679f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304547579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.304547579
Directory	/workspace/34.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2200261851
Short name	T711
Test name
Test status
Simulation time	970066342 ps
CPU time	5.88 seconds
Started	Jun 07 07:38:17 PM PDT 24
Finished	Jun 07 07:38:26 PM PDT 24
Peak memory	211092 kb
Host	smart-f071aae9-b06c-419a-9f19-9ff9e4110496
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200261851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.2200261851
Directory	/workspace/34.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_mem_walk.720838477
Short name	T299
Test name
Test status
Simulation time	862315632 ps
CPU time	5.91 seconds
Started	Jun 07 07:38:19 PM PDT 24
Finished	Jun 07 07:38:29 PM PDT 24
Peak memory	211052 kb
Host	smart-f536980b-f284-4fb8-b16a-38447f6ada86
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720838477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _mem_walk.720838477
Directory	/workspace/34.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/34.sram_ctrl_multiple_keys.1082823241
Short name	T855
Test name
Test status
Simulation time	48776945618 ps
CPU time	1007.26 seconds
Started	Jun 07 07:38:08 PM PDT 24
Finished	Jun 07 07:54:58 PM PDT 24
Peak memory	373896 kb
Host	smart-faa00fa9-11fc-4b4a-8bac-a62c754bb410
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082823241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1082823241
Directory	/workspace/34.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access.1198157501
Short name	T626
Test name
Test status
Simulation time	2173541050 ps
CPU time	21.25 seconds
Started	Jun 07 07:38:11 PM PDT 24
Finished	Jun 07 07:38:35 PM PDT 24
Peak memory	202936 kb
Host	smart-a4c47409-8c56-4c24-bfc5-d75beedce05d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198157501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1198157501
Directory	/workspace/34.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1440782128
Short name	T562
Test name
Test status
Simulation time	64657333926 ps
CPU time	240.43 seconds
Started	Jun 07 07:38:09 PM PDT 24
Finished	Jun 07 07:42:12 PM PDT 24
Peak memory	202804 kb
Host	smart-9e584c58-a8f7-4930-aaac-8887bbf02952
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440782128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1440782128
Directory	/workspace/34.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/34.sram_ctrl_ram_cfg.2609821456
Short name	T568
Test name
Test status
Simulation time	45489540 ps
CPU time	0.78 seconds
Started	Jun 07 07:38:20 PM PDT 24
Finished	Jun 07 07:38:25 PM PDT 24
Peak memory	202888 kb
Host	smart-c33fd3fd-527e-45d3-a63d-a12f5051729a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609821456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2609821456
Directory	/workspace/34.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/34.sram_ctrl_regwen.1080205074
Short name	T247
Test name
Test status
Simulation time	15830317247 ps
CPU time	166.59 seconds
Started	Jun 07 07:38:20 PM PDT 24
Finished	Jun 07 07:41:11 PM PDT 24
Peak memory	284920 kb
Host	smart-64ffdbe1-30ee-4a57-bce5-215dce89b3a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080205074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1080205074
Directory	/workspace/34.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/34.sram_ctrl_smoke.1106555694
Short name	T612
Test name
Test status
Simulation time	281036291 ps
CPU time	147.38 seconds
Started	Jun 07 07:38:11 PM PDT 24
Finished	Jun 07 07:40:41 PM PDT 24
Peak memory	369036 kb
Host	smart-c0b281a3-1759-4561-bb5a-e0fdf716e3ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106555694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1106555694
Directory	/workspace/34.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_all.3407731910
Short name	T641
Test name
Test status
Simulation time	66245975535 ps
CPU time	2567.06 seconds
Started	Jun 07 07:38:27 PM PDT 24
Finished	Jun 07 08:21:17 PM PDT 24
Peak memory	375792 kb
Host	smart-6804ab19-53c5-40ca-b176-e43542a5fbe1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407731910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.3407731910
Directory	/workspace/34.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3990466964
Short name	T524
Test name
Test status
Simulation time	39451906104 ps
CPU time	254.28 seconds
Started	Jun 07 07:38:09 PM PDT 24
Finished	Jun 07 07:42:26 PM PDT 24
Peak memory	202988 kb
Host	smart-14050b3f-1fac-46c6-9ca2-fce1efedc923
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990466964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.3990466964
Directory	/workspace/34.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2711843890
Short name	T521
Test name
Test status
Simulation time	131005514 ps
CPU time	10.39 seconds
Started	Jun 07 07:38:20 PM PDT 24
Finished	Jun 07 07:38:35 PM PDT 24
Peak memory	251812 kb
Host	smart-56ec1f22-a47d-4560-a352-2a6c2d9e4824
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711843890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2711843890
Directory	/workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/35.sram_ctrl_access_during_key_req.3225872733
Short name	T194
Test name
Test status
Simulation time	2882011793 ps
CPU time	583.9 seconds
Started	Jun 07 07:38:36 PM PDT 24
Finished	Jun 07 07:48:22 PM PDT 24
Peak memory	367580 kb
Host	smart-e0809746-7aac-458e-840c-f4e08606a8e4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225872733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.3225872733
Directory	/workspace/35.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/35.sram_ctrl_alert_test.3139860213
Short name	T350
Test name
Test status
Simulation time	59409393 ps
CPU time	0.67 seconds
Started	Jun 07 07:38:43 PM PDT 24
Finished	Jun 07 07:38:48 PM PDT 24
Peak memory	202576 kb
Host	smart-db0e895b-c001-484a-a285-592e39ec957a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139860213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3139860213
Directory	/workspace/35.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.sram_ctrl_bijection.1239708864
Short name	T491
Test name
Test status
Simulation time	4214913605 ps
CPU time	48.62 seconds
Started	Jun 07 07:38:28 PM PDT 24
Finished	Jun 07 07:39:20 PM PDT 24
Peak memory	202980 kb
Host	smart-33c791fd-10bb-4b05-97b1-3441ca81843b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239708864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .1239708864
Directory	/workspace/35.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/35.sram_ctrl_executable.3005382685
Short name	T360
Test name
Test status
Simulation time	451699784 ps
CPU time	127.74 seconds
Started	Jun 07 07:38:36 PM PDT 24
Finished	Jun 07 07:40:46 PM PDT 24
Peak memory	326320 kb
Host	smart-b8130e44-ad6c-4010-96ea-801ed0944763
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005382685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.3005382685
Directory	/workspace/35.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/35.sram_ctrl_lc_escalation.1235042143
Short name	T463
Test name
Test status
Simulation time	1426176786 ps
CPU time	8.42 seconds
Started	Jun 07 07:38:34 PM PDT 24
Finished	Jun 07 07:38:44 PM PDT 24
Peak memory	211072 kb
Host	smart-fc90b35b-c08e-45c2-9ff9-3e75f4373efc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235042143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.1235042143
Directory	/workspace/35.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/35.sram_ctrl_max_throughput.3968208349
Short name	T273
Test name
Test status
Simulation time	151055775 ps
CPU time	1.98 seconds
Started	Jun 07 07:38:27 PM PDT 24
Finished	Jun 07 07:38:32 PM PDT 24
Peak memory	211032 kb
Host	smart-1f628b07-8334-4f73-8173-fb4876d64548
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968208349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3968208349
Directory	/workspace/35.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2216225898
Short name	T789
Test name
Test status
Simulation time	106532977 ps
CPU time	3.07 seconds
Started	Jun 07 07:38:40 PM PDT 24
Finished	Jun 07 07:38:44 PM PDT 24
Peak memory	210988 kb
Host	smart-5aa26e69-b606-409b-ac5e-cad61506aaf0
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216225898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2216225898
Directory	/workspace/35.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_mem_walk.1212493847
Short name	T294
Test name
Test status
Simulation time	1320795476 ps
CPU time	11.06 seconds
Started	Jun 07 07:38:36 PM PDT 24
Finished	Jun 07 07:38:49 PM PDT 24
Peak memory	211064 kb
Host	smart-ea24af63-2a07-4c7b-b5f9-c506007cc3e6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212493847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.1212493847
Directory	/workspace/35.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/35.sram_ctrl_multiple_keys.813226527
Short name	T201
Test name
Test status
Simulation time	1729380765 ps
CPU time	248.93 seconds
Started	Jun 07 07:38:29 PM PDT 24
Finished	Jun 07 07:42:41 PM PDT 24
Peak memory	365504 kb
Host	smart-58d9ec56-ece5-45c1-9511-5565b17cff8e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813226527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.813226527
Directory	/workspace/35.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access.3919468801
Short name	T163
Test name
Test status
Simulation time	948575581 ps
CPU time	17.67 seconds
Started	Jun 07 07:38:26 PM PDT 24
Finished	Jun 07 07:38:47 PM PDT 24
Peak memory	202980 kb
Host	smart-cc868a01-57dc-4498-9a0c-2143e924a973
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919468801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35. sram_ctrl_partial_access.3919468801
Directory	/workspace/35.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3029864894
Short name	T133
Test name
Test status
Simulation time	51667772644 ps
CPU time	384.64 seconds
Started	Jun 07 07:38:27 PM PDT 24
Finished	Jun 07 07:44:55 PM PDT 24
Peak memory	203004 kb
Host	smart-444e717a-eaed-4df3-bd78-56a64fe2150e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029864894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3029864894
Directory	/workspace/35.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/35.sram_ctrl_ram_cfg.2736825314
Short name	T867
Test name
Test status
Simulation time	26544704 ps
CPU time	0.79 seconds
Started	Jun 07 07:38:36 PM PDT 24
Finished	Jun 07 07:38:39 PM PDT 24
Peak memory	202860 kb
Host	smart-4f10c1bb-2354-4f12-92a6-a21b6e52569e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736825314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2736825314
Directory	/workspace/35.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/35.sram_ctrl_regwen.2135359502
Short name	T800
Test name
Test status
Simulation time	4606273203 ps
CPU time	580.84 seconds
Started	Jun 07 07:38:34 PM PDT 24
Finished	Jun 07 07:48:16 PM PDT 24
Peak memory	363908 kb
Host	smart-8ae05489-7223-40ff-a5cb-598f38d102bb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135359502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2135359502
Directory	/workspace/35.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/35.sram_ctrl_smoke.2242342798
Short name	T872
Test name
Test status
Simulation time	1416237596 ps
CPU time	128.9 seconds
Started	Jun 07 07:38:27 PM PDT 24
Finished	Jun 07 07:40:39 PM PDT 24
Peak memory	366436 kb
Host	smart-fa70cf50-e3c8-4e83-84d5-94a229469db2
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242342798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2242342798
Directory	/workspace/35.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all.1831897577
Short name	T442
Test name
Test status
Simulation time	124745581320 ps
CPU time	1627.69 seconds
Started	Jun 07 07:38:35 PM PDT 24
Finished	Jun 07 08:05:45 PM PDT 24
Peak memory	373464 kb
Host	smart-d0493b65-577c-48a6-a5d9-96b353568a4c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831897577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1831897577
Directory	/workspace/35.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3025485302
Short name	T25
Test name
Test status
Simulation time	147214434 ps
CPU time	5.05 seconds
Started	Jun 07 07:38:37 PM PDT 24
Finished	Jun 07 07:38:44 PM PDT 24
Peak memory	214292 kb
Host	smart-116e35ac-6036-4ba1-bd16-5b2c9342896d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3025485302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3025485302
Directory	/workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3541752395
Short name	T366
Test name
Test status
Simulation time	4970725063 ps
CPU time	238.97 seconds
Started	Jun 07 07:38:28 PM PDT 24
Finished	Jun 07 07:42:29 PM PDT 24
Peak memory	202988 kb
Host	smart-32aef9cf-5162-42e3-8ed9-2cfda6351538
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541752395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.3541752395
Directory	/workspace/35.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2431155505
Short name	T906
Test name
Test status
Simulation time	142962949 ps
CPU time	86.07 seconds
Started	Jun 07 07:38:34 PM PDT 24
Finished	Jun 07 07:40:01 PM PDT 24
Peak memory	351868 kb
Host	smart-0e90e1cf-b64e-4caa-9b2b-c405aa56f27c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431155505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.2431155505
Directory	/workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1964255517
Short name	T62
Test name
Test status
Simulation time	25444419360 ps
CPU time	1834.09 seconds
Started	Jun 07 07:38:44 PM PDT 24
Finished	Jun 07 08:09:22 PM PDT 24
Peak memory	376844 kb
Host	smart-9de7d30b-70e4-4f53-a087-b83961a597b8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964255517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.1964255517
Directory	/workspace/36.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/36.sram_ctrl_alert_test.3068574001
Short name	T206
Test name
Test status
Simulation time	13816336 ps
CPU time	0.65 seconds
Started	Jun 07 07:38:52 PM PDT 24
Finished	Jun 07 07:38:55 PM PDT 24
Peak memory	202624 kb
Host	smart-5960f371-dbf3-4ac6-ace9-f14ad4dd21bf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068574001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3068574001
Directory	/workspace/36.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.sram_ctrl_bijection.1072774387
Short name	T871
Test name
Test status
Simulation time	12537124761 ps
CPU time	74.06 seconds
Started	Jun 07 07:38:43 PM PDT 24
Finished	Jun 07 07:40:00 PM PDT 24
Peak memory	202936 kb
Host	smart-4cee711d-4274-4f0e-a56c-8cffe7e2d35f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072774387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .1072774387
Directory	/workspace/36.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/36.sram_ctrl_executable.3635218161
Short name	T398
Test name
Test status
Simulation time	2858748968 ps
CPU time	732.56 seconds
Started	Jun 07 07:38:45 PM PDT 24
Finished	Jun 07 07:51:01 PM PDT 24
Peak memory	372804 kb
Host	smart-befc05e6-44e1-46c3-a5b9-5fa8199eef7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635218161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.3635218161
Directory	/workspace/36.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/36.sram_ctrl_lc_escalation.3198649304
Short name	T785
Test name
Test status
Simulation time	3692231171 ps
CPU time	8.86 seconds
Started	Jun 07 07:38:43 PM PDT 24
Finished	Jun 07 07:38:56 PM PDT 24
Peak memory	215308 kb
Host	smart-869c0cbc-c98b-4101-bff6-ce165ad109ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198649304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.3198649304
Directory	/workspace/36.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/36.sram_ctrl_max_throughput.2176971870
Short name	T813
Test name
Test status
Simulation time	37058680 ps
CPU time	1.34 seconds
Started	Jun 07 07:38:44 PM PDT 24
Finished	Jun 07 07:38:49 PM PDT 24
Peak memory	211092 kb
Host	smart-a17b0399-d40d-412a-b921-8767b5952582
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176971870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.2176971870
Directory	/workspace/36.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3439498638
Short name	T798
Test name
Test status
Simulation time	66574616 ps
CPU time	4.8 seconds
Started	Jun 07 07:38:50 PM PDT 24
Finished	Jun 07 07:38:57 PM PDT 24
Peak memory	211096 kb
Host	smart-332c4f35-fbc5-42ec-bc99-1f793a28fa85
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439498638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.3439498638
Directory	/workspace/36.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_mem_walk.2804455794
Short name	T383
Test name
Test status
Simulation time	1146819974 ps
CPU time	6.13 seconds
Started	Jun 07 07:38:51 PM PDT 24
Finished	Jun 07 07:39:00 PM PDT 24
Peak memory	211100 kb
Host	smart-bc89d444-28cd-4ef8-8f64-e1dca2658d85
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804455794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.2804455794
Directory	/workspace/36.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/36.sram_ctrl_multiple_keys.356994764
Short name	T589
Test name
Test status
Simulation time	9093366880 ps
CPU time	405.21 seconds
Started	Jun 07 07:38:43 PM PDT 24
Finished	Jun 07 07:45:31 PM PDT 24
Peak memory	370056 kb
Host	smart-d4ada601-4f28-42b9-925f-a1a7465d5820
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356994764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip le_keys.356994764
Directory	/workspace/36.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access.4263809253
Short name	T795
Test name
Test status
Simulation time	602154960 ps
CPU time	91.46 seconds
Started	Jun 07 07:38:43 PM PDT 24
Finished	Jun 07 07:40:17 PM PDT 24
Peak memory	357224 kb
Host	smart-513bc976-1e12-4a7a-8ac7-a6038f529b5d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263809253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.4263809253
Directory	/workspace/36.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1003360305
Short name	T621
Test name
Test status
Simulation time	15083927953 ps
CPU time	346.4 seconds
Started	Jun 07 07:38:45 PM PDT 24
Finished	Jun 07 07:44:35 PM PDT 24
Peak memory	202952 kb
Host	smart-55a2e4a9-a36b-4714-b9c3-095a1e4307b0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003360305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.1003360305
Directory	/workspace/36.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/36.sram_ctrl_ram_cfg.3622123837
Short name	T486
Test name
Test status
Simulation time	28604512 ps
CPU time	0.77 seconds
Started	Jun 07 07:38:51 PM PDT 24
Finished	Jun 07 07:38:55 PM PDT 24
Peak memory	202904 kb
Host	smart-fb8fa9b2-947d-4acb-b08f-6c772e3ac33d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622123837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3622123837
Directory	/workspace/36.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/36.sram_ctrl_regwen.480919120
Short name	T759
Test name
Test status
Simulation time	16080111817 ps
CPU time	251.89 seconds
Started	Jun 07 07:38:44 PM PDT 24
Finished	Jun 07 07:42:59 PM PDT 24
Peak memory	365600 kb
Host	smart-672d11da-78b0-4849-befb-75c5183e498b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480919120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.480919120
Directory	/workspace/36.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/36.sram_ctrl_smoke.2077589122
Short name	T204
Test name
Test status
Simulation time	147246568 ps
CPU time	8.83 seconds
Started	Jun 07 07:38:42 PM PDT 24
Finished	Jun 07 07:38:53 PM PDT 24
Peak memory	202872 kb
Host	smart-bef81141-f53a-46d4-8549-90df43cba989
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077589122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2077589122
Directory	/workspace/36.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all.4100009726
Short name	T420
Test name
Test status
Simulation time	23562160105 ps
CPU time	198.47 seconds
Started	Jun 07 07:38:49 PM PDT 24
Finished	Jun 07 07:42:10 PM PDT 24
Peak memory	286316 kb
Host	smart-55d2a10f-247f-4d69-86fe-b7944d5ff06a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100009726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.4100009726
Directory	/workspace/36.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1651539223
Short name	T58
Test name
Test status
Simulation time	1495353231 ps
CPU time	113.78 seconds
Started	Jun 07 07:38:49 PM PDT 24
Finished	Jun 07 07:40:44 PM PDT 24
Peak memory	339100 kb
Host	smart-1ee03e99-7829-451e-a24c-15da5c940399
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1651539223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.1651539223
Directory	/workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1249758186
Short name	T441
Test name
Test status
Simulation time	4966607912 ps
CPU time	236.01 seconds
Started	Jun 07 07:38:44 PM PDT 24
Finished	Jun 07 07:42:43 PM PDT 24
Peak memory	202748 kb
Host	smart-433e5e77-da42-4141-aff9-890ada8551ab
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249758186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.1249758186
Directory	/workspace/36.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3831751915
Short name	T614
Test name
Test status
Simulation time	138358549 ps
CPU time	12.55 seconds
Started	Jun 07 07:38:44 PM PDT 24
Finished	Jun 07 07:39:00 PM PDT 24
Peak memory	251496 kb
Host	smart-eef814c3-ef4c-41b6-8bad-b2d7e8ad95df
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831751915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.3831751915
Directory	/workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/37.sram_ctrl_access_during_key_req.2241085079
Short name	T160
Test name
Test status
Simulation time	4871346515 ps
CPU time	480.91 seconds
Started	Jun 07 07:38:59 PM PDT 24
Finished	Jun 07 07:47:03 PM PDT 24
Peak memory	373652 kb
Host	smart-3013ee54-33c4-4677-86ff-22d85254ed15
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241085079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.2241085079
Directory	/workspace/37.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/37.sram_ctrl_alert_test.636327346
Short name	T893
Test name
Test status
Simulation time	32527549 ps
CPU time	0.67 seconds
Started	Jun 07 07:39:05 PM PDT 24
Finished	Jun 07 07:39:08 PM PDT 24
Peak memory	202020 kb
Host	smart-ba4208d5-d042-4898-9e81-ef470d37dd53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636327346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.636327346
Directory	/workspace/37.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.sram_ctrl_bijection.2271125463
Short name	T833
Test name
Test status
Simulation time	589823091 ps
CPU time	38.9 seconds
Started	Jun 07 07:38:50 PM PDT 24
Finished	Jun 07 07:39:31 PM PDT 24
Peak memory	202964 kb
Host	smart-34693e45-bba7-46df-ab39-c0c6b9c5e298
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271125463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2271125463
Directory	/workspace/37.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/37.sram_ctrl_executable.2016856808
Short name	T170
Test name
Test status
Simulation time	26983544167 ps
CPU time	544.96 seconds
Started	Jun 07 07:38:58 PM PDT 24
Finished	Jun 07 07:48:05 PM PDT 24
Peak memory	365980 kb
Host	smart-c2262731-39f9-4f12-9268-a31387925596
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016856808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab le.2016856808
Directory	/workspace/37.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/37.sram_ctrl_lc_escalation.452953717
Short name	T290
Test name
Test status
Simulation time	297447533 ps
CPU time	1.4 seconds
Started	Jun 07 07:38:57 PM PDT 24
Finished	Jun 07 07:39:01 PM PDT 24
Peak memory	202960 kb
Host	smart-3c4419a8-6773-4829-b650-02292a69fda6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452953717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.452953717
Directory	/workspace/37.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/37.sram_ctrl_max_throughput.3999162000
Short name	T670
Test name
Test status
Simulation time	45226562 ps
CPU time	1.64 seconds
Started	Jun 07 07:38:57 PM PDT 24
Finished	Jun 07 07:39:01 PM PDT 24
Peak memory	211124 kb
Host	smart-5e7bbe23-5b75-453c-b214-9775072bc6d1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999162000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.3999162000
Directory	/workspace/37.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_partial_access.257406761
Short name	T132
Test name
Test status
Simulation time	94487792 ps
CPU time	3.16 seconds
Started	Jun 07 07:39:06 PM PDT 24
Finished	Jun 07 07:39:12 PM PDT 24
Peak memory	211120 kb
Host	smart-cd8634d8-2701-4f9f-9744-3277bb0dfd31
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257406761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.257406761
Directory	/workspace/37.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_mem_walk.3785379642
Short name	T249
Test name
Test status
Simulation time	658293848 ps
CPU time	12.89 seconds
Started	Jun 07 07:38:57 PM PDT 24
Finished	Jun 07 07:39:12 PM PDT 24
Peak memory	210992 kb
Host	smart-7896b99e-8023-4a9b-9edb-edfdf493be6b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785379642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.3785379642
Directory	/workspace/37.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/37.sram_ctrl_multiple_keys.2909944617
Short name	T796
Test name
Test status
Simulation time	6790835304 ps
CPU time	217.64 seconds
Started	Jun 07 07:38:52 PM PDT 24
Finished	Jun 07 07:42:32 PM PDT 24
Peak memory	346676 kb
Host	smart-a1997593-06da-4263-855f-55de36dd97ed
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909944617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.2909944617
Directory	/workspace/37.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access.1119651520
Short name	T399
Test name
Test status
Simulation time	186558171 ps
CPU time	74.16 seconds
Started	Jun 07 07:38:50 PM PDT 24
Finished	Jun 07 07:40:06 PM PDT 24
Peak memory	335800 kb
Host	smart-768a1032-3337-4e44-a779-24fd94bf4e60
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119651520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.1119651520
Directory	/workspace/37.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3824589684
Short name	T660
Test name
Test status
Simulation time	237408438081 ps
CPU time	455.84 seconds
Started	Jun 07 07:38:57 PM PDT 24
Finished	Jun 07 07:46:35 PM PDT 24
Peak memory	203012 kb
Host	smart-79b61391-cf5d-4653-9284-24cb1cc0b487
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824589684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.3824589684
Directory	/workspace/37.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/37.sram_ctrl_regwen.719043867
Short name	T516
Test name
Test status
Simulation time	534640332 ps
CPU time	61.09 seconds
Started	Jun 07 07:38:58 PM PDT 24
Finished	Jun 07 07:40:02 PM PDT 24
Peak memory	307288 kb
Host	smart-ef867cdc-168d-479a-b683-47eecf262f43
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719043867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.719043867
Directory	/workspace/37.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/37.sram_ctrl_smoke.2076831666
Short name	T916
Test name
Test status
Simulation time	1708637742 ps
CPU time	10.4 seconds
Started	Jun 07 07:38:49 PM PDT 24
Finished	Jun 07 07:39:02 PM PDT 24
Peak memory	202800 kb
Host	smart-7059d9ea-155e-4234-b487-96607e4dbc11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076831666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2076831666
Directory	/workspace/37.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all.3051143911
Short name	T508
Test name
Test status
Simulation time	232513569222 ps
CPU time	4008.55 seconds
Started	Jun 07 07:39:04 PM PDT 24
Finished	Jun 07 08:45:54 PM PDT 24
Peak memory	383988 kb
Host	smart-9d389c9f-d499-41ea-b5c1-fc3998731d49
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051143911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3051143911
Directory	/workspace/37.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.330950150
Short name	T107
Test name
Test status
Simulation time	3861924984 ps
CPU time	119.89 seconds
Started	Jun 07 07:39:05 PM PDT 24
Finished	Jun 07 07:41:07 PM PDT 24
Peak memory	317616 kb
Host	smart-f4a4602c-5cf1-4cc0-9d82-861e06166477
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=330950150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.330950150
Directory	/workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1149511143
Short name	T45
Test name
Test status
Simulation time	4715162039 ps
CPU time	245.08 seconds
Started	Jun 07 07:38:51 PM PDT 24
Finished	Jun 07 07:42:59 PM PDT 24
Peak memory	203020 kb
Host	smart-c1d3ae6e-2c08-4f32-aad4-dd23c8324e9c
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149511143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1149511143
Directory	/workspace/37.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.532519279
Short name	T729
Test name
Test status
Simulation time	271930564 ps
CPU time	102.31 seconds
Started	Jun 07 07:38:59 PM PDT 24
Finished	Jun 07 07:40:44 PM PDT 24
Peak memory	350832 kb
Host	smart-75e418df-3ff1-4a73-b246-1ea5cec058ea
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532519279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.532519279
Directory	/workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/38.sram_ctrl_access_during_key_req.258168415
Short name	T356
Test name
Test status
Simulation time	39840085572 ps
CPU time	530.93 seconds
Started	Jun 07 07:39:12 PM PDT 24
Finished	Jun 07 07:48:05 PM PDT 24
Peak memory	372616 kb
Host	smart-e8ee1bad-0fc5-440a-8a64-1a964dcdf324
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258168415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 38.sram_ctrl_access_during_key_req.258168415
Directory	/workspace/38.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/38.sram_ctrl_alert_test.911193944
Short name	T852
Test name
Test status
Simulation time	13786669 ps
CPU time	0.68 seconds
Started	Jun 07 07:39:22 PM PDT 24
Finished	Jun 07 07:39:25 PM PDT 24
Peak memory	202672 kb
Host	smart-d448cd7c-193d-4d76-bda8-8f3ae16f4e46
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911193944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.911193944
Directory	/workspace/38.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.sram_ctrl_bijection.484553354
Short name	T431
Test name
Test status
Simulation time	2226894245 ps
CPU time	17.69 seconds
Started	Jun 07 07:39:03 PM PDT 24
Finished	Jun 07 07:39:21 PM PDT 24
Peak memory	202912 kb
Host	smart-6f57e0b5-4358-4e4d-8d62-fa226390206f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484553354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection. 484553354
Directory	/workspace/38.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/38.sram_ctrl_executable.1841149409
Short name	T806
Test name
Test status
Simulation time	6067628744 ps
CPU time	314.67 seconds
Started	Jun 07 07:39:12 PM PDT 24
Finished	Jun 07 07:44:29 PM PDT 24
Peak memory	374508 kb
Host	smart-5c6cbd6b-f467-4900-b806-3a847108e2e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841149409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.1841149409
Directory	/workspace/38.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/38.sram_ctrl_lc_escalation.4062801500
Short name	T691
Test name
Test status
Simulation time	1689182175 ps
CPU time	4.91 seconds
Started	Jun 07 07:39:13 PM PDT 24
Finished	Jun 07 07:39:21 PM PDT 24
Peak memory	202912 kb
Host	smart-c9b9d8b3-09a5-4dc8-a5c3-2ee888123543
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062801500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.4062801500
Directory	/workspace/38.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/38.sram_ctrl_max_throughput.1071524095
Short name	T434
Test name
Test status
Simulation time	34945735 ps
CPU time	1 seconds
Started	Jun 07 07:39:14 PM PDT 24
Finished	Jun 07 07:39:17 PM PDT 24
Peak memory	202708 kb
Host	smart-fca2c346-2c3d-43df-85c1-fb9a622959fd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071524095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_max_throughput.1071524095
Directory	/workspace/38.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1611322003
Short name	T602
Test name
Test status
Simulation time	112520905 ps
CPU time	3.19 seconds
Started	Jun 07 07:39:14 PM PDT 24
Finished	Jun 07 07:39:20 PM PDT 24
Peak memory	211144 kb
Host	smart-648e27b9-c60d-4d3a-867e-3bc0792f5506
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611322003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.1611322003
Directory	/workspace/38.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_mem_walk.1764576616
Short name	T411
Test name
Test status
Simulation time	1341354190 ps
CPU time	11.8 seconds
Started	Jun 07 07:39:12 PM PDT 24
Finished	Jun 07 07:39:27 PM PDT 24
Peak memory	211032 kb
Host	smart-4ac4e7a7-3b6a-44b4-bec1-0c274eea08b4
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764576616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1764576616
Directory	/workspace/38.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/38.sram_ctrl_multiple_keys.1604996809
Short name	T848
Test name
Test status
Simulation time	81623503107 ps
CPU time	1542.75 seconds
Started	Jun 07 07:39:08 PM PDT 24
Finished	Jun 07 08:04:53 PM PDT 24
Peak memory	374824 kb
Host	smart-a719a5e5-0f5f-4d44-81f4-d1813304dcd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604996809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.1604996809
Directory	/workspace/38.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access.3405461753
Short name	T866
Test name
Test status
Simulation time	3000641052 ps
CPU time	137.98 seconds
Started	Jun 07 07:39:13 PM PDT 24
Finished	Jun 07 07:41:33 PM PDT 24
Peak memory	362336 kb
Host	smart-b2e7fa92-d489-4893-8f03-c1d2b2dcd1fc
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405461753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3405461753
Directory	/workspace/38.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2298489340
Short name	T631
Test name
Test status
Simulation time	15237469524 ps
CPU time	284.96 seconds
Started	Jun 07 07:39:11 PM PDT 24
Finished	Jun 07 07:43:58 PM PDT 24
Peak memory	203020 kb
Host	smart-6417b91a-b959-4040-bfae-f6b29830cd64
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298489340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.2298489340
Directory	/workspace/38.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/38.sram_ctrl_ram_cfg.3147227895
Short name	T200
Test name
Test status
Simulation time	30274509 ps
CPU time	0.77 seconds
Started	Jun 07 07:39:13 PM PDT 24
Finished	Jun 07 07:39:16 PM PDT 24
Peak memory	202912 kb
Host	smart-cfe21f8e-6d6c-48df-a280-c18bc745ec5b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147227895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3147227895
Directory	/workspace/38.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/38.sram_ctrl_regwen.942335931
Short name	T873
Test name
Test status
Simulation time	12397361560 ps
CPU time	719.58 seconds
Started	Jun 07 07:39:11 PM PDT 24
Finished	Jun 07 07:51:13 PM PDT 24
Peak memory	371544 kb
Host	smart-df79223d-2bae-4f96-aef9-1cd8ddef6fbc
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942335931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.942335931
Directory	/workspace/38.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/38.sram_ctrl_smoke.3492001129
Short name	T845
Test name
Test status
Simulation time	362552908 ps
CPU time	27.26 seconds
Started	Jun 07 07:39:05 PM PDT 24
Finished	Jun 07 07:39:33 PM PDT 24
Peak memory	282640 kb
Host	smart-d67a5b3e-875e-4be2-ac30-f22e741bcfa0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492001129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3492001129
Directory	/workspace/38.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all.3328561827
Short name	T838
Test name
Test status
Simulation time	37249510894 ps
CPU time	2798.87 seconds
Started	Jun 07 07:39:21 PM PDT 24
Finished	Jun 07 08:26:02 PM PDT 24
Peak memory	376864 kb
Host	smart-04733854-4487-4e48-8cd9-a525946e0368
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328561827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3328561827
Directory	/workspace/38.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3325021749
Short name	T108
Test name
Test status
Simulation time	4879291036 ps
CPU time	78.34 seconds
Started	Jun 07 07:39:18 PM PDT 24
Finished	Jun 07 07:40:38 PM PDT 24
Peak memory	310300 kb
Host	smart-a193e774-424a-41b0-807f-db48a87173ed
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3325021749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3325021749
Directory	/workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.sram_ctrl_stress_pipeline.2796514280
Short name	T102
Test name
Test status
Simulation time	2066877001 ps
CPU time	199.76 seconds
Started	Jun 07 07:39:12 PM PDT 24
Finished	Jun 07 07:42:34 PM PDT 24
Peak memory	202928 kb
Host	smart-24d9fdad-d4c3-49ab-845d-930531c9e6b0
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796514280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.2796514280
Directory	/workspace/38.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3709773769
Short name	T713
Test name
Test status
Simulation time	302154698 ps
CPU time	67.42 seconds
Started	Jun 07 07:39:13 PM PDT 24
Finished	Jun 07 07:40:23 PM PDT 24
Peak memory	317396 kb
Host	smart-27cc452f-7aa4-456d-be15-644e4979fa2e
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709773769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3709773769
Directory	/workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/39.sram_ctrl_access_during_key_req.2225296266
Short name	T823
Test name
Test status
Simulation time	3917878159 ps
CPU time	1889.03 seconds
Started	Jun 07 07:39:28 PM PDT 24
Finished	Jun 07 08:10:59 PM PDT 24
Peak memory	374484 kb
Host	smart-d1f42bd8-2b40-4f1d-86cf-c0a6fa85d547
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225296266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2225296266
Directory	/workspace/39.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/39.sram_ctrl_alert_test.2048349649
Short name	T15
Test name
Test status
Simulation time	15405050 ps
CPU time	0.71 seconds
Started	Jun 07 07:39:35 PM PDT 24
Finished	Jun 07 07:39:37 PM PDT 24
Peak memory	202624 kb
Host	smart-4ce7f65b-2af7-4d03-9bea-ae15ebf76850
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048349649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2048349649
Directory	/workspace/39.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.sram_ctrl_bijection.3628772622
Short name	T642
Test name
Test status
Simulation time	3780181796 ps
CPU time	45 seconds
Started	Jun 07 07:39:19 PM PDT 24
Finished	Jun 07 07:40:06 PM PDT 24
Peak memory	202948 kb
Host	smart-be6bc819-f80d-4447-8721-a50f548cf8f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628772622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .3628772622
Directory	/workspace/39.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/39.sram_ctrl_executable.3301819396
Short name	T225
Test name
Test status
Simulation time	956057765 ps
CPU time	229.47 seconds
Started	Jun 07 07:39:32 PM PDT 24
Finished	Jun 07 07:43:23 PM PDT 24
Peak memory	368992 kb
Host	smart-cc86867a-2197-4f85-bab0-b5fcb481c19a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301819396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.3301819396
Directory	/workspace/39.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/39.sram_ctrl_lc_escalation.1705470775
Short name	T825
Test name
Test status
Simulation time	577377368 ps
CPU time	3.97 seconds
Started	Jun 07 07:39:28 PM PDT 24
Finished	Jun 07 07:39:34 PM PDT 24
Peak memory	202876 kb
Host	smart-70adf23b-f560-458a-88b5-855bccff8071
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705470775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.1705470775
Directory	/workspace/39.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/39.sram_ctrl_max_throughput.2118604725
Short name	T461
Test name
Test status
Simulation time	262782084 ps
CPU time	14.79 seconds
Started	Jun 07 07:39:27 PM PDT 24
Finished	Jun 07 07:39:43 PM PDT 24
Peak memory	258136 kb
Host	smart-b6ad7334-8b61-4c1a-9a13-29eb1a06d89f
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118604725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.2118604725
Directory	/workspace/39.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_partial_access.3647495518
Short name	T256
Test name
Test status
Simulation time	385445678 ps
CPU time	3.49 seconds
Started	Jun 07 07:39:29 PM PDT 24
Finished	Jun 07 07:39:35 PM PDT 24
Peak memory	211132 kb
Host	smart-cc3e1618-e05f-428a-9d8c-ad3ffd77d33c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647495518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3647495518
Directory	/workspace/39.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_mem_walk.3527247097
Short name	T413
Test name
Test status
Simulation time	976944252 ps
CPU time	5.66 seconds
Started	Jun 07 07:39:27 PM PDT 24
Finished	Jun 07 07:39:34 PM PDT 24
Peak memory	211028 kb
Host	smart-666a50d8-b37d-4bc6-a8f2-74b90953ce05
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527247097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.3527247097
Directory	/workspace/39.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/39.sram_ctrl_multiple_keys.2315605842
Short name	T689
Test name
Test status
Simulation time	4986100025 ps
CPU time	2357.9 seconds
Started	Jun 07 07:39:19 PM PDT 24
Finished	Jun 07 08:18:39 PM PDT 24
Peak memory	371672 kb
Host	smart-d1167a98-a36f-4909-9a01-0d6e72c90ab9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315605842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2315605842
Directory	/workspace/39.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access.1410464787
Short name	T512
Test name
Test status
Simulation time	4809066412 ps
CPU time	21.07 seconds
Started	Jun 07 07:39:23 PM PDT 24
Finished	Jun 07 07:39:46 PM PDT 24
Peak memory	202972 kb
Host	smart-40b8d817-99d9-48e7-b183-7ac85a22e9d9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410464787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.1410464787
Directory	/workspace/39.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4096485352
Short name	T734
Test name
Test status
Simulation time	58633023898 ps
CPU time	410.98 seconds
Started	Jun 07 07:39:29 PM PDT 24
Finished	Jun 07 07:46:22 PM PDT 24
Peak memory	202992 kb
Host	smart-d2d71cbc-515b-4ec9-b14b-da1d990020b9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096485352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4096485352
Directory	/workspace/39.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/39.sram_ctrl_ram_cfg.3537319274
Short name	T330
Test name
Test status
Simulation time	46663093 ps
CPU time	0.73 seconds
Started	Jun 07 07:39:29 PM PDT 24
Finished	Jun 07 07:39:32 PM PDT 24
Peak memory	202908 kb
Host	smart-3b81a2e9-aba8-4a81-9d45-9008d12a4d6b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537319274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3537319274
Directory	/workspace/39.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/39.sram_ctrl_regwen.3728515264
Short name	T53
Test name
Test status
Simulation time	4336986745 ps
CPU time	1848.75 seconds
Started	Jun 07 07:39:28 PM PDT 24
Finished	Jun 07 08:10:19 PM PDT 24
Peak memory	371056 kb
Host	smart-b1fe2419-0890-4950-a23d-c113badf2b77
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728515264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3728515264
Directory	/workspace/39.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/39.sram_ctrl_smoke.2861402243
Short name	T849
Test name
Test status
Simulation time	36675290 ps
CPU time	1.53 seconds
Started	Jun 07 07:39:22 PM PDT 24
Finished	Jun 07 07:39:26 PM PDT 24
Peak memory	202912 kb
Host	smart-247d457c-edb6-41c9-80e4-b91ac9a1227f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861402243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2861402243
Directory	/workspace/39.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all.2664916720
Short name	T348
Test name
Test status
Simulation time	55161660289 ps
CPU time	1712.94 seconds
Started	Jun 07 07:39:37 PM PDT 24
Finished	Jun 07 08:08:13 PM PDT 24
Peak memory	376852 kb
Host	smart-7a613126-bedd-451e-8ad0-ed0370c33847
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664916720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2664916720
Directory	/workspace/39.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2711877161
Short name	T48
Test name
Test status
Simulation time	7600756062 ps
CPU time	438.06 seconds
Started	Jun 07 07:39:35 PM PDT 24
Finished	Jun 07 07:46:55 PM PDT 24
Peak memory	362596 kb
Host	smart-ded59e9c-7995-4386-b97a-a5b8ad45e004
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2711877161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2711877161
Directory	/workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.sram_ctrl_stress_pipeline.2860077041
Short name	T409
Test name
Test status
Simulation time	4235642860 ps
CPU time	230.33 seconds
Started	Jun 07 07:39:20 PM PDT 24
Finished	Jun 07 07:43:12 PM PDT 24
Peak memory	202980 kb
Host	smart-66b25f5b-13e9-4c37-ad1b-ee813e4abf2e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860077041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.2860077041
Directory	/workspace/39.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3331410182
Short name	T462
Test name
Test status
Simulation time	390189995 ps
CPU time	25.13 seconds
Started	Jun 07 07:39:29 PM PDT 24
Finished	Jun 07 07:39:56 PM PDT 24
Peak memory	291448 kb
Host	smart-a79f18aa-bea8-4715-86a8-ca83eb16e0df
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331410182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3331410182
Directory	/workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/4.sram_ctrl_access_during_key_req.4190251838
Short name	T576
Test name
Test status
Simulation time	7085198801 ps
CPU time	763 seconds
Started	Jun 07 07:33:50 PM PDT 24
Finished	Jun 07 07:46:36 PM PDT 24
Peak memory	372428 kb
Host	smart-a0e51a36-2859-4a14-95f1-974a7d49af16
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190251838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.4190251838
Directory	/workspace/4.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/4.sram_ctrl_alert_test.1523863108
Short name	T185
Test name
Test status
Simulation time	15056079 ps
CPU time	0.65 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:48 PM PDT 24
Peak memory	202616 kb
Host	smart-c32d669a-9687-4308-a21d-da368ae08f17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523863108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1523863108
Directory	/workspace/4.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.sram_ctrl_bijection.3464502868
Short name	T159
Test name
Test status
Simulation time	10366690591 ps
CPU time	89.53 seconds
Started	Jun 07 07:33:49 PM PDT 24
Finished	Jun 07 07:35:21 PM PDT 24
Peak memory	202984 kb
Host	smart-01df7f5c-67cd-452c-ad24-d2b8fd560156
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464502868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 3464502868
Directory	/workspace/4.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/4.sram_ctrl_executable.1223738507
Short name	T718
Test name
Test status
Simulation time	17255326582 ps
CPU time	1367.23 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:56:34 PM PDT 24
Peak memory	374852 kb
Host	smart-50d18db4-dd11-48d3-8949-d995bbbf6e11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223738507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.1223738507
Directory	/workspace/4.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/4.sram_ctrl_lc_escalation.1295083423
Short name	T403
Test name
Test status
Simulation time	163477235 ps
CPU time	2.21 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	202900 kb
Host	smart-933f63d7-ec76-4674-8314-115d1b430780
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295083423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc alation.1295083423
Directory	/workspace/4.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/4.sram_ctrl_max_throughput.746126264
Short name	T168
Test name
Test status
Simulation time	521265426 ps
CPU time	14.11 seconds
Started	Jun 07 07:33:38 PM PDT 24
Finished	Jun 07 07:33:57 PM PDT 24
Peak memory	255804 kb
Host	smart-685a659c-bc83-4883-8408-0014886cd4f6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746126264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.sram_ctrl_max_throughput.746126264
Directory	/workspace/4.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1922864381
Short name	T594
Test name
Test status
Simulation time	1010021978 ps
CPU time	3.78 seconds
Started	Jun 07 07:33:49 PM PDT 24
Finished	Jun 07 07:33:56 PM PDT 24
Peak memory	211100 kb
Host	smart-0eb0957e-78e8-4a51-9b17-afbcb03bbd3a
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922864381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.1922864381
Directory	/workspace/4.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_mem_walk.3227815719
Short name	T577
Test name
Test status
Simulation time	289633172 ps
CPU time	8.29 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:55 PM PDT 24
Peak memory	211080 kb
Host	smart-4edaa70b-f870-4a58-8086-f96581d52a0a
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227815719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3227815719
Directory	/workspace/4.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/4.sram_ctrl_multiple_keys.2043470404
Short name	T57
Test name
Test status
Simulation time	13316155919 ps
CPU time	1790.88 seconds
Started	Jun 07 07:33:41 PM PDT 24
Finished	Jun 07 08:03:36 PM PDT 24
Peak memory	374028 kb
Host	smart-66511f14-d7f3-476a-ac6a-4bde965d6520
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043470404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.2043470404
Directory	/workspace/4.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access.2960131195
Short name	T440
Test name
Test status
Simulation time	255006493 ps
CPU time	4.5 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	222060 kb
Host	smart-9c7160c7-2f37-4550-bbfd-a9a04202c14b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960131195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2960131195
Directory	/workspace/4.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3571281394
Short name	T433
Test name
Test status
Simulation time	9084525683 ps
CPU time	336.74 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:39:26 PM PDT 24
Peak memory	203044 kb
Host	smart-3d4cf4a4-0756-44ac-a0e1-c5182cfbb0fa
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571281394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3571281394
Directory	/workspace/4.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/4.sram_ctrl_ram_cfg.643008024
Short name	T792
Test name
Test status
Simulation time	160235545 ps
CPU time	0.75 seconds
Started	Jun 07 07:33:47 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	202448 kb
Host	smart-1d4dd2bd-c5ad-40a4-b258-50b416fd2352
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643008024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.643008024
Directory	/workspace/4.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/4.sram_ctrl_regwen.1332365900
Short name	T715
Test name
Test status
Simulation time	83641304723 ps
CPU time	1583.39 seconds
Started	Jun 07 07:33:39 PM PDT 24
Finished	Jun 07 08:00:07 PM PDT 24
Peak memory	375860 kb
Host	smart-c66c03d8-3d9d-4cd9-ac43-0a9f56c9bad3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332365900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1332365900
Directory	/workspace/4.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/4.sram_ctrl_smoke.2989120707
Short name	T500
Test name
Test status
Simulation time	470766743 ps
CPU time	2.13 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:33:51 PM PDT 24
Peak memory	202848 kb
Host	smart-90bd558e-24ca-4f6b-84f1-185842f905dd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989120707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2989120707
Directory	/workspace/4.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3051173579
Short name	T885
Test name
Test status
Simulation time	5413225517 ps
CPU time	47.24 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:34:34 PM PDT 24
Peak memory	249792 kb
Host	smart-a2f3b5bb-22e7-462b-8fd9-98cc82959982
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3051173579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3051173579
Directory	/workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3064399053
Short name	T692
Test name
Test status
Simulation time	4467869644 ps
CPU time	173.24 seconds
Started	Jun 07 07:33:41 PM PDT 24
Finished	Jun 07 07:36:39 PM PDT 24
Peak memory	203008 kb
Host	smart-c4e38e5a-aae9-48b1-ae84-5a7fc026c1ad
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064399053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3064399053
Directory	/workspace/4.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3975735140
Short name	T842
Test name
Test status
Simulation time	159675354 ps
CPU time	75.71 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:35:04 PM PDT 24
Peak memory	370340 kb
Host	smart-540a313d-d535-49d9-ab79-a72f10bceaff
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975735140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3975735140
Directory	/workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/40.sram_ctrl_access_during_key_req.1730725072
Short name	T155
Test name
Test status
Simulation time	522509884 ps
CPU time	186.9 seconds
Started	Jun 07 07:39:47 PM PDT 24
Finished	Jun 07 07:42:55 PM PDT 24
Peak memory	364460 kb
Host	smart-f64c8eeb-b7ba-41f4-8473-d042e2ecc211
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730725072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.1730725072
Directory	/workspace/40.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/40.sram_ctrl_alert_test.1463922418
Short name	T214
Test name
Test status
Simulation time	19091951 ps
CPU time	0.69 seconds
Started	Jun 07 07:39:55 PM PDT 24
Finished	Jun 07 07:39:57 PM PDT 24
Peak memory	202592 kb
Host	smart-c48d37b1-271e-42a1-86a2-c2f27c3465ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463922418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1463922418
Directory	/workspace/40.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.sram_ctrl_bijection.2742449362
Short name	T473
Test name
Test status
Simulation time	2619654186 ps
CPU time	58.45 seconds
Started	Jun 07 07:39:36 PM PDT 24
Finished	Jun 07 07:40:37 PM PDT 24
Peak memory	203032 kb
Host	smart-9ddb441f-1f63-43d7-b03b-e596d3600612
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742449362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .2742449362
Directory	/workspace/40.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/40.sram_ctrl_executable.3727996168
Short name	T238
Test name
Test status
Simulation time	6112892351 ps
CPU time	976.29 seconds
Started	Jun 07 07:39:45 PM PDT 24
Finished	Jun 07 07:56:03 PM PDT 24
Peak memory	371680 kb
Host	smart-e0f96935-4faf-4a9f-9449-7efd3a4babf3
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727996168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3727996168
Directory	/workspace/40.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/40.sram_ctrl_lc_escalation.3585211293
Short name	T446
Test name
Test status
Simulation time	1205396475 ps
CPU time	6.77 seconds
Started	Jun 07 07:39:44 PM PDT 24
Finished	Jun 07 07:39:52 PM PDT 24
Peak memory	202900 kb
Host	smart-d49c8e56-2ede-459b-9531-75ce13435990
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585211293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.3585211293
Directory	/workspace/40.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/40.sram_ctrl_max_throughput.341894708
Short name	T662
Test name
Test status
Simulation time	154806384 ps
CPU time	135.07 seconds
Started	Jun 07 07:39:37 PM PDT 24
Finished	Jun 07 07:41:55 PM PDT 24
Peak memory	369560 kb
Host	smart-f0843b10-12eb-4380-89c9-48e3a5fb3424
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341894708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.341894708
Directory	/workspace/40.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3811548964
Short name	T252
Test name
Test status
Simulation time	1685075889 ps
CPU time	5.49 seconds
Started	Jun 07 07:39:47 PM PDT 24
Finished	Jun 07 07:39:54 PM PDT 24
Peak memory	211136 kb
Host	smart-80582514-34e4-4e7e-a9d3-a04307d7dc73
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811548964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.3811548964
Directory	/workspace/40.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_mem_walk.377058693
Short name	T678
Test name
Test status
Simulation time	303875478 ps
CPU time	6.23 seconds
Started	Jun 07 07:39:44 PM PDT 24
Finished	Jun 07 07:39:51 PM PDT 24
Peak memory	211072 kb
Host	smart-7388c5e3-e8e4-403c-885d-2e36e6f7aa4e
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377058693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.377058693
Directory	/workspace/40.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/40.sram_ctrl_multiple_keys.3193518099
Short name	T295
Test name
Test status
Simulation time	9404915431 ps
CPU time	423.82 seconds
Started	Jun 07 07:39:35 PM PDT 24
Finished	Jun 07 07:46:40 PM PDT 24
Peak memory	358092 kb
Host	smart-706eb306-f58f-49ed-9cdc-60cf2d334cd5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193518099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.3193518099
Directory	/workspace/40.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access.3869301623
Short name	T690
Test name
Test status
Simulation time	745693273 ps
CPU time	1.46 seconds
Started	Jun 07 07:39:38 PM PDT 24
Finished	Jun 07 07:39:42 PM PDT 24
Peak memory	202944 kb
Host	smart-bbfe762f-be45-4b40-bb79-f53b7ae0092a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869301623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40. sram_ctrl_partial_access.3869301623
Directory	/workspace/40.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3924956290
Short name	T681
Test name
Test status
Simulation time	3512598712 ps
CPU time	252.04 seconds
Started	Jun 07 07:39:35 PM PDT 24
Finished	Jun 07 07:43:49 PM PDT 24
Peak memory	202976 kb
Host	smart-845fad05-6f18-4f44-803d-c3136adae00a
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924956290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_partial_access_b2b.3924956290
Directory	/workspace/40.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/40.sram_ctrl_ram_cfg.2030208967
Short name	T485
Test name
Test status
Simulation time	72891884 ps
CPU time	0.77 seconds
Started	Jun 07 07:39:43 PM PDT 24
Finished	Jun 07 07:39:45 PM PDT 24
Peak memory	202932 kb
Host	smart-70d18bef-9595-47ec-88b4-026b9f648200
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030208967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2030208967
Directory	/workspace/40.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/40.sram_ctrl_regwen.3504563799
Short name	T791
Test name
Test status
Simulation time	9638912585 ps
CPU time	491.97 seconds
Started	Jun 07 07:39:43 PM PDT 24
Finished	Jun 07 07:47:55 PM PDT 24
Peak memory	371180 kb
Host	smart-99e3be02-2c59-4c17-8643-e87874b2dd11
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504563799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3504563799
Directory	/workspace/40.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/40.sram_ctrl_smoke.864154022
Short name	T737
Test name
Test status
Simulation time	1071692245 ps
CPU time	17.77 seconds
Started	Jun 07 07:39:34 PM PDT 24
Finished	Jun 07 07:39:54 PM PDT 24
Peak memory	202836 kb
Host	smart-3d5c748f-0d87-4605-a723-e750bbf1d2ef
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864154022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.864154022
Directory	/workspace/40.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1727293306
Short name	T703
Test name
Test status
Simulation time	7429153131 ps
CPU time	135.24 seconds
Started	Jun 07 07:39:51 PM PDT 24
Finished	Jun 07 07:42:08 PM PDT 24
Peak memory	359476 kb
Host	smart-723f496b-f38e-4135-bda4-e326a7661d5d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1727293306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1727293306
Directory	/workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3236587621
Short name	T650
Test name
Test status
Simulation time	3815256653 ps
CPU time	252.25 seconds
Started	Jun 07 07:39:35 PM PDT 24
Finished	Jun 07 07:43:49 PM PDT 24
Peak memory	203016 kb
Host	smart-392fc878-52e7-490f-a878-c0c865223af5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236587621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.3236587621
Directory	/workspace/40.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3029160145
Short name	T550
Test name
Test status
Simulation time	161000958 ps
CPU time	159.94 seconds
Started	Jun 07 07:39:46 PM PDT 24
Finished	Jun 07 07:42:27 PM PDT 24
Peak memory	370380 kb
Host	smart-89808d62-8677-44aa-8880-f2c0a091f4d9
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029160145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3029160145
Directory	/workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/41.sram_ctrl_access_during_key_req.232844093
Short name	T351
Test name
Test status
Simulation time	3770977689 ps
CPU time	957.68 seconds
Started	Jun 07 07:39:59 PM PDT 24
Finished	Jun 07 07:56:01 PM PDT 24
Peak memory	373812 kb
Host	smart-6a029a92-2244-4bc9-9eb1-68f158e52e69
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232844093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sram_ctrl_access_during_key_req.232844093
Directory	/workspace/41.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/41.sram_ctrl_alert_test.2963054624
Short name	T596
Test name
Test status
Simulation time	17522831 ps
CPU time	0.66 seconds
Started	Jun 07 07:40:01 PM PDT 24
Finished	Jun 07 07:40:06 PM PDT 24
Peak memory	202628 kb
Host	smart-7e5f5463-15d1-401a-8cab-9a1747174264
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963054624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2963054624
Directory	/workspace/41.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.sram_ctrl_bijection.1651972540
Short name	T171
Test name
Test status
Simulation time	3853921949 ps
CPU time	39.89 seconds
Started	Jun 07 07:39:54 PM PDT 24
Finished	Jun 07 07:40:35 PM PDT 24
Peak memory	202912 kb
Host	smart-bfa89273-f6f2-444b-b27d-4e53f11a4a29
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651972540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1651972540
Directory	/workspace/41.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/41.sram_ctrl_executable.4275680311
Short name	T827
Test name
Test status
Simulation time	7807498193 ps
CPU time	562.36 seconds
Started	Jun 07 07:39:58 PM PDT 24
Finished	Jun 07 07:49:24 PM PDT 24
Peak memory	361532 kb
Host	smart-47d07062-4efe-4f43-a4b1-838d01daa7af
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275680311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.4275680311
Directory	/workspace/41.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/41.sram_ctrl_lc_escalation.3769347916
Short name	T277
Test name
Test status
Simulation time	1715599500 ps
CPU time	5.58 seconds
Started	Jun 07 07:39:59 PM PDT 24
Finished	Jun 07 07:40:09 PM PDT 24
Peak memory	202924 kb
Host	smart-29053858-546f-40b2-8869-eb0fa3776c38
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769347916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3769347916
Directory	/workspace/41.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/41.sram_ctrl_max_throughput.4054772328
Short name	T611
Test name
Test status
Simulation time	1444506081 ps
CPU time	166.18 seconds
Started	Jun 07 07:39:52 PM PDT 24
Finished	Jun 07 07:42:40 PM PDT 24
Peak memory	368484 kb
Host	smart-0415a6b2-8c93-44f2-986f-161a027554b6
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054772328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.4054772328
Directory	/workspace/41.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1793209015
Short name	T239
Test name
Test status
Simulation time	163425883 ps
CPU time	2.65 seconds
Started	Jun 07 07:39:57 PM PDT 24
Finished	Jun 07 07:40:01 PM PDT 24
Peak memory	211068 kb
Host	smart-40ba23cd-4ee3-47f2-ab6a-1227c8435933
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793209015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.1793209015
Directory	/workspace/41.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_mem_walk.2001365821
Short name	T210
Test name
Test status
Simulation time	299749852 ps
CPU time	5.93 seconds
Started	Jun 07 07:39:59 PM PDT 24
Finished	Jun 07 07:40:08 PM PDT 24
Peak memory	211016 kb
Host	smart-4b4ded64-ae76-4728-941c-6ae8bbe51f7c
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001365821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.2001365821
Directory	/workspace/41.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/41.sram_ctrl_multiple_keys.1580056813
Short name	T141
Test name
Test status
Simulation time	13412294786 ps
CPU time	1502.53 seconds
Started	Jun 07 07:39:55 PM PDT 24
Finished	Jun 07 08:04:59 PM PDT 24
Peak memory	375540 kb
Host	smart-203555ff-c2ae-4820-903a-373fd54f613e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580056813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.1580056813
Directory	/workspace/41.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access.2681670646
Short name	T816
Test name
Test status
Simulation time	238858683 ps
CPU time	4.77 seconds
Started	Jun 07 07:39:55 PM PDT 24
Finished	Jun 07 07:40:02 PM PDT 24
Peak memory	202884 kb
Host	smart-b26e19fb-ba68-4fed-97ee-d823c520f092
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681670646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2681670646
Directory	/workspace/41.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2507166978
Short name	T865
Test name
Test status
Simulation time	62966168285 ps
CPU time	408.58 seconds
Started	Jun 07 07:39:51 PM PDT 24
Finished	Jun 07 07:46:40 PM PDT 24
Peak memory	202940 kb
Host	smart-9d6babea-70aa-42bd-988f-73fc598e5300
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507166978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2507166978
Directory	/workspace/41.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/41.sram_ctrl_ram_cfg.1096134070
Short name	T534
Test name
Test status
Simulation time	87327384 ps
CPU time	0.78 seconds
Started	Jun 07 07:39:58 PM PDT 24
Finished	Jun 07 07:40:01 PM PDT 24
Peak memory	202932 kb
Host	smart-065d12bc-8ebd-4be7-a14e-5a9818265ce9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096134070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1096134070
Directory	/workspace/41.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/41.sram_ctrl_regwen.2275273432
Short name	T697
Test name
Test status
Simulation time	6685035086 ps
CPU time	1467.85 seconds
Started	Jun 07 07:39:58 PM PDT 24
Finished	Jun 07 08:04:30 PM PDT 24
Peak memory	375852 kb
Host	smart-786bcd58-dea8-4e78-af9b-7e583a21d94f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275273432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2275273432
Directory	/workspace/41.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/41.sram_ctrl_smoke.290949602
Short name	T421
Test name
Test status
Simulation time	217650913 ps
CPU time	91.35 seconds
Started	Jun 07 07:39:52 PM PDT 24
Finished	Jun 07 07:41:25 PM PDT 24
Peak memory	335888 kb
Host	smart-ba4833c0-187b-47f0-82e3-8017d9ba99aa
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290949602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.290949602
Directory	/workspace/41.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all.1954175864
Short name	T564
Test name
Test status
Simulation time	14411921073 ps
CPU time	1453.31 seconds
Started	Jun 07 07:39:59 PM PDT 24
Finished	Jun 07 08:04:16 PM PDT 24
Peak memory	375916 kb
Host	smart-276b375d-8d1c-4b30-92d9-c501b90adca5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954175864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.1954175864
Directory	/workspace/41.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3537923494
Short name	T921
Test name
Test status
Simulation time	2740731838 ps
CPU time	152.32 seconds
Started	Jun 07 07:39:58 PM PDT 24
Finished	Jun 07 07:42:33 PM PDT 24
Peak memory	325088 kb
Host	smart-65dc22de-f948-4ec3-bf2b-06aa60ea0c6f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3537923494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3537923494
Directory	/workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1705924724
Short name	T349
Test name
Test status
Simulation time	2579054724 ps
CPU time	239.34 seconds
Started	Jun 07 07:39:52 PM PDT 24
Finished	Jun 07 07:43:53 PM PDT 24
Peak memory	202964 kb
Host	smart-f2401f32-038f-47eb-a909-48330d5660b6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705924724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_stress_pipeline.1705924724
Directory	/workspace/41.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.971157176
Short name	T918
Test name
Test status
Simulation time	183046954 ps
CPU time	41.43 seconds
Started	Jun 07 07:39:54 PM PDT 24
Finished	Jun 07 07:40:37 PM PDT 24
Peak memory	308256 kb
Host	smart-681d0b96-c2ab-4ac9-929a-3e1d75d2326b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971157176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.971157176
Directory	/workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/42.sram_ctrl_access_during_key_req.2873833237
Short name	T774
Test name
Test status
Simulation time	989987048 ps
CPU time	387.21 seconds
Started	Jun 07 07:40:13 PM PDT 24
Finished	Jun 07 07:46:43 PM PDT 24
Peak memory	370628 kb
Host	smart-c596eb4d-5599-437f-b21c-243153cdc8d4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873833237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.2873833237
Directory	/workspace/42.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/42.sram_ctrl_alert_test.501643119
Short name	T899
Test name
Test status
Simulation time	37467263 ps
CPU time	0.67 seconds
Started	Jun 07 07:40:21 PM PDT 24
Finished	Jun 07 07:40:23 PM PDT 24
Peak memory	202588 kb
Host	smart-f2e36afe-61ba-463b-b617-e18b30542411
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501643119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.501643119
Directory	/workspace/42.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.sram_ctrl_bijection.1232687552
Short name	T184
Test name
Test status
Simulation time	584504963 ps
CPU time	37.81 seconds
Started	Jun 07 07:40:04 PM PDT 24
Finished	Jun 07 07:40:46 PM PDT 24
Peak memory	202892 kb
Host	smart-f4a0472f-53a4-41bd-a5ec-b622ae8c73a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232687552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1232687552
Directory	/workspace/42.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/42.sram_ctrl_executable.2849543982
Short name	T12
Test name
Test status
Simulation time	6331390437 ps
CPU time	1505.02 seconds
Started	Jun 07 07:40:12 PM PDT 24
Finished	Jun 07 08:05:21 PM PDT 24
Peak memory	374932 kb
Host	smart-0f91093d-45cd-4215-9120-0a26e4d4333a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849543982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.2849543982
Directory	/workspace/42.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/42.sram_ctrl_lc_escalation.2446973408
Short name	T753
Test name
Test status
Simulation time	164284923 ps
CPU time	2.03 seconds
Started	Jun 07 07:40:13 PM PDT 24
Finished	Jun 07 07:40:18 PM PDT 24
Peak memory	202928 kb
Host	smart-41d00bfc-07e1-46dd-843b-aae86b42626b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446973408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.2446973408
Directory	/workspace/42.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/42.sram_ctrl_max_throughput.4199451411
Short name	T166
Test name
Test status
Simulation time	285383336 ps
CPU time	8.66 seconds
Started	Jun 07 07:40:07 PM PDT 24
Finished	Jun 07 07:40:20 PM PDT 24
Peak memory	237604 kb
Host	smart-d5b8821b-70ca-438e-9c47-37fc89796ff3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199451411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.4199451411
Directory	/workspace/42.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4166073987
Short name	T556
Test name
Test status
Simulation time	58121106 ps
CPU time	3.16 seconds
Started	Jun 07 07:40:11 PM PDT 24
Finished	Jun 07 07:40:18 PM PDT 24
Peak memory	211148 kb
Host	smart-eeaa87ec-fed1-4f0d-8f76-cb46bbf26adf
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166073987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.4166073987
Directory	/workspace/42.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_mem_walk.134050946
Short name	T39
Test name
Test status
Simulation time	711176933 ps
CPU time	10.6 seconds
Started	Jun 07 07:40:10 PM PDT 24
Finished	Jun 07 07:40:24 PM PDT 24
Peak memory	211100 kb
Host	smart-55d6a164-b893-40e3-9495-53310d792914
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134050946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _mem_walk.134050946
Directory	/workspace/42.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/42.sram_ctrl_multiple_keys.3369491692
Short name	T250
Test name
Test status
Simulation time	2413401192 ps
CPU time	524.4 seconds
Started	Jun 07 07:40:06 PM PDT 24
Finished	Jun 07 07:48:55 PM PDT 24
Peak memory	372420 kb
Host	smart-e3f6f9fe-074b-46e9-a6c3-d0e480e6f535
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369491692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.3369491692
Directory	/workspace/42.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access.2563461205
Short name	T338
Test name
Test status
Simulation time	2759845834 ps
CPU time	17.7 seconds
Started	Jun 07 07:40:08 PM PDT 24
Finished	Jun 07 07:40:29 PM PDT 24
Peak memory	203104 kb
Host	smart-68069ba6-9bda-4dbf-899c-4a054d625880
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563461205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2563461205
Directory	/workspace/42.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2401853866
Short name	T11
Test name
Test status
Simulation time	5545739280 ps
CPU time	409.09 seconds
Started	Jun 07 07:40:06 PM PDT 24
Finished	Jun 07 07:46:59 PM PDT 24
Peak memory	202996 kb
Host	smart-54f8ad08-eaf8-4668-8eb9-149d6dcc2c8c
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401853866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.2401853866
Directory	/workspace/42.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/42.sram_ctrl_ram_cfg.2364262519
Short name	T345
Test name
Test status
Simulation time	27334229 ps
CPU time	0.79 seconds
Started	Jun 07 07:40:13 PM PDT 24
Finished	Jun 07 07:40:16 PM PDT 24
Peak memory	202848 kb
Host	smart-e6b5a9c4-92a6-41ec-a307-7358fdd8d3df
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364262519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2364262519
Directory	/workspace/42.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/42.sram_ctrl_regwen.3621835914
Short name	T539
Test name
Test status
Simulation time	14520123329 ps
CPU time	923.68 seconds
Started	Jun 07 07:40:14 PM PDT 24
Finished	Jun 07 07:55:40 PM PDT 24
Peak memory	369520 kb
Host	smart-aee7c46b-4957-494a-9a85-aa20ff912f2d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621835914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3621835914
Directory	/workspace/42.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/42.sram_ctrl_smoke.1810382650
Short name	T29
Test name
Test status
Simulation time	362656842 ps
CPU time	9.56 seconds
Started	Jun 07 07:40:05 PM PDT 24
Finished	Jun 07 07:40:19 PM PDT 24
Peak memory	236500 kb
Host	smart-d06fdc87-e246-4a0d-953d-5dd8865e152e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810382650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1810382650
Directory	/workspace/42.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all.1245206014
Short name	T917
Test name
Test status
Simulation time	29064828232 ps
CPU time	2397.66 seconds
Started	Jun 07 07:40:22 PM PDT 24
Finished	Jun 07 08:20:22 PM PDT 24
Peak memory	382580 kb
Host	smart-9853cd57-e635-4818-ac38-fcaeaa6b0286
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245206014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.1245206014
Directory	/workspace/42.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2681071441
Short name	T931
Test name
Test status
Simulation time	1895774628 ps
CPU time	217.48 seconds
Started	Jun 07 07:40:19 PM PDT 24
Finished	Jun 07 07:43:59 PM PDT 24
Peak memory	382892 kb
Host	smart-b633c84f-e8cf-4089-bc9b-db86451d8cca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2681071441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2681071441
Directory	/workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1100704114
Short name	T248
Test name
Test status
Simulation time	3547399867 ps
CPU time	224.48 seconds
Started	Jun 07 07:40:06 PM PDT 24
Finished	Jun 07 07:43:55 PM PDT 24
Peak memory	202944 kb
Host	smart-d66f75b3-4eea-446c-a843-513a40f18b54
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100704114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.1100704114
Directory	/workspace/42.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3109164706
Short name	T862
Test name
Test status
Simulation time	792157610 ps
CPU time	44.16 seconds
Started	Jun 07 07:40:06 PM PDT 24
Finished	Jun 07 07:40:54 PM PDT 24
Peak memory	300988 kb
Host	smart-96c2bdc7-2f12-4006-abf8-5e3e0f4c3527
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109164706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3109164706
Directory	/workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2088356483
Short name	T272
Test name
Test status
Simulation time	5800866265 ps
CPU time	863.79 seconds
Started	Jun 07 07:40:31 PM PDT 24
Finished	Jun 07 07:54:56 PM PDT 24
Peak memory	374800 kb
Host	smart-d0beffd5-1503-4356-be21-7ba992dea9f9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088356483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2088356483
Directory	/workspace/43.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/43.sram_ctrl_alert_test.755598060
Short name	T20
Test name
Test status
Simulation time	12915887 ps
CPU time	0.64 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:40:50 PM PDT 24
Peak memory	202604 kb
Host	smart-1d7f74f2-87a6-4471-91be-5045255c6cfe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755598060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.755598060
Directory	/workspace/43.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.sram_ctrl_bijection.2310832213
Short name	T765
Test name
Test status
Simulation time	16490610328 ps
CPU time	77.24 seconds
Started	Jun 07 07:40:20 PM PDT 24
Finished	Jun 07 07:41:39 PM PDT 24
Peak memory	202940 kb
Host	smart-f46ece62-cfc5-4d97-ab71-68174817debe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310832213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .2310832213
Directory	/workspace/43.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/43.sram_ctrl_executable.2040134245
Short name	T33
Test name
Test status
Simulation time	5612762791 ps
CPU time	568.09 seconds
Started	Jun 07 07:40:32 PM PDT 24
Finished	Jun 07 07:50:02 PM PDT 24
Peak memory	374840 kb
Host	smart-51a7df23-46b1-4f01-b8ed-c6c91179b341
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040134245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab le.2040134245
Directory	/workspace/43.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/43.sram_ctrl_lc_escalation.305313679
Short name	T427
Test name
Test status
Simulation time	649309314 ps
CPU time	2.37 seconds
Started	Jun 07 07:40:32 PM PDT 24
Finished	Jun 07 07:40:35 PM PDT 24
Peak memory	211116 kb
Host	smart-017edb9a-d4c8-48b5-bc34-472b8e5c8bfe
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305313679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_esc alation.305313679
Directory	/workspace/43.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/43.sram_ctrl_max_throughput.1757657913
Short name	T913
Test name
Test status
Simulation time	170605393 ps
CPU time	37.25 seconds
Started	Jun 07 07:40:34 PM PDT 24
Finished	Jun 07 07:41:12 PM PDT 24
Peak memory	301020 kb
Host	smart-440389d3-845c-4325-bde8-03ca79e11fb0
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757657913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1757657913
Directory	/workspace/43.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3415171571
Short name	T361
Test name
Test status
Simulation time	44285696 ps
CPU time	2.63 seconds
Started	Jun 07 07:40:42 PM PDT 24
Finished	Jun 07 07:40:46 PM PDT 24
Peak memory	211028 kb
Host	smart-b933eff8-40cc-4a52-baee-82ab40b9a3b4
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415171571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.3415171571
Directory	/workspace/43.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_mem_walk.3486316620
Short name	T762
Test name
Test status
Simulation time	1827573173 ps
CPU time	11.01 seconds
Started	Jun 07 07:40:40 PM PDT 24
Finished	Jun 07 07:40:52 PM PDT 24
Peak memory	211048 kb
Host	smart-63e7ed8f-3889-46ae-b5c3-0a029925dd81
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486316620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3486316620
Directory	/workspace/43.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/43.sram_ctrl_multiple_keys.2996653763
Short name	T716
Test name
Test status
Simulation time	2820660292 ps
CPU time	1377.89 seconds
Started	Jun 07 07:40:19 PM PDT 24
Finished	Jun 07 08:03:19 PM PDT 24
Peak memory	374528 kb
Host	smart-fdcadd7a-a637-453d-bd0d-f6d120edd84c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996653763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2996653763
Directory	/workspace/43.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access.4111636467
Short name	T65
Test name
Test status
Simulation time	230401298 ps
CPU time	17.36 seconds
Started	Jun 07 07:40:19 PM PDT 24
Finished	Jun 07 07:40:38 PM PDT 24
Peak memory	251660 kb
Host	smart-b3208013-e55a-483a-af4e-cd0eea8099a1
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111636467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.4111636467
Directory	/workspace/43.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3311756731
Short name	T700
Test name
Test status
Simulation time	7679922863 ps
CPU time	285.59 seconds
Started	Jun 07 07:40:31 PM PDT 24
Finished	Jun 07 07:45:17 PM PDT 24
Peak memory	202956 kb
Host	smart-ce09d242-d3c4-4152-b6d8-baeae1da47b9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311756731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3311756731
Directory	/workspace/43.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/43.sram_ctrl_ram_cfg.3860056024
Short name	T490
Test name
Test status
Simulation time	48677047 ps
CPU time	0.83 seconds
Started	Jun 07 07:40:32 PM PDT 24
Finished	Jun 07 07:40:34 PM PDT 24
Peak memory	202912 kb
Host	smart-1932dc3b-d18a-455c-84d3-f8b835c936da
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860056024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.3860056024
Directory	/workspace/43.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/43.sram_ctrl_regwen.1451113324
Short name	T781
Test name
Test status
Simulation time	41771193798 ps
CPU time	533.09 seconds
Started	Jun 07 07:40:34 PM PDT 24
Finished	Jun 07 07:49:28 PM PDT 24
Peak memory	374668 kb
Host	smart-6ebc059d-eedd-44f5-99bb-ff585f24b477
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451113324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.1451113324
Directory	/workspace/43.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/43.sram_ctrl_smoke.1445558170
Short name	T580
Test name
Test status
Simulation time	680479102 ps
CPU time	4.52 seconds
Started	Jun 07 07:40:20 PM PDT 24
Finished	Jun 07 07:40:26 PM PDT 24
Peak memory	222384 kb
Host	smart-51700863-1f70-4ce5-9810-dab3e410f871
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445558170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1445558170
Directory	/workspace/43.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_all.3983443785
Short name	T606
Test name
Test status
Simulation time	270498327772 ps
CPU time	3522.29 seconds
Started	Jun 07 07:40:43 PM PDT 24
Finished	Jun 07 08:39:28 PM PDT 24
Peak memory	375676 kb
Host	smart-87ed60f6-e3aa-4b62-9181-7a5480e2e472
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983443785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.3983443785
Directory	/workspace/43.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.sram_ctrl_stress_pipeline.84902548
Short name	T740
Test name
Test status
Simulation time	13499254529 ps
CPU time	300.07 seconds
Started	Jun 07 07:40:19 PM PDT 24
Finished	Jun 07 07:45:20 PM PDT 24
Peak memory	203036 kb
Host	smart-d54e23aa-e146-4783-8aa8-926a53c87423
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84902548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_stress_pipeline.84902548
Directory	/workspace/43.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3541208314
Short name	T8
Test name
Test status
Simulation time	78474937 ps
CPU time	1.68 seconds
Started	Jun 07 07:40:33 PM PDT 24
Finished	Jun 07 07:40:36 PM PDT 24
Peak memory	211144 kb
Host	smart-ae0ab4b9-5327-45a6-bc5c-f597e87e77ce
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541208314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3541208314
Directory	/workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1443003294
Short name	T266
Test name
Test status
Simulation time	6605001114 ps
CPU time	839.72 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:54:50 PM PDT 24
Peak memory	350028 kb
Host	smart-f8411ee6-39a0-40aa-91f1-cf5399c39a50
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443003294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.1443003294
Directory	/workspace/44.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/44.sram_ctrl_alert_test.1410946566
Short name	T597
Test name
Test status
Simulation time	15995294 ps
CPU time	0.63 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:40:50 PM PDT 24
Peak memory	202700 kb
Host	smart-90f63cee-4219-44fd-bcbd-0544acc8ef3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410946566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1410946566
Directory	/workspace/44.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.sram_ctrl_bijection.112690418
Short name	T803
Test name
Test status
Simulation time	4339071293 ps
CPU time	59.97 seconds
Started	Jun 07 07:40:41 PM PDT 24
Finished	Jun 07 07:41:43 PM PDT 24
Peak memory	202980 kb
Host	smart-4a9a5694-5477-4d7d-8485-02bc5f47e502
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112690418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection. 112690418
Directory	/workspace/44.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/44.sram_ctrl_executable.3533346468
Short name	T634
Test name
Test status
Simulation time	1808306187 ps
CPU time	624.95 seconds
Started	Jun 07 07:40:43 PM PDT 24
Finished	Jun 07 07:51:10 PM PDT 24
Peak memory	366508 kb
Host	smart-e5cf5a67-7015-4e52-b474-1dd7a6975488
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533346468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.3533346468
Directory	/workspace/44.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/44.sram_ctrl_lc_escalation.1143557453
Short name	T628
Test name
Test status
Simulation time	4531628653 ps
CPU time	10.02 seconds
Started	Jun 07 07:40:41 PM PDT 24
Finished	Jun 07 07:40:53 PM PDT 24
Peak memory	203020 kb
Host	smart-57e357e8-0d67-4318-b26c-13c4eda64327
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143557453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1143557453
Directory	/workspace/44.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/44.sram_ctrl_max_throughput.4041698172
Short name	T211
Test name
Test status
Simulation time	275980547 ps
CPU time	97.74 seconds
Started	Jun 07 07:40:38 PM PDT 24
Finished	Jun 07 07:42:17 PM PDT 24
Peak memory	357380 kb
Host	smart-1fd1e34c-9b11-4d63-a2f3-2735d682436c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041698172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.4041698172
Directory	/workspace/44.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_partial_access.417039310
Short name	T674
Test name
Test status
Simulation time	125366774 ps
CPU time	4.7 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:40:53 PM PDT 24
Peak memory	211116 kb
Host	smart-f69ff5b0-132c-49f7-a081-48587d03e817
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417039310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .sram_ctrl_mem_partial_access.417039310
Directory	/workspace/44.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_mem_walk.1267335690
Short name	T801
Test name
Test status
Simulation time	454978576 ps
CPU time	6.54 seconds
Started	Jun 07 07:40:48 PM PDT 24
Finished	Jun 07 07:40:57 PM PDT 24
Peak memory	210964 kb
Host	smart-da2bdba8-41ba-4b8f-a385-6c50d09b5c1f
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267335690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.1267335690
Directory	/workspace/44.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/44.sram_ctrl_multiple_keys.1765406628
Short name	T629
Test name
Test status
Simulation time	8182572930 ps
CPU time	532.71 seconds
Started	Jun 07 07:40:40 PM PDT 24
Finished	Jun 07 07:49:35 PM PDT 24
Peak memory	373468 kb
Host	smart-1888b370-ebe1-4674-a00f-1bca8152a67c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765406628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.1765406628
Directory	/workspace/44.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access.580283426
Short name	T907
Test name
Test status
Simulation time	309365158 ps
CPU time	1.18 seconds
Started	Jun 07 07:40:43 PM PDT 24
Finished	Jun 07 07:40:45 PM PDT 24
Peak memory	202720 kb
Host	smart-35931676-1007-4fa8-b8c5-533c08eeadbb
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580283426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ram_ctrl_partial_access.580283426
Directory	/workspace/44.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.282082191
Short name	T419
Test name
Test status
Simulation time	21093603849 ps
CPU time	250.15 seconds
Started	Jun 07 07:40:40 PM PDT 24
Finished	Jun 07 07:44:52 PM PDT 24
Peak memory	202972 kb
Host	smart-47cbe3be-7e76-49dc-a1fa-c42f2fe15be3
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282082191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.sram_ctrl_partial_access_b2b.282082191
Directory	/workspace/44.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/44.sram_ctrl_ram_cfg.227570120
Short name	T477
Test name
Test status
Simulation time	34716792 ps
CPU time	0.82 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:40:47 PM PDT 24
Peak memory	202916 kb
Host	smart-1310c62f-ea24-4b22-afe2-b23644e4e868
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227570120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.227570120
Directory	/workspace/44.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/44.sram_ctrl_regwen.3044181911
Short name	T573
Test name
Test status
Simulation time	66745865980 ps
CPU time	1294.63 seconds
Started	Jun 07 07:40:40 PM PDT 24
Finished	Jun 07 08:02:17 PM PDT 24
Peak memory	374876 kb
Host	smart-1f44f592-301b-4d08-843f-fdf6fd9b142c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044181911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3044181911
Directory	/workspace/44.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/44.sram_ctrl_smoke.310266105
Short name	T333
Test name
Test status
Simulation time	308328281 ps
CPU time	95 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:42:25 PM PDT 24
Peak memory	355076 kb
Host	smart-f9cbd686-4148-46a1-a0a9-555060217fc6
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310266105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.310266105
Directory	/workspace/44.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all.1959549099
Short name	T445
Test name
Test status
Simulation time	18495939609 ps
CPU time	1188.13 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 08:00:34 PM PDT 24
Peak memory	382080 kb
Host	smart-8f36ab34-9383-433d-baeb-549bb54e1b8a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959549099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.1959549099
Directory	/workspace/44.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2631122390
Short name	T623
Test name
Test status
Simulation time	4653943080 ps
CPU time	881.6 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:55:28 PM PDT 24
Peak memory	378924 kb
Host	smart-0e4acc13-cb92-4df3-8c62-19a9e8b1453d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2631122390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2631122390
Directory	/workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1150274307
Short name	T331
Test name
Test status
Simulation time	7372886030 ps
CPU time	155.71 seconds
Started	Jun 07 07:40:40 PM PDT 24
Finished	Jun 07 07:43:17 PM PDT 24
Peak memory	203020 kb
Host	smart-347273fb-4ff1-4c7c-9f05-e52996b6aac2
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150274307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.1150274307
Directory	/workspace/44.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4205736183
Short name	T149
Test name
Test status
Simulation time	88995923 ps
CPU time	20.79 seconds
Started	Jun 07 07:40:38 PM PDT 24
Finished	Jun 07 07:41:00 PM PDT 24
Peak memory	271480 kb
Host	smart-2fd72e30-f59e-4320-bf48-45814ee5d7f3
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205736183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.4205736183
Directory	/workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2095925781
Short name	T472
Test name
Test status
Simulation time	21021683023 ps
CPU time	835.61 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:54:43 PM PDT 24
Peak memory	354756 kb
Host	smart-d25884e7-bc2f-42b8-bfa6-007b1e23c360
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095925781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.2095925781
Directory	/workspace/45.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/45.sram_ctrl_alert_test.1824261840
Short name	T533
Test name
Test status
Simulation time	12257413 ps
CPU time	0.65 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:40:48 PM PDT 24
Peak memory	202656 kb
Host	smart-10123538-dafd-4ca4-8ba0-6c99e131b917
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824261840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.1824261840
Directory	/workspace/45.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.sram_ctrl_bijection.3945949551
Short name	T392
Test name
Test status
Simulation time	6402330174 ps
CPU time	36.76 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:41:24 PM PDT 24
Peak memory	202968 kb
Host	smart-7d130f50-348f-4b6a-a83f-5bbfd0662cf8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945949551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .3945949551
Directory	/workspace/45.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/45.sram_ctrl_executable.1234553814
Short name	T444
Test name
Test status
Simulation time	40615416941 ps
CPU time	849.1 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:54:57 PM PDT 24
Peak memory	375844 kb
Host	smart-39a4c068-7d67-4000-ae3c-d907f788d67b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234553814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.1234553814
Directory	/workspace/45.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/45.sram_ctrl_lc_escalation.3977941546
Short name	T859
Test name
Test status
Simulation time	587189351 ps
CPU time	6.71 seconds
Started	Jun 07 07:40:49 PM PDT 24
Finished	Jun 07 07:40:58 PM PDT 24
Peak memory	214416 kb
Host	smart-d11c100c-8be2-4a99-81b2-3dbf73ba328c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977941546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.3977941546
Directory	/workspace/45.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/45.sram_ctrl_max_throughput.3559715632
Short name	T224
Test name
Test status
Simulation time	269230149 ps
CPU time	120.67 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:42:48 PM PDT 24
Peak memory	363480 kb
Host	smart-a1f7c56a-be9d-49aa-b953-598cff5babcd
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559715632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3559715632
Directory	/workspace/45.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_partial_access.456354054
Short name	T378
Test name
Test status
Simulation time	278118876 ps
CPU time	4.57 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:40:54 PM PDT 24
Peak memory	211128 kb
Host	smart-8b7a7864-beb0-406b-bbf3-a03589f15164
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456354054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .sram_ctrl_mem_partial_access.456354054
Directory	/workspace/45.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_mem_walk.4253774687
Short name	T850
Test name
Test status
Simulation time	371908653 ps
CPU time	6.41 seconds
Started	Jun 07 07:40:48 PM PDT 24
Finished	Jun 07 07:40:57 PM PDT 24
Peak memory	211028 kb
Host	smart-b5ff35f6-e3d1-4f82-9784-11a4e4e7f2e6
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253774687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.4253774687
Directory	/workspace/45.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/45.sram_ctrl_multiple_keys.3709406847
Short name	T567
Test name
Test status
Simulation time	13160525637 ps
CPU time	848.21 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:54:57 PM PDT 24
Peak memory	354388 kb
Host	smart-923d282c-3095-49b8-bb74-658fcbce645a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709406847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.3709406847
Directory	/workspace/45.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access.2708730221
Short name	T152
Test name
Test status
Simulation time	1903744548 ps
CPU time	18.73 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:41:05 PM PDT 24
Peak memory	202868 kb
Host	smart-ce6a3bef-bcba-4750-a1b8-0c24ea316745
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708730221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.2708730221
Directory	/workspace/45.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1287433862
Short name	T819
Test name
Test status
Simulation time	20261512359 ps
CPU time	371.38 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:47:00 PM PDT 24
Peak memory	202912 kb
Host	smart-8c8abfd2-5c79-48a6-b40a-e47366ed5616
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287433862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 45.sram_ctrl_partial_access_b2b.1287433862
Directory	/workspace/45.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/45.sram_ctrl_ram_cfg.2018014983
Short name	T154
Test name
Test status
Simulation time	33464688 ps
CPU time	0.84 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:40:50 PM PDT 24
Peak memory	202928 kb
Host	smart-bec735fb-cbd5-48d5-99f6-a4c9c2a39598
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018014983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2018014983
Directory	/workspace/45.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/45.sram_ctrl_regwen.3516176071
Short name	T727
Test name
Test status
Simulation time	12384327344 ps
CPU time	592.55 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:50:38 PM PDT 24
Peak memory	355368 kb
Host	smart-9faa4252-9388-4988-92f8-3753db2221d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516176071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3516176071
Directory	/workspace/45.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/45.sram_ctrl_smoke.3184998871
Short name	T46
Test name
Test status
Simulation time	3407666080 ps
CPU time	14.86 seconds
Started	Jun 07 07:40:49 PM PDT 24
Finished	Jun 07 07:41:06 PM PDT 24
Peak memory	202984 kb
Host	smart-60abb69e-3386-45b9-aec8-ec7788591d55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184998871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3184998871
Directory	/workspace/45.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2537737804
Short name	T208
Test name
Test status
Simulation time	2919674439 ps
CPU time	280.41 seconds
Started	Jun 07 07:40:48 PM PDT 24
Finished	Jun 07 07:45:31 PM PDT 24
Peak memory	203020 kb
Host	smart-8310708d-bead-42f8-9354-cb4795282dcb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537737804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2537737804
Directory	/workspace/45.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1867809277
Short name	T297
Test name
Test status
Simulation time	125559435 ps
CPU time	64.43 seconds
Started	Jun 07 07:40:49 PM PDT 24
Finished	Jun 07 07:41:56 PM PDT 24
Peak memory	329660 kb
Host	smart-829b1fc5-c6fc-46fe-882c-780d37cdce33
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867809277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1867809277
Directory	/workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2664848843
Short name	T898
Test name
Test status
Simulation time	9733946314 ps
CPU time	369.35 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:46:56 PM PDT 24
Peak memory	374616 kb
Host	smart-a6e13e7b-6676-4cfb-9add-8e82e0735d0e
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664848843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.2664848843
Directory	/workspace/46.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/46.sram_ctrl_alert_test.663304767
Short name	T202
Test name
Test status
Simulation time	11146829 ps
CPU time	0.65 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:40:56 PM PDT 24
Peak memory	202600 kb
Host	smart-c2c0befc-f0b4-4316-99c6-ff7b990bbeb7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663304767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.663304767
Directory	/workspace/46.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.sram_ctrl_bijection.2607572265
Short name	T847
Test name
Test status
Simulation time	3654446493 ps
CPU time	42.38 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:41:31 PM PDT 24
Peak memory	203016 kb
Host	smart-d4a112a5-cd08-4440-8d3f-95b698ebf10c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607572265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2607572265
Directory	/workspace/46.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/46.sram_ctrl_executable.3734819846
Short name	T32
Test name
Test status
Simulation time	17057012037 ps
CPU time	686.66 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:52:16 PM PDT 24
Peak memory	375304 kb
Host	smart-6291f292-dc97-4ddb-9482-792589afa918
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734819846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3734819846
Directory	/workspace/46.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/46.sram_ctrl_lc_escalation.4091193798
Short name	T569
Test name
Test status
Simulation time	668577256 ps
CPU time	7.45 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:40:57 PM PDT 24
Peak memory	214460 kb
Host	smart-4b9111e3-c14d-4131-80c8-f8f7bf1bdc90
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091193798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.4091193798
Directory	/workspace/46.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/46.sram_ctrl_max_throughput.137944660
Short name	T826
Test name
Test status
Simulation time	76618819 ps
CPU time	16.7 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 07:41:05 PM PDT 24
Peak memory	272524 kb
Host	smart-877ad982-6996-48f5-a350-988da236c125
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137944660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.sram_ctrl_max_throughput.137944660
Directory	/workspace/46.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1141177856
Short name	T778
Test name
Test status
Simulation time	644808075 ps
CPU time	5.27 seconds
Started	Jun 07 07:40:55 PM PDT 24
Finished	Jun 07 07:41:02 PM PDT 24
Peak memory	211092 kb
Host	smart-5624deb0-1e2e-41aa-bd11-873bbcfe97c9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141177856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.1141177856
Directory	/workspace/46.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_mem_walk.169364087
Short name	T190
Test name
Test status
Simulation time	183256102 ps
CPU time	10.16 seconds
Started	Jun 07 07:40:52 PM PDT 24
Finished	Jun 07 07:41:03 PM PDT 24
Peak memory	211100 kb
Host	smart-41652250-6aed-4077-bcfb-2e4c196276ad
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169364087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.169364087
Directory	/workspace/46.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/46.sram_ctrl_multiple_keys.4082453551
Short name	T879
Test name
Test status
Simulation time	16692799768 ps
CPU time	2052.25 seconds
Started	Jun 07 07:40:46 PM PDT 24
Finished	Jun 07 08:15:01 PM PDT 24
Peak memory	375728 kb
Host	smart-7367c6dc-8b30-4b9c-95d7-1bd3fde7ad3a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082453551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.4082453551
Directory	/workspace/46.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access.2486938599
Short name	T188
Test name
Test status
Simulation time	3731426401 ps
CPU time	17.38 seconds
Started	Jun 07 07:40:49 PM PDT 24
Finished	Jun 07 07:41:09 PM PDT 24
Peak memory	202620 kb
Host	smart-18a0929e-65ed-447a-91f0-4699aaa54c16
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486938599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.2486938599
Directory	/workspace/46.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.868915438
Short name	T637
Test name
Test status
Simulation time	74868832287 ps
CPU time	520.78 seconds
Started	Jun 07 07:40:45 PM PDT 24
Finished	Jun 07 07:49:28 PM PDT 24
Peak memory	202940 kb
Host	smart-cc9cdbd8-59f8-4ab1-a479-909f36f23592
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868915438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.868915438
Directory	/workspace/46.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/46.sram_ctrl_ram_cfg.3767346363
Short name	T220
Test name
Test status
Simulation time	29047816 ps
CPU time	0.79 seconds
Started	Jun 07 07:40:55 PM PDT 24
Finished	Jun 07 07:40:58 PM PDT 24
Peak memory	202912 kb
Host	smart-217b36b8-2a40-4677-b639-38035fab6257
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767346363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3767346363
Directory	/workspace/46.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/46.sram_ctrl_regwen.1537198771
Short name	T930
Test name
Test status
Simulation time	130274103987 ps
CPU time	2038.65 seconds
Started	Jun 07 07:40:56 PM PDT 24
Finished	Jun 07 08:14:57 PM PDT 24
Peak memory	376064 kb
Host	smart-84948f9f-8312-4436-8224-5eb8ae4dabc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537198771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1537198771
Directory	/workspace/46.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/46.sram_ctrl_smoke.1367949743
Short name	T535
Test name
Test status
Simulation time	2583566720 ps
CPU time	19.16 seconds
Started	Jun 07 07:40:47 PM PDT 24
Finished	Jun 07 07:41:09 PM PDT 24
Peak memory	203000 kb
Host	smart-b0511d8c-4ffa-47fc-83a6-475e398ca096
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367949743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1367949743
Directory	/workspace/46.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_all.1642995219
Short name	T890
Test name
Test status
Simulation time	125426879750 ps
CPU time	4154.73 seconds
Started	Jun 07 07:40:53 PM PDT 24
Finished	Jun 07 08:50:09 PM PDT 24
Peak memory	376884 kb
Host	smart-92e3b813-f95a-44b0-9187-775a8e524012
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642995219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1642995219
Directory	/workspace/46.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3831573069
Short name	T161
Test name
Test status
Simulation time	2141581916 ps
CPU time	108.03 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:42:34 PM PDT 24
Peak memory	202892 kb
Host	smart-8a9186b5-f21c-4aef-8a96-f871fbe6b2ce
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831573069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.3831573069
Directory	/workspace/46.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1804752569
Short name	T308
Test name
Test status
Simulation time	511343526 ps
CPU time	98.85 seconds
Started	Jun 07 07:40:44 PM PDT 24
Finished	Jun 07 07:42:25 PM PDT 24
Peak memory	337836 kb
Host	smart-d44f7e5a-ac73-4e45-aa65-eaaf2acba036
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804752569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1804752569
Directory	/workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3629299780
Short name	T372
Test name
Test status
Simulation time	3433748485 ps
CPU time	791.79 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:54:08 PM PDT 24
Peak memory	369024 kb
Host	smart-fdc0c093-a1a8-4103-8316-374f562fe897
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629299780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.3629299780
Directory	/workspace/47.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/47.sram_ctrl_alert_test.1675186703
Short name	T895
Test name
Test status
Simulation time	35089026 ps
CPU time	0.72 seconds
Started	Jun 07 07:41:03 PM PDT 24
Finished	Jun 07 07:41:06 PM PDT 24
Peak memory	202592 kb
Host	smart-e3963424-93ba-45de-8664-2a77c2fa05c4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675186703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.1675186703
Directory	/workspace/47.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.sram_ctrl_bijection.2179385085
Short name	T443
Test name
Test status
Simulation time	973034773 ps
CPU time	57.14 seconds
Started	Jun 07 07:40:53 PM PDT 24
Finished	Jun 07 07:41:51 PM PDT 24
Peak memory	202936 kb
Host	smart-f32b8b95-e20d-4031-bbce-3d02662f34d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179385085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .2179385085
Directory	/workspace/47.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/47.sram_ctrl_executable.2837886341
Short name	T320
Test name
Test status
Simulation time	61331561933 ps
CPU time	1265.59 seconds
Started	Jun 07 07:40:52 PM PDT 24
Finished	Jun 07 08:01:59 PM PDT 24
Peak memory	369416 kb
Host	smart-9db01ef4-9544-42e8-b14a-d839aff6bd5f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837886341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.2837886341
Directory	/workspace/47.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/47.sram_ctrl_lc_escalation.62784942
Short name	T519
Test name
Test status
Simulation time	4177260449 ps
CPU time	5.67 seconds
Started	Jun 07 07:40:56 PM PDT 24
Finished	Jun 07 07:41:03 PM PDT 24
Peak memory	211188 kb
Host	smart-ab7b71bc-7b62-4878-b2a8-28e447f01f60
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62784942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_esca lation.62784942
Directory	/workspace/47.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/47.sram_ctrl_max_throughput.1035723102
Short name	T231
Test name
Test status
Simulation time	458476239 ps
CPU time	4.41 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:41:00 PM PDT 24
Peak memory	224360 kb
Host	smart-2c212d4f-7cbf-45d9-8f07-c0fdc331625d
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035723102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.1035723102
Directory	/workspace/47.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_partial_access.584528774
Short name	T172
Test name
Test status
Simulation time	300963604 ps
CPU time	3.41 seconds
Started	Jun 07 07:40:57 PM PDT 24
Finished	Jun 07 07:41:02 PM PDT 24
Peak memory	211064 kb
Host	smart-93696ff1-abf2-48ee-b764-34002768bedd
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584528774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.584528774
Directory	/workspace/47.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_mem_walk.677096554
Short name	T284
Test name
Test status
Simulation time	182174750 ps
CPU time	9.72 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:41:05 PM PDT 24
Peak memory	211108 kb
Host	smart-9b222d87-7913-4ee7-bfab-deeba5ba36df
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677096554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl _mem_walk.677096554
Directory	/workspace/47.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/47.sram_ctrl_multiple_keys.3342208366
Short name	T355
Test name
Test status
Simulation time	6497419805 ps
CPU time	942.48 seconds
Started	Jun 07 07:40:52 PM PDT 24
Finished	Jun 07 07:56:35 PM PDT 24
Peak memory	370856 kb
Host	smart-4fc35390-8054-41e1-983e-14b1677580c9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342208366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.3342208366
Directory	/workspace/47.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access.4205561066
Short name	T270
Test name
Test status
Simulation time	91482902 ps
CPU time	2.57 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:40:59 PM PDT 24
Peak memory	209000 kb
Host	smart-ef608f6b-9895-4ad2-9733-7eadf87b77ca
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205561066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.4205561066
Directory	/workspace/47.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3519870361
Short name	T618
Test name
Test status
Simulation time	4173610709 ps
CPU time	250.92 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:45:07 PM PDT 24
Peak memory	202992 kb
Host	smart-e6089026-98f7-4d5e-b531-6a4d33d0da14
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519870361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.3519870361
Directory	/workspace/47.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/47.sram_ctrl_ram_cfg.1687235244
Short name	T891
Test name
Test status
Simulation time	53177727 ps
CPU time	0.76 seconds
Started	Jun 07 07:40:53 PM PDT 24
Finished	Jun 07 07:40:55 PM PDT 24
Peak memory	202908 kb
Host	smart-38591a39-f2bb-4c68-bfab-1ccabd7190d8
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687235244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1687235244
Directory	/workspace/47.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/47.sram_ctrl_regwen.3083290431
Short name	T390
Test name
Test status
Simulation time	3000740232 ps
CPU time	631.67 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:51:27 PM PDT 24
Peak memory	375396 kb
Host	smart-6e332be1-d56e-400c-a8da-a1a971adea04
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083290431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3083290431
Directory	/workspace/47.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/47.sram_ctrl_smoke.892283498
Short name	T526
Test name
Test status
Simulation time	63039342 ps
CPU time	7.74 seconds
Started	Jun 07 07:40:57 PM PDT 24
Finished	Jun 07 07:41:06 PM PDT 24
Peak memory	238396 kb
Host	smart-5d5638d0-4fc1-4625-a2cf-d0d9265bb601
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892283498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.892283498
Directory	/workspace/47.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all.4214868684
Short name	T497
Test name
Test status
Simulation time	1907186120 ps
CPU time	402.56 seconds
Started	Jun 07 07:41:03 PM PDT 24
Finished	Jun 07 07:47:48 PM PDT 24
Peak memory	370280 kb
Host	smart-eb431551-77e6-4a59-be05-b62235bda193
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214868684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.4214868684
Directory	/workspace/47.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1426333442
Short name	T905
Test name
Test status
Simulation time	2849829556 ps
CPU time	336.67 seconds
Started	Jun 07 07:40:53 PM PDT 24
Finished	Jun 07 07:46:30 PM PDT 24
Peak memory	365288 kb
Host	smart-14965ae8-c65c-4951-ae47-11bbfb6dd6aa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1426333442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1426333442
Directory	/workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.sram_ctrl_stress_pipeline.702138195
Short name	T393
Test name
Test status
Simulation time	2923376802 ps
CPU time	282.29 seconds
Started	Jun 07 07:40:55 PM PDT 24
Finished	Jun 07 07:45:39 PM PDT 24
Peak memory	202972 kb
Host	smart-86903d41-c0b3-4ce9-870f-cc5df328a72a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702138195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_stress_pipeline.702138195
Directory	/workspace/47.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.371665097
Short name	T869
Test name
Test status
Simulation time	86946264 ps
CPU time	25.39 seconds
Started	Jun 07 07:40:54 PM PDT 24
Finished	Jun 07 07:41:21 PM PDT 24
Peak memory	277504 kb
Host	smart-d77dc63a-5a2c-457e-a6ff-011828a4ab18
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371665097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.371665097
Directory	/workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1764084447
Short name	T322
Test name
Test status
Simulation time	4722895868 ps
CPU time	277.26 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:45:40 PM PDT 24
Peak memory	328924 kb
Host	smart-3b31eaae-2119-4733-87a2-968c71bb051d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764084447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.1764084447
Directory	/workspace/48.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/48.sram_ctrl_alert_test.3285010325
Short name	T807
Test name
Test status
Simulation time	32552020 ps
CPU time	0.66 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:41:04 PM PDT 24
Peak memory	202632 kb
Host	smart-a1b8e788-0a6a-44fa-8415-52ab05c6c5f3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285010325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3285010325
Directory	/workspace/48.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.sram_ctrl_bijection.3482477641
Short name	T422
Test name
Test status
Simulation time	682086306 ps
CPU time	42.16 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:46 PM PDT 24
Peak memory	202948 kb
Host	smart-8d95e07b-540f-40e0-889b-7ee06c1233ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482477641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3482477641
Directory	/workspace/48.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/48.sram_ctrl_executable.772704785
Short name	T128
Test name
Test status
Simulation time	51334214021 ps
CPU time	1253.22 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 08:01:58 PM PDT 24
Peak memory	370708 kb
Host	smart-fb575fb8-9b35-4c25-a9ce-31a15e87860b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772704785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl e.772704785
Directory	/workspace/48.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/48.sram_ctrl_lc_escalation.2673288339
Short name	T868
Test name
Test status
Simulation time	81013105 ps
CPU time	1.34 seconds
Started	Jun 07 07:41:34 PM PDT 24
Finished	Jun 07 07:41:36 PM PDT 24
Peak memory	202704 kb
Host	smart-c097ec8f-9d56-441f-aa00-5e9bae8d473e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673288339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2673288339
Directory	/workspace/48.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/48.sram_ctrl_max_throughput.165560839
Short name	T341
Test name
Test status
Simulation time	236129642 ps
CPU time	25.33 seconds
Started	Jun 07 07:41:06 PM PDT 24
Finished	Jun 07 07:41:33 PM PDT 24
Peak memory	281692 kb
Host	smart-57873b7a-d0c7-47df-b418-4e73f3060fc1
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165560839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.165560839
Directory	/workspace/48.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_partial_access.873715836
Short name	T44
Test name
Test status
Simulation time	274036503 ps
CPU time	3.11 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:07 PM PDT 24
Peak memory	211120 kb
Host	smart-0cb70bbe-8f08-4f06-8694-44e5a6987d42
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873715836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_mem_partial_access.873715836
Directory	/workspace/48.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_mem_walk.2312169789
Short name	T914
Test name
Test status
Simulation time	1661722206 ps
CPU time	6.38 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:10 PM PDT 24
Peak memory	202840 kb
Host	smart-a7458610-6b47-44cd-b8af-b836f2c08a83
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312169789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2312169789
Directory	/workspace/48.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/48.sram_ctrl_multiple_keys.1652612088
Short name	T143
Test name
Test status
Simulation time	25958536004 ps
CPU time	461.12 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:48:44 PM PDT 24
Peak memory	362528 kb
Host	smart-adce1b3d-d22e-49c8-987b-7fb6ed2bc82f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652612088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1652612088
Directory	/workspace/48.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access.554708460
Short name	T808
Test name
Test status
Simulation time	670393956 ps
CPU time	157.73 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:43:42 PM PDT 24
Peak memory	368240 kb
Host	smart-5050e113-f04d-459b-9bb3-f344881df119
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554708460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s ram_ctrl_partial_access.554708460
Directory	/workspace/48.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1702289771
Short name	T901
Test name
Test status
Simulation time	59338739303 ps
CPU time	348.29 seconds
Started	Jun 07 07:41:00 PM PDT 24
Finished	Jun 07 07:46:49 PM PDT 24
Peak memory	202908 kb
Host	smart-9271b82a-067b-4f57-a7e4-f1370f99618b
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702289771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1702289771
Directory	/workspace/48.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/48.sram_ctrl_ram_cfg.845393492
Short name	T507
Test name
Test status
Simulation time	74644025 ps
CPU time	0.75 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:05 PM PDT 24
Peak memory	202896 kb
Host	smart-7f9897b7-8808-495f-bed2-d58df3af99b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845393492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.845393492
Directory	/workspace/48.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/48.sram_ctrl_regwen.3907296925
Short name	T790
Test name
Test status
Simulation time	28342711718 ps
CPU time	1108.25 seconds
Started	Jun 07 07:40:59 PM PDT 24
Finished	Jun 07 07:59:29 PM PDT 24
Peak memory	374872 kb
Host	smart-5dcee8d3-d93d-4628-836e-1231042b59ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907296925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3907296925
Directory	/workspace/48.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/48.sram_ctrl_smoke.2318579754
Short name	T673
Test name
Test status
Simulation time	186531125 ps
CPU time	36.08 seconds
Started	Jun 07 07:41:00 PM PDT 24
Finished	Jun 07 07:41:37 PM PDT 24
Peak memory	303372 kb
Host	smart-7622beaa-c67f-429a-9e55-b5e30c160d07
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318579754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.2318579754
Directory	/workspace/48.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all.474601052
Short name	T478
Test name
Test status
Simulation time	75924546035 ps
CPU time	2857.57 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 08:28:41 PM PDT 24
Peak memory	375624 kb
Host	smart-778d250d-76c8-4e44-9cdc-945d36a003b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474601052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_stress_all.474601052
Directory	/workspace/48.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3087997073
Short name	T590
Test name
Test status
Simulation time	1738387887 ps
CPU time	241.69 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:45:05 PM PDT 24
Peak memory	349364 kb
Host	smart-3a52d86e-767d-47a8-8d32-57f06bd11805
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3087997073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3087997073
Directory	/workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1752297921
Short name	T710
Test name
Test status
Simulation time	5151560113 ps
CPU time	255.69 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:45:19 PM PDT 24
Peak memory	202972 kb
Host	smart-5edd83a8-b6a6-4319-b63e-9b05505643a6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752297921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1752297921
Directory	/workspace/48.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3421217846
Short name	T724
Test name
Test status
Simulation time	96467761 ps
CPU time	3.57 seconds
Started	Jun 07 07:41:00 PM PDT 24
Finished	Jun 07 07:41:06 PM PDT 24
Peak memory	220372 kb
Host	smart-a429bd1f-cfbe-408b-8425-25678df748c5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421217846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3421217846
Directory	/workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/49.sram_ctrl_access_during_key_req.3235057586
Short name	T591
Test name
Test status
Simulation time	3687285578 ps
CPU time	1029.87 seconds
Started	Jun 07 07:41:07 PM PDT 24
Finished	Jun 07 07:58:18 PM PDT 24
Peak memory	370752 kb
Host	smart-5eb25401-4282-4805-9651-4dd8ef3d2121
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235057586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.3235057586
Directory	/workspace/49.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/49.sram_ctrl_alert_test.2952486
Short name	T449
Test name
Test status
Simulation time	46275040 ps
CPU time	0.68 seconds
Started	Jun 07 07:41:12 PM PDT 24
Finished	Jun 07 07:41:14 PM PDT 24
Peak memory	202556 kb
Host	smart-00863586-1fb5-4b9c-9a4b-693f6b281dc8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_alert_test.2952486
Directory	/workspace/49.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.sram_ctrl_bijection.2984272307
Short name	T282
Test name
Test status
Simulation time	14532406894 ps
CPU time	57.44 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:42:01 PM PDT 24
Peak memory	202996 kb
Host	smart-608dce17-26f1-41af-9715-b39d66522bbb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984272307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2984272307
Directory	/workspace/49.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/49.sram_ctrl_executable.3376767710
Short name	T258
Test name
Test status
Simulation time	59231189570 ps
CPU time	1192.96 seconds
Started	Jun 07 07:41:09 PM PDT 24
Finished	Jun 07 08:01:04 PM PDT 24
Peak memory	375064 kb
Host	smart-8e391914-aa13-48e4-b836-be4598477720
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376767710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.3376767710
Directory	/workspace/49.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/49.sram_ctrl_lc_escalation.3951456746
Short name	T140
Test name
Test status
Simulation time	614034129 ps
CPU time	7.19 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:41:10 PM PDT 24
Peak memory	211120 kb
Host	smart-bae44e60-cd5a-4b81-a8b2-d400a8e09f19
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951456746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.3951456746
Directory	/workspace/49.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/49.sram_ctrl_max_throughput.1717236842
Short name	T489
Test name
Test status
Simulation time	1443654458 ps
CPU time	20.5 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:24 PM PDT 24
Peak memory	274832 kb
Host	smart-77673207-770c-471a-b0c9-2f8a4e66b8b5
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717236842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1717236842
Directory	/workspace/49.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3227332457
Short name	T824
Test name
Test status
Simulation time	1596100936 ps
CPU time	6.14 seconds
Started	Jun 07 07:41:09 PM PDT 24
Finished	Jun 07 07:41:17 PM PDT 24
Peak memory	211112 kb
Host	smart-156368b0-b9cb-4d8e-a04d-058a164c8eac
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227332457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.3227332457
Directory	/workspace/49.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_mem_walk.2163980760
Short name	T588
Test name
Test status
Simulation time	2600958415 ps
CPU time	12.12 seconds
Started	Jun 07 07:41:08 PM PDT 24
Finished	Jun 07 07:41:21 PM PDT 24
Peak memory	211088 kb
Host	smart-f39551bc-f2a3-41fa-8f2c-a6b6993498b1
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163980760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.2163980760
Directory	/workspace/49.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/49.sram_ctrl_multiple_keys.2513174479
Short name	T447
Test name
Test status
Simulation time	4498307129 ps
CPU time	1659.56 seconds
Started	Jun 07 07:41:05 PM PDT 24
Finished	Jun 07 08:08:46 PM PDT 24
Peak memory	373548 kb
Host	smart-bb495051-4c9b-4c1c-b975-2e1349c98acf
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513174479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.2513174479
Directory	/workspace/49.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access.3993368123
Short name	T317
Test name
Test status
Simulation time	932934480 ps
CPU time	13.48 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:17 PM PDT 24
Peak memory	202912 kb
Host	smart-e36bfe61-19ad-48b2-b306-68be9b8acf08
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993368123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.3993368123
Directory	/workspace/49.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3999537597
Short name	T655
Test name
Test status
Simulation time	4831602534 ps
CPU time	351 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:46:54 PM PDT 24
Peak memory	202992 kb
Host	smart-50f045de-5bbc-4ff8-a7a7-72c98c7e5f04
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999537597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.3999537597
Directory	/workspace/49.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/49.sram_ctrl_ram_cfg.977725448
Short name	T223
Test name
Test status
Simulation time	71781390 ps
CPU time	0.9 seconds
Started	Jun 07 07:41:10 PM PDT 24
Finished	Jun 07 07:41:12 PM PDT 24
Peak memory	202936 kb
Host	smart-8925de51-0f14-4d00-b89b-243f874eb61b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977725448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.977725448
Directory	/workspace/49.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/49.sram_ctrl_regwen.2544528030
Short name	T646
Test name
Test status
Simulation time	18690831137 ps
CPU time	996.39 seconds
Started	Jun 07 07:41:09 PM PDT 24
Finished	Jun 07 07:57:46 PM PDT 24
Peak memory	349228 kb
Host	smart-b8e63a72-aad5-4059-ad07-16328dce9829
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544528030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2544528030
Directory	/workspace/49.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/49.sram_ctrl_smoke.524082408
Short name	T723
Test name
Test status
Simulation time	9325967785 ps
CPU time	19.72 seconds
Started	Jun 07 07:41:02 PM PDT 24
Finished	Jun 07 07:41:24 PM PDT 24
Peak memory	202964 kb
Host	smart-4123b610-bb23-4594-a4fd-a9a030080f92
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524082408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.524082408
Directory	/workspace/49.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all.1665128016
Short name	T875
Test name
Test status
Simulation time	163708613838 ps
CPU time	5608.84 seconds
Started	Jun 07 07:41:09 PM PDT 24
Finished	Jun 07 09:14:40 PM PDT 24
Peak memory	376380 kb
Host	smart-125c1df0-0560-4a1a-aaa8-8214a65530d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665128016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.1665128016
Directory	/workspace/49.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3852650292
Short name	T620
Test name
Test status
Simulation time	706438347 ps
CPU time	33.84 seconds
Started	Jun 07 07:41:09 PM PDT 24
Finished	Jun 07 07:41:43 PM PDT 24
Peak memory	295788 kb
Host	smart-d7794352-7d92-4cd2-8a84-74f3751eebb4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3852650292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3852650292
Directory	/workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1140296764
Short name	T174
Test name
Test status
Simulation time	8450589017 ps
CPU time	209.24 seconds
Started	Jun 07 07:41:07 PM PDT 24
Finished	Jun 07 07:44:38 PM PDT 24
Peak memory	202948 kb
Host	smart-bd1be7cb-3288-4497-887b-28bad8b4fbf6
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140296764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.1140296764
Directory	/workspace/49.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3691893555
Short name	T928
Test name
Test status
Simulation time	153338927 ps
CPU time	110.4 seconds
Started	Jun 07 07:41:01 PM PDT 24
Finished	Jun 07 07:42:53 PM PDT 24
Peak memory	364436 kb
Host	smart-5c86d7a2-4994-49d4-8015-e0013acc8e8a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691893555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.3691893555
Directory	/workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3828944906
Short name	T755
Test name
Test status
Simulation time	1240523195 ps
CPU time	404.3 seconds
Started	Jun 07 07:33:48 PM PDT 24
Finished	Jun 07 07:40:35 PM PDT 24
Peak memory	371332 kb
Host	smart-02952dda-9494-4046-80e6-c5b640dd7b4d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828944906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3828944906
Directory	/workspace/5.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/5.sram_ctrl_alert_test.630800550
Short name	T226
Test name
Test status
Simulation time	12060597 ps
CPU time	0.64 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:33:47 PM PDT 24
Peak memory	202640 kb
Host	smart-e1ea77d4-8e65-4840-a9ab-43956830911d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630800550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.630800550
Directory	/workspace/5.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.sram_ctrl_bijection.3412295925
Short name	T456
Test name
Test status
Simulation time	16463935965 ps
CPU time	68.74 seconds
Started	Jun 07 07:33:44 PM PDT 24
Finished	Jun 07 07:34:57 PM PDT 24
Peak memory	202944 kb
Host	smart-0f71a138-efbc-4b9a-8327-621aa9268980
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412295925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 3412295925
Directory	/workspace/5.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/5.sram_ctrl_executable.1372130595
Short name	T169
Test name
Test status
Simulation time	7299719630 ps
CPU time	454.85 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:41:25 PM PDT 24
Peak memory	361484 kb
Host	smart-15fd4f5a-eeac-401b-a59b-2acdffb28b64
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372130595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.1372130595
Directory	/workspace/5.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/5.sram_ctrl_lc_escalation.2303607424
Short name	T772
Test name
Test status
Simulation time	7204499294 ps
CPU time	7.89 seconds
Started	Jun 07 07:33:46 PM PDT 24
Finished	Jun 07 07:33:58 PM PDT 24
Peak memory	215608 kb
Host	smart-780f929e-727e-4c0a-8167-183e3fdf8b55
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303607424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.2303607424
Directory	/workspace/5.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/5.sram_ctrl_max_throughput.66974571
Short name	T326
Test name
Test status
Simulation time	577449665 ps
CPU time	118.47 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:35:45 PM PDT 24
Peak memory	370324 kb
Host	smart-8de0e36c-c58d-4613-9bf4-f7e6a817eae7
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66974571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_max_throughput.66974571
Directory	/workspace/5.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1277375482
Short name	T730
Test name
Test status
Simulation time	323120854 ps
CPU time	4.47 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:52 PM PDT 24
Peak memory	211072 kb
Host	smart-781cb135-93ac-43fd-83a0-6b5e50fe9aa9
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277375482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1277375482
Directory	/workspace/5.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_mem_walk.2003155823
Short name	T364
Test name
Test status
Simulation time	458253570 ps
CPU time	11.38 seconds
Started	Jun 07 07:33:49 PM PDT 24
Finished	Jun 07 07:34:04 PM PDT 24
Peak memory	211040 kb
Host	smart-ea449fcc-69c7-4df4-ac90-f573249dee07
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003155823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.2003155823
Directory	/workspace/5.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/5.sram_ctrl_multiple_keys.1329897817
Short name	T542
Test name
Test status
Simulation time	12945953032 ps
CPU time	1169.72 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:53:17 PM PDT 24
Peak memory	370720 kb
Host	smart-340b11bc-32ec-41f2-a3fd-890aae2d769f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329897817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.1329897817
Directory	/workspace/5.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access.854581463
Short name	T543
Test name
Test status
Simulation time	115897955 ps
CPU time	6.2 seconds
Started	Jun 07 07:33:49 PM PDT 24
Finished	Jun 07 07:33:58 PM PDT 24
Peak memory	202920 kb
Host	smart-f4dba041-5b7d-4f2a-8d26-086de8a839e0
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854581463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr am_ctrl_partial_access.854581463
Directory	/workspace/5.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3309382033
Short name	T547
Test name
Test status
Simulation time	12561402841 ps
CPU time	347.57 seconds
Started	Jun 07 07:33:50 PM PDT 24
Finished	Jun 07 07:39:40 PM PDT 24
Peak memory	202932 kb
Host	smart-9a112d66-d6ef-4f58-a268-66354fe3aed6
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309382033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3309382033
Directory	/workspace/5.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/5.sram_ctrl_ram_cfg.4189512931
Short name	T310
Test name
Test status
Simulation time	54150824 ps
CPU time	0.74 seconds
Started	Jun 07 07:33:49 PM PDT 24
Finished	Jun 07 07:33:53 PM PDT 24
Peak memory	202900 kb
Host	smart-dcb89bdd-372a-4a83-9df0-f35c632bc651
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189512931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4189512931
Directory	/workspace/5.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/5.sram_ctrl_regwen.1732888045
Short name	T802
Test name
Test status
Simulation time	13671616556 ps
CPU time	1366.55 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:56:36 PM PDT 24
Peak memory	362356 kb
Host	smart-11fa153b-9010-4571-b73e-3a0c4eedf2d1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732888045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1732888045
Directory	/workspace/5.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/5.sram_ctrl_smoke.3562286936
Short name	T744
Test name
Test status
Simulation time	193822337 ps
CPU time	11.01 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:33:57 PM PDT 24
Peak memory	202912 kb
Host	smart-ee2904e9-08c7-4c22-a4ab-d907f2938d7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562286936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3562286936
Directory	/workspace/5.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all.3707177535
Short name	T566
Test name
Test status
Simulation time	98143772166 ps
CPU time	3281.48 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 08:28:29 PM PDT 24
Peak memory	384708 kb
Host	smart-bfedeae6-f97e-4ace-b11f-b9fff9f5520e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707177535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3707177535
Directory	/workspace/5.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1885939475
Short name	T47
Test name
Test status
Simulation time	4203828339 ps
CPU time	190.7 seconds
Started	Jun 07 07:33:42 PM PDT 24
Finished	Jun 07 07:36:58 PM PDT 24
Peak memory	349868 kb
Host	smart-bbe46564-f6fb-4b6a-9830-26fe7f994bf4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1885939475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1885939475
Directory	/workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4267904538
Short name	T60
Test name
Test status
Simulation time	2914566054 ps
CPU time	281.03 seconds
Started	Jun 07 07:33:50 PM PDT 24
Finished	Jun 07 07:38:34 PM PDT 24
Peak memory	202948 kb
Host	smart-9bb76c50-cf2d-4a1f-ba53-06aeef90aacb
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267904538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.4267904538
Directory	/workspace/5.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.331710028
Short name	T425
Test name
Test status
Simulation time	101998207 ps
CPU time	18.34 seconds
Started	Jun 07 07:33:50 PM PDT 24
Finished	Jun 07 07:34:12 PM PDT 24
Peak memory	279084 kb
Host	smart-cae9466c-65eb-4e65-842d-4bffd0f7180b
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331710028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.331710028
Directory	/workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/6.sram_ctrl_access_during_key_req.296747420
Short name	T892
Test name
Test status
Simulation time	30864727806 ps
CPU time	796.17 seconds
Started	Jun 07 07:33:51 PM PDT 24
Finished	Jun 07 07:47:10 PM PDT 24
Peak memory	338620 kb
Host	smart-d6f05056-84cb-40f9-ac13-cf3b624c5ad7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296747420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_access_during_key_req.296747420
Directory	/workspace/6.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/6.sram_ctrl_alert_test.1637666244
Short name	T709
Test name
Test status
Simulation time	14784376 ps
CPU time	0.63 seconds
Started	Jun 07 07:33:51 PM PDT 24
Finished	Jun 07 07:33:54 PM PDT 24
Peak memory	202620 kb
Host	smart-87b95629-09ce-4715-886a-baba07d87cc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637666244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1637666244
Directory	/workspace/6.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.sram_ctrl_bijection.2028667578
Short name	T151
Test name
Test status
Simulation time	887155678 ps
CPU time	57.39 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:34:44 PM PDT 24
Peak memory	202924 kb
Host	smart-7904b388-b3f2-418f-a078-8d483bd1b17c
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028667578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2028667578
Directory	/workspace/6.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/6.sram_ctrl_executable.1591811004
Short name	T805
Test name
Test status
Simulation time	15745123965 ps
CPU time	881.78 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:48:37 PM PDT 24
Peak memory	366260 kb
Host	smart-375830aa-19a2-41b9-8408-80d20570c263
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591811004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1591811004
Directory	/workspace/6.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/6.sram_ctrl_lc_escalation.2038354632
Short name	T5
Test name
Test status
Simulation time	1185013879 ps
CPU time	8.74 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:34:05 PM PDT 24
Peak memory	202868 kb
Host	smart-f7aa8596-7f4a-4a2b-b23d-31569d58ff0e
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038354632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.2038354632
Directory	/workspace/6.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/6.sram_ctrl_max_throughput.1432059466
Short name	T668
Test name
Test status
Simulation time	494460462 ps
CPU time	115.16 seconds
Started	Jun 07 07:33:48 PM PDT 24
Finished	Jun 07 07:35:47 PM PDT 24
Peak memory	354124 kb
Host	smart-973b9b1f-7ca0-4eb7-95f1-92b946262b80
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432059466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.1432059466
Directory	/workspace/6.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2115803962
Short name	T909
Test name
Test status
Simulation time	1795608014 ps
CPU time	5.53 seconds
Started	Jun 07 07:33:56 PM PDT 24
Finished	Jun 07 07:34:03 PM PDT 24
Peak memory	211080 kb
Host	smart-331385e3-09b1-4886-b6dc-c39ac0177f37
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115803962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.2115803962
Directory	/workspace/6.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_mem_walk.1586503123
Short name	T640
Test name
Test status
Simulation time	942775302 ps
CPU time	6.41 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:34:04 PM PDT 24
Peak memory	211036 kb
Host	smart-cf4d9c50-be68-4f6a-96f4-d62c421a145b
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586503123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl _mem_walk.1586503123
Directory	/workspace/6.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/6.sram_ctrl_multiple_keys.3257590608
Short name	T721
Test name
Test status
Simulation time	74044015076 ps
CPU time	918.07 seconds
Started	Jun 07 07:33:46 PM PDT 24
Finished	Jun 07 07:49:08 PM PDT 24
Peak memory	363936 kb
Host	smart-fbaaf06c-6e5d-48aa-abe7-91420ba09380
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257590608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.3257590608
Directory	/workspace/6.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access.304149770
Short name	T306
Test name
Test status
Simulation time	65349924 ps
CPU time	2.28 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:33:50 PM PDT 24
Peak memory	204588 kb
Host	smart-c5169f13-4e26-4bba-80de-6fb0dba16737
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304149770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr am_ctrl_partial_access.304149770
Directory	/workspace/6.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.878136493
Short name	T933
Test name
Test status
Simulation time	14412263255 ps
CPU time	286.18 seconds
Started	Jun 07 07:33:45 PM PDT 24
Finished	Jun 07 07:38:36 PM PDT 24
Peak memory	203052 kb
Host	smart-160a0247-31fa-4084-83ed-99409d80b22d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878136493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.878136493
Directory	/workspace/6.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/6.sram_ctrl_ram_cfg.2716818368
Short name	T915
Test name
Test status
Simulation time	87576613 ps
CPU time	0.78 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:33:57 PM PDT 24
Peak memory	202932 kb
Host	smart-39d7078a-b868-48ac-97e1-d46d10c8a64a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716818368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2716818368
Directory	/workspace/6.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/6.sram_ctrl_regwen.3515206128
Short name	T878
Test name
Test status
Simulation time	27022100034 ps
CPU time	1023.23 seconds
Started	Jun 07 07:33:56 PM PDT 24
Finished	Jun 07 07:51:02 PM PDT 24
Peak memory	368600 kb
Host	smart-b9d5a9b7-0618-4f35-b129-1f4c78d8036d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515206128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3515206128
Directory	/workspace/6.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/6.sram_ctrl_smoke.3418223114
Short name	T688
Test name
Test status
Simulation time	247094329 ps
CPU time	14.74 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:34:03 PM PDT 24
Peak memory	202916 kb
Host	smart-d8db3d63-c106-49c3-bf87-a991d205051a
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418223114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3418223114
Directory	/workspace/6.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_all.292979765
Short name	T667
Test name
Test status
Simulation time	9865613302 ps
CPU time	2050.03 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 08:08:06 PM PDT 24
Peak memory	382964 kb
Host	smart-711f0c39-24e1-4ff9-aaa9-b809c1cb0460
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292979765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_stress_all.292979765
Directory	/workspace/6.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.sram_ctrl_stress_pipeline.1830949815
Short name	T679
Test name
Test status
Simulation time	4566654876 ps
CPU time	364.83 seconds
Started	Jun 07 07:33:43 PM PDT 24
Finished	Jun 07 07:39:52 PM PDT 24
Peak memory	202996 kb
Host	smart-ab25c9b8-5eb3-4812-bc1e-0ddf1c2358a9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830949815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.1830949815
Directory	/workspace/6.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.763388228
Short name	T702
Test name
Test status
Simulation time	91386769 ps
CPU time	26.98 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:34:23 PM PDT 24
Peak memory	281356 kb
Host	smart-6ddf74ee-873e-48e6-a87d-5692d04b9889
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763388228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.763388228
Directory	/workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/7.sram_ctrl_access_during_key_req.645596190
Short name	T493
Test name
Test status
Simulation time	3300874710 ps
CPU time	1089.09 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:52:06 PM PDT 24
Peak memory	369448 kb
Host	smart-87585a7d-3c5b-4f2c-a8ac-5f867b248d45
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645596190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_access_during_key_req.645596190
Directory	/workspace/7.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/7.sram_ctrl_alert_test.1008932384
Short name	T175
Test name
Test status
Simulation time	16091543 ps
CPU time	0.67 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:33:56 PM PDT 24
Peak memory	202628 kb
Host	smart-9d699b00-86f0-4653-a553-0e5e796006d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008932384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1008932384
Directory	/workspace/7.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.sram_ctrl_bijection.1013542797
Short name	T676
Test name
Test status
Simulation time	5152202434 ps
CPU time	37.82 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:34:34 PM PDT 24
Peak memory	202980 kb
Host	smart-8113c528-2f37-4450-b6ac-956a705a8d9d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013542797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 1013542797
Directory	/workspace/7.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/7.sram_ctrl_executable.2533674596
Short name	T241
Test name
Test status
Simulation time	12940613801 ps
CPU time	838.9 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:47:55 PM PDT 24
Peak memory	374912 kb
Host	smart-006f3aad-cc06-4957-bfb1-1638b415f629
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533674596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.2533674596
Directory	/workspace/7.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/7.sram_ctrl_lc_escalation.128859024
Short name	T583
Test name
Test status
Simulation time	629859970 ps
CPU time	8.1 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:34:04 PM PDT 24
Peak memory	202900 kb
Host	smart-e9eb8ea6-db9c-4ae0-ba54-c7388b2ad9eb
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128859024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.128859024
Directory	/workspace/7.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/7.sram_ctrl_max_throughput.2462383842
Short name	T605
Test name
Test status
Simulation time	330137148 ps
CPU time	26.75 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:34:22 PM PDT 24
Peak memory	286760 kb
Host	smart-a5cab720-cf0d-466a-8a2b-e9df9b56779a
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462383842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_max_throughput.2462383842
Directory	/workspace/7.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_partial_access.202855870
Short name	T858
Test name
Test status
Simulation time	555451014 ps
CPU time	5.32 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:34:02 PM PDT 24
Peak memory	211052 kb
Host	smart-c29d4a35-c33b-4c0a-9a43-53d42bcf0559
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202855870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. sram_ctrl_mem_partial_access.202855870
Directory	/workspace/7.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_mem_walk.2585360431
Short name	T213
Test name
Test status
Simulation time	293580491 ps
CPU time	4.89 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:34:02 PM PDT 24
Peak memory	202844 kb
Host	smart-ab835071-4d40-463b-81c4-325b40c1a6aa
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585360431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2585360431
Directory	/workspace/7.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/7.sram_ctrl_multiple_keys.2446323669
Short name	T732
Test name
Test status
Simulation time	5834215167 ps
CPU time	751.04 seconds
Started	Jun 07 07:33:56 PM PDT 24
Finished	Jun 07 07:46:29 PM PDT 24
Peak memory	375036 kb
Host	smart-822b92b3-c174-4b42-b427-25b45716f98b
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446323669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2446323669
Directory	/workspace/7.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access.3435509224
Short name	T882
Test name
Test status
Simulation time	529206702 ps
CPU time	22.9 seconds
Started	Jun 07 07:33:57 PM PDT 24
Finished	Jun 07 07:34:22 PM PDT 24
Peak memory	264700 kb
Host	smart-431180cc-b227-422d-bd2f-863781983fb2
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435509224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.3435509224
Directory	/workspace/7.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3079478827
Short name	T488
Test name
Test status
Simulation time	4063638014 ps
CPU time	295.53 seconds
Started	Jun 07 07:33:56 PM PDT 24
Finished	Jun 07 07:38:53 PM PDT 24
Peak memory	202976 kb
Host	smart-0cbb10ea-d1ae-4ff7-ab4e-b316ed8678d9
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079478827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.3079478827
Directory	/workspace/7.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/7.sram_ctrl_ram_cfg.111092007
Short name	T212
Test name
Test status
Simulation time	151803181 ps
CPU time	0.91 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:33:58 PM PDT 24
Peak memory	202896 kb
Host	smart-5168eb99-9fc4-4abb-a8f0-ea527d12cc46
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111092007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.111092007
Directory	/workspace/7.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/7.sram_ctrl_regwen.1536202394
Short name	T127
Test name
Test status
Simulation time	54957521791 ps
CPU time	1301.8 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:55:36 PM PDT 24
Peak memory	374860 kb
Host	smart-51803b58-484f-4676-96db-fe0143c9a9e5
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536202394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1536202394
Directory	/workspace/7.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/7.sram_ctrl_smoke.2213468927
Short name	T371
Test name
Test status
Simulation time	688836117 ps
CPU time	27.88 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 07:34:23 PM PDT 24
Peak memory	278532 kb
Host	smart-252e3768-7c77-4587-b86a-725592069d6f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213468927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2213468927
Directory	/workspace/7.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all.2523676410
Short name	T439
Test name
Test status
Simulation time	756841537122 ps
CPU time	5533.61 seconds
Started	Jun 07 07:33:52 PM PDT 24
Finished	Jun 07 09:06:10 PM PDT 24
Peak memory	377892 kb
Host	smart-26ea966e-e608-4478-b3d0-562cad2d141f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523676410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.2523676410
Directory	/workspace/7.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.821501094
Short name	T332
Test name
Test status
Simulation time	2044312537 ps
CPU time	369.87 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:40:07 PM PDT 24
Peak memory	359992 kb
Host	smart-358c8267-8436-42a7-bb64-6c52e39199c2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=821501094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.821501094
Directory	/workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2924842147
Short name	T100
Test name
Test status
Simulation time	37589907287 ps
CPU time	191.75 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:37:08 PM PDT 24
Peak memory	202948 kb
Host	smart-929a8838-41a4-4b41-96ae-02faaf0cd79f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924842147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.2924842147
Directory	/workspace/7.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2082209151
Short name	T479
Test name
Test status
Simulation time	93153971 ps
CPU time	23.69 seconds
Started	Jun 07 07:33:51 PM PDT 24
Finished	Jun 07 07:34:18 PM PDT 24
Peak memory	279860 kb
Host	smart-faf04e1a-c81a-4d33-ab47-0aa060377a1c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082209151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2082209151
Directory	/workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2505387480
Short name	T581
Test name
Test status
Simulation time	14064157796 ps
CPU time	1022.83 seconds
Started	Jun 07 07:34:08 PM PDT 24
Finished	Jun 07 07:51:14 PM PDT 24
Peak memory	371444 kb
Host	smart-0cf3f52f-75e5-4c30-bfc0-a0e606a7a00b
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505387480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.2505387480
Directory	/workspace/8.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/8.sram_ctrl_alert_test.722437947
Short name	T537
Test name
Test status
Simulation time	13752818 ps
CPU time	0.67 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:34:10 PM PDT 24
Peak memory	202500 kb
Host	smart-15296d90-7983-43b6-a2e3-5bdfbfd33398
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722437947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.722437947
Directory	/workspace/8.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.sram_ctrl_bijection.2857085886
Short name	T384
Test name
Test status
Simulation time	6110884784 ps
CPU time	34.51 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:34:31 PM PDT 24
Peak memory	202924 kb
Host	smart-d209a938-d4e3-4901-b666-b2aa3836f0cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857085886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 2857085886
Directory	/workspace/8.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/8.sram_ctrl_executable.1686012402
Short name	T438
Test name
Test status
Simulation time	2970089342 ps
CPU time	728.64 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:46:19 PM PDT 24
Peak memory	375852 kb
Host	smart-06f997aa-ed4c-4208-a8fa-26b1b29e83f0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686012402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.1686012402
Directory	/workspace/8.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/8.sram_ctrl_lc_escalation.3168279513
Short name	T592
Test name
Test status
Simulation time	416737146 ps
CPU time	2.09 seconds
Started	Jun 07 07:33:59 PM PDT 24
Finished	Jun 07 07:34:02 PM PDT 24
Peak memory	211156 kb
Host	smart-aef21369-ac10-4a0d-b089-24ffe88f5ad0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168279513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.3168279513
Directory	/workspace/8.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/8.sram_ctrl_max_throughput.705598241
Short name	T229
Test name
Test status
Simulation time	141987645 ps
CPU time	120.06 seconds
Started	Jun 07 07:33:59 PM PDT 24
Finished	Jun 07 07:36:01 PM PDT 24
Peak memory	370404 kb
Host	smart-4ba5237b-1f96-4978-a1f3-76c2b22c0b77
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705598241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.sram_ctrl_max_throughput.705598241
Directory	/workspace/8.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1648275301
Short name	T714
Test name
Test status
Simulation time	358098703 ps
CPU time	5.46 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:34:14 PM PDT 24
Peak memory	211052 kb
Host	smart-3ba5947b-1f84-407e-8792-3a80b58f5e95
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648275301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1648275301
Directory	/workspace/8.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_mem_walk.3698979160
Short name	T831
Test name
Test status
Simulation time	545080316 ps
CPU time	8.78 seconds
Started	Jun 07 07:34:04 PM PDT 24
Finished	Jun 07 07:34:14 PM PDT 24
Peak memory	211116 kb
Host	smart-82f91fc3-8d71-4262-8aac-b684d00fcda2
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698979160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.3698979160
Directory	/workspace/8.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/8.sram_ctrl_multiple_keys.2377452392
Short name	T138
Test name
Test status
Simulation time	35252118799 ps
CPU time	713.04 seconds
Started	Jun 07 07:33:54 PM PDT 24
Finished	Jun 07 07:45:50 PM PDT 24
Peak memory	371440 kb
Host	smart-932f1b25-5627-4e91-98ec-003b578aae15
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377452392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip le_keys.2377452392
Directory	/workspace/8.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access.1060146505
Short name	T525
Test name
Test status
Simulation time	2946429540 ps
CPU time	13.25 seconds
Started	Jun 07 07:34:01 PM PDT 24
Finished	Jun 07 07:34:16 PM PDT 24
Peak memory	202956 kb
Host	smart-9a4aef58-63c2-47c9-9a18-d25d19d83b8d
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060146505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.1060146505
Directory	/workspace/8.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2355653
Short name	T458
Test name
Test status
Simulation time	79152806965 ps
CPU time	521.49 seconds
Started	Jun 07 07:34:02 PM PDT 24
Finished	Jun 07 07:42:45 PM PDT 24
Peak memory	202956 kb
Host	smart-4edd424a-99ea-4020-88d4-ee6ef48fbb98
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_partial_access_b2b.2355653
Directory	/workspace/8.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/8.sram_ctrl_ram_cfg.3222817055
Short name	T352
Test name
Test status
Simulation time	47620330 ps
CPU time	0.83 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:34:11 PM PDT 24
Peak memory	202900 kb
Host	smart-5b9bb38e-b22c-4fdd-9f33-b66e96ef6d31
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222817055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3222817055
Directory	/workspace/8.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/8.sram_ctrl_smoke.956676614
Short name	T468
Test name
Test status
Simulation time	1573265513 ps
CPU time	8.81 seconds
Started	Jun 07 07:33:53 PM PDT 24
Finished	Jun 07 07:34:05 PM PDT 24
Peak memory	202908 kb
Host	smart-8a8e2108-1443-407e-8321-d5f386d627c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956676614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.956676614
Directory	/workspace/8.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all.212287077
Short name	T834
Test name
Test status
Simulation time	57824647959 ps
CPU time	5152.16 seconds
Started	Jun 07 07:34:08 PM PDT 24
Finished	Jun 07 09:00:03 PM PDT 24
Peak memory	377864 kb
Host	smart-0ea5a51e-f4dd-4f28-bdd5-a0b0b4130731
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212287077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_stress_all.212287077
Directory	/workspace/8.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3336607105
Short name	T877
Test name
Test status
Simulation time	638988225 ps
CPU time	37.09 seconds
Started	Jun 07 07:34:08 PM PDT 24
Finished	Jun 07 07:34:48 PM PDT 24
Peak memory	295332 kb
Host	smart-1c3755c5-3aa9-4b75-9939-a024f8fde844
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3336607105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3336607105
Directory	/workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.sram_ctrl_stress_pipeline.858774725
Short name	T417
Test name
Test status
Simulation time	2065004646 ps
CPU time	204.49 seconds
Started	Jun 07 07:34:01 PM PDT 24
Finished	Jun 07 07:37:27 PM PDT 24
Peak memory	202888 kb
Host	smart-07118123-67b9-4263-9211-d60aeea539b7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858774725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. sram_ctrl_stress_pipeline.858774725
Directory	/workspace/8.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3870879216
Short name	T504
Test name
Test status
Simulation time	161341215 ps
CPU time	136.11 seconds
Started	Jun 07 07:33:59 PM PDT 24
Finished	Jun 07 07:36:17 PM PDT 24
Peak memory	370384 kb
Host	smart-cbffd505-a7c4-4792-80d4-c0e3ba878d21
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870879216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.3870879216
Directory	/workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location	/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3410822844
Short name	T233
Test name
Test status
Simulation time	7552824995 ps
CPU time	417.68 seconds
Started	Jun 07 07:34:05 PM PDT 24
Finished	Jun 07 07:41:04 PM PDT 24
Peak memory	370028 kb
Host	smart-95b901e0-e21d-43fe-b7ab-bb51308b9706
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410822844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3410822844
Directory	/workspace/9.sram_ctrl_access_during_key_req/latest

Test location	/workspace/coverage/default/9.sram_ctrl_alert_test.2495218170
Short name	T428
Test name
Test status
Simulation time	14796045 ps
CPU time	0.66 seconds
Started	Jun 07 07:34:13 PM PDT 24
Finished	Jun 07 07:34:15 PM PDT 24
Peak memory	202660 kb
Host	smart-7fc2b3cd-4e5b-4be6-91ec-f076e0cf2b1a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495218170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.2495218170
Directory	/workspace/9.sram_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.sram_ctrl_bijection.2841824482
Short name	T607
Test name
Test status
Simulation time	851082569 ps
CPU time	57.31 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:35:06 PM PDT 24
Peak memory	202940 kb
Host	smart-f1f248a4-5165-4032-9b50-d81b64cc7193
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841824482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 2841824482
Directory	/workspace/9.sram_ctrl_bijection/latest

Test location	/workspace/coverage/default/9.sram_ctrl_executable.493270046
Short name	T454
Test name
Test status
Simulation time	118894467056 ps
CPU time	1320.47 seconds
Started	Jun 07 07:34:14 PM PDT 24
Finished	Jun 07 07:56:17 PM PDT 24
Peak memory	374620 kb
Host	smart-aff03ae5-39c1-4117-a93d-59927b828d3d
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493270046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable .493270046
Directory	/workspace/9.sram_ctrl_executable/latest

Test location	/workspace/coverage/default/9.sram_ctrl_lc_escalation.3514589787
Short name	T21
Test name
Test status
Simulation time	471654680 ps
CPU time	5.42 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:34:15 PM PDT 24
Peak memory	202984 kb
Host	smart-ad3a3ff2-37ef-4160-83de-c034b0977b4f
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514589787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.3514589787
Directory	/workspace/9.sram_ctrl_lc_escalation/latest

Test location	/workspace/coverage/default/9.sram_ctrl_max_throughput.90693364
Short name	T180
Test name
Test status
Simulation time	126921597 ps
CPU time	71.23 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:35:21 PM PDT 24
Peak memory	347616 kb
Host	smart-82cf2320-d6ab-4cda-96c5-21e099f0c87c
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90693364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_max_throughput.90693364
Directory	/workspace/9.sram_ctrl_max_throughput/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3066170852
Short name	T300
Test name
Test status
Simulation time	147638111 ps
CPU time	2.91 seconds
Started	Jun 07 07:34:16 PM PDT 24
Finished	Jun 07 07:34:21 PM PDT 24
Peak memory	211092 kb
Host	smart-597864dd-d7f7-4620-bf42-e7301437406c
User	root
Command	/workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066170852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.3066170852
Directory	/workspace/9.sram_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_mem_walk.377049
Short name	T746
Test name
Test status
Simulation time	448600617 ps
CPU time	10.4 seconds
Started	Jun 07 07:34:15 PM PDT 24
Finished	Jun 07 07:34:27 PM PDT 24
Peak memory	211040 kb
Host	smart-f32ac3ae-ff5e-434b-b6c4-ba9a790224b7
User	root
Command	/workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem _walk.377049
Directory	/workspace/9.sram_ctrl_mem_walk/latest

Test location	/workspace/coverage/default/9.sram_ctrl_multiple_keys.1238151466
Short name	T499
Test name
Test status
Simulation time	29208143691 ps
CPU time	732.51 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:46:22 PM PDT 24
Peak memory	375140 kb
Host	smart-374fbae3-2b2e-43ae-9327-390a66e42266
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238151466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1238151466
Directory	/workspace/9.sram_ctrl_multiple_keys/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access.1790832332
Short name	T492
Test name
Test status
Simulation time	372972398 ps
CPU time	5.03 seconds
Started	Jun 07 07:34:11 PM PDT 24
Finished	Jun 07 07:34:18 PM PDT 24
Peak memory	202872 kb
Host	smart-866d0a91-0136-4878-ae99-2a36cc6bde1e
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790832332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.1790832332
Directory	/workspace/9.sram_ctrl_partial_access/latest

Test location	/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4236355490
Short name	T636
Test name
Test status
Simulation time	4368244207 ps
CPU time	323.77 seconds
Started	Jun 07 07:34:09 PM PDT 24
Finished	Jun 07 07:39:36 PM PDT 24
Peak memory	202992 kb
Host	smart-afbc5479-4293-4d22-8b8c-626b5bc21622
User	root
Command	/workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236355490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.4236355490
Directory	/workspace/9.sram_ctrl_partial_access_b2b/latest

Test location	/workspace/coverage/default/9.sram_ctrl_ram_cfg.1471063274
Short name	T752
Test name
Test status
Simulation time	78951680 ps
CPU time	0.73 seconds
Started	Jun 07 07:34:16 PM PDT 24
Finished	Jun 07 07:34:20 PM PDT 24
Peak memory	202924 kb
Host	smart-512ef479-1e8b-4e25-ac2a-5f58cb1b7fb1
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471063274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1471063274
Directory	/workspace/9.sram_ctrl_ram_cfg/latest

Test location	/workspace/coverage/default/9.sram_ctrl_regwen.3075361858
Short name	T18
Test name
Test status
Simulation time	15156781277 ps
CPU time	752.73 seconds
Started	Jun 07 07:34:18 PM PDT 24
Finished	Jun 07 07:46:53 PM PDT 24
Peak memory	373900 kb
Host	smart-3a7551b8-23a8-4814-99e5-ea22d28485a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075361858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3075361858
Directory	/workspace/9.sram_ctrl_regwen/latest

Test location	/workspace/coverage/default/9.sram_ctrl_smoke.2778799073
Short name	T293
Test name
Test status
Simulation time	4628627435 ps
CPU time	30.13 seconds
Started	Jun 07 07:34:10 PM PDT 24
Finished	Jun 07 07:34:42 PM PDT 24
Peak memory	277104 kb
Host	smart-cc0fbc64-ecbc-4581-becd-892ee193f8f9
User	root
Command	/workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778799073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2778799073
Directory	/workspace/9.sram_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all.738995470
Short name	T720
Test name
Test status
Simulation time	48703585205 ps
CPU time	1653.84 seconds
Started	Jun 07 07:34:14 PM PDT 24
Finished	Jun 07 08:01:50 PM PDT 24
Peak memory	375720 kb
Host	smart-ffa8ddef-cd2f-49ca-96fe-6542cbc59a8c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738995470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_stress_all.738995470
Directory	/workspace/9.sram_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4219264905
Short name	T705
Test name
Test status
Simulation time	1696712310 ps
CPU time	410.53 seconds
Started	Jun 07 07:34:15 PM PDT 24
Finished	Jun 07 07:41:07 PM PDT 24
Peak memory	378524 kb
Host	smart-c10b25cf-db18-4a58-92fc-fa3cb56c98fb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4219264905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.4219264905
Directory	/workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3727021236
Short name	T586
Test name
Test status
Simulation time	11182898638 ps
CPU time	284.5 seconds
Started	Jun 07 07:34:05 PM PDT 24
Finished	Jun 07 07:38:51 PM PDT 24
Peak memory	203000 kb
Host	smart-6135e79b-92e0-48e3-bc4e-3e7ac173303a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727021236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.3727021236
Directory	/workspace/9.sram_ctrl_stress_pipeline/latest

Test location	/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2030343021
Short name	T245
Test name
Test status
Simulation time	602245075 ps
CPU time	27.76 seconds
Started	Jun 07 07:34:07 PM PDT 24
Finished	Jun 07 07:34:37 PM PDT 24
Peak memory	289908 kb
Host	smart-f0846640-2e9e-45f0-9287-e6d10ecd24cf
User	root
Command	/workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030343021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2030343021
Directory	/workspace/9.sram_ctrl_throughput_w_partial_write/latest

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