Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13957020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61045022

1

T1

243873

T2

62

T3

21920

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37391280	1			T1	133833		T2	342		T3	11225
values[0x0]	17404637	1			T1	64524		T2	190		T3	5996
values[0x1]	20206125	1			T1	69822		T2	406		T3	6575

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6954087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68047955

1

T1

256046

T2

433

T3

22886

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	272123	1			T1	1008		T2	4		T3	108
valid_sources[0x01]	259706	1			T1	1035		T2	5		T3	89
valid_sources[0x02]	281300	1			T1	933		T2	4		T3	90
valid_sources[0x03]	304578	1			T1	987		T2	7		T3	66
valid_sources[0x04]	271388	1			T1	1104		T3	89		T9	856
valid_sources[0x05]	319362	1			T1	1006		T2	2		T3	100
valid_sources[0x06]	396906	1			T1	970		T2	2		T3	93
valid_sources[0x07]	286235	1			T1	1051		T2	2		T3	107
valid_sources[0x08]	313393	1			T1	1178		T2	6		T3	90
valid_sources[0x09]	302748	1			T1	1172		T2	1		T3	72
valid_sources[0x0a]	274035	1			T1	840		T2	4		T3	88
valid_sources[0x0b]	276879	1			T1	1095		T3	84		T4	35
valid_sources[0x0c]	314288	1			T1	1007		T2	1		T3	80
valid_sources[0x0d]	303022	1			T1	1144		T2	4		T3	87
valid_sources[0x0e]	329738	1			T1	1014		T3	91		T4	40
valid_sources[0x0f]	293680	1			T1	974		T2	2		T3	99
valid_sources[0x10]	278120	1			T1	876		T2	2		T3	107
valid_sources[0x11]	340971	1			T1	936		T2	7		T3	88
valid_sources[0x12]	283997	1			T1	1064		T2	16		T3	87
valid_sources[0x13]	271145	1			T1	910		T3	91		T9	788
valid_sources[0x14]	276553	1			T1	1009		T2	2		T3	116
valid_sources[0x15]	328028	1			T1	1172		T2	2		T3	100
valid_sources[0x16]	263653	1			T1	1078		T2	1		T3	74
valid_sources[0x17]	264483	1			T1	1144		T2	5		T3	90
valid_sources[0x18]	268420	1			T1	1122		T2	8		T3	100
valid_sources[0x19]	283704	1			T1	896		T2	2		T3	90
valid_sources[0x1a]	297760	1			T1	966		T2	5		T3	102
valid_sources[0x1b]	283848	1			T1	1138		T2	5		T3	101
valid_sources[0x1c]	260017	1			T1	1039		T2	2		T3	109
valid_sources[0x1d]	259425	1			T1	1081		T2	4		T3	67
valid_sources[0x1e]	268007	1			T1	943		T2	2		T3	117
valid_sources[0x1f]	268286	1			T1	1133		T2	2		T3	80
valid_sources[0x20]	281964	1			T1	1066		T2	4		T3	103
valid_sources[0x21]	304942	1			T1	997		T2	2		T3	87
valid_sources[0x22]	302410	1			T1	978		T2	3		T3	86
valid_sources[0x23]	262322	1			T1	1047		T2	3		T3	71
valid_sources[0x24]	273057	1			T1	913		T2	5		T3	98
valid_sources[0x25]	315662	1			T1	1266		T2	10		T3	117
valid_sources[0x26]	431970	1			T1	1155		T2	8		T3	100
valid_sources[0x27]	426738	1			T1	1226		T3	85		T9	840
valid_sources[0x28]	292491	1			T1	960		T2	1		T3	80
valid_sources[0x29]	356641	1			T1	1179		T2	1		T3	86
valid_sources[0x2a]	264483	1			T1	1082		T2	5		T3	83
valid_sources[0x2b]	271422	1			T1	1121		T2	11		T3	103
valid_sources[0x2c]	280927	1			T1	880		T2	7		T3	95
valid_sources[0x2d]	261106	1			T1	1172		T2	4		T3	86
valid_sources[0x2e]	296170	1			T1	942		T2	4		T3	84
valid_sources[0x2f]	294170	1			T1	1029		T3	96		T9	766
valid_sources[0x30]	292076	1			T1	1287		T2	4		T3	93
valid_sources[0x31]	287852	1			T1	991		T2	10		T3	67
valid_sources[0x32]	348539	1			T1	1249		T2	8		T3	90
valid_sources[0x33]	276556	1			T1	1149		T2	1		T3	83
valid_sources[0x34]	274580	1			T1	892		T2	3		T3	93
valid_sources[0x35]	296189	1			T1	860		T2	12		T3	99
valid_sources[0x36]	296258	1			T1	871		T2	8		T3	94
valid_sources[0x37]	288928	1			T1	1281		T2	1		T3	75
valid_sources[0x38]	345757	1			T1	1152		T2	1		T3	103
valid_sources[0x39]	340544	1			T1	1168		T2	1		T3	116
valid_sources[0x3a]	276755	1			T1	1081		T3	101		T9	866
valid_sources[0x3b]	329035	1			T1	1212		T2	12		T3	84
valid_sources[0x3c]	276752	1			T1	1082		T2	12		T3	85
valid_sources[0x3d]	313454	1			T1	905		T2	2		T3	98
valid_sources[0x3e]	305588	1			T1	1052		T2	4		T3	88
valid_sources[0x3f]	280185	1			T1	1096		T2	2		T3	83
valid_sources[0x40]	324092	1			T1	1012		T2	1		T3	85
valid_sources[0x41]	283553	1			T1	1026		T2	1		T3	97
valid_sources[0x42]	271546	1			T1	1103		T2	4		T3	95
valid_sources[0x43]	289392	1			T1	1004		T2	6		T3	79
valid_sources[0x44]	277047	1			T1	999		T2	1		T3	82
valid_sources[0x45]	310859	1			T1	1147		T2	4		T3	96
valid_sources[0x46]	273101	1			T1	1127		T3	103		T9	834
valid_sources[0x47]	266033	1			T1	1084		T2	2		T3	117
valid_sources[0x48]	263715	1			T1	1146		T2	1		T3	96
valid_sources[0x49]	325840	1			T1	1229		T2	6		T3	89
valid_sources[0x4a]	385390	1			T1	1125		T3	111		T9	826
valid_sources[0x4b]	284047	1			T1	1060		T2	4		T3	72
valid_sources[0x4c]	270479	1			T1	1041		T2	6		T3	90
valid_sources[0x4d]	267496	1			T1	1156		T2	1		T3	89
valid_sources[0x4e]	310563	1			T1	1057		T2	10		T3	92
valid_sources[0x4f]	272102	1			T1	1118		T2	4		T3	83
valid_sources[0x50]	297669	1			T1	1024		T2	5		T3	87
valid_sources[0x51]	269017	1			T1	1243		T2	2		T3	109
valid_sources[0x52]	285655	1			T1	1113		T2	1		T3	106
valid_sources[0x53]	322512	1			T1	990		T2	4		T3	98
valid_sources[0x54]	276671	1			T1	945		T2	8		T3	96
valid_sources[0x55]	282141	1			T1	1142		T3	97		T9	730
valid_sources[0x56]	296460	1			T1	1092		T2	1		T3	89
valid_sources[0x57]	275116	1			T1	863		T2	12		T3	97
valid_sources[0x58]	453334	1			T1	1166		T2	6		T3	102
valid_sources[0x59]	283940	1			T1	1146		T2	2		T3	124
valid_sources[0x5a]	330234	1			T1	1135		T2	4		T3	90
valid_sources[0x5b]	281032	1			T1	1169		T2	1		T3	84
valid_sources[0x5c]	335473	1			T1	844		T2	3		T3	92
valid_sources[0x5d]	268812	1			T1	944		T2	4		T3	97
valid_sources[0x5e]	291607	1			T1	1094		T3	96		T9	826
valid_sources[0x5f]	277904	1			T1	1128		T3	88		T9	860
valid_sources[0x60]	349048	1			T1	1054		T2	1		T3	88
valid_sources[0x61]	278237	1			T1	1062		T2	4		T3	98
valid_sources[0x62]	265126	1			T1	1048		T2	1		T3	85
valid_sources[0x63]	360483	1			T1	1058		T3	80		T4	25
valid_sources[0x64]	291728	1			T1	1084		T2	3		T3	76
valid_sources[0x65]	332497	1			T1	972		T2	4		T3	88
valid_sources[0x66]	263315	1			T1	1111		T2	8		T3	77
valid_sources[0x67]	297427	1			T1	1086		T2	3		T3	92
valid_sources[0x68]	272286	1			T1	1030		T2	3		T3	104
valid_sources[0x69]	261946	1			T1	1009		T2	6		T3	101
valid_sources[0x6a]	259509	1			T1	1089		T3	100		T9	852
valid_sources[0x6b]	352883	1			T1	913		T2	2		T3	91
valid_sources[0x6c]	260558	1			T1	1106		T2	6		T3	84
valid_sources[0x6d]	271162	1			T1	1051		T2	13		T3	91
valid_sources[0x6e]	305937	1			T1	965		T2	7		T3	89
valid_sources[0x6f]	298436	1			T1	1142		T2	3		T3	89
valid_sources[0x70]	284087	1			T1	1063		T3	85		T9	900
valid_sources[0x71]	322792	1			T1	1080		T3	102		T4	196
valid_sources[0x72]	266968	1			T1	1157		T2	2		T3	110
valid_sources[0x73]	276211	1			T1	1028		T2	5		T3	90
valid_sources[0x74]	282629	1			T1	1273		T2	9		T3	111
valid_sources[0x75]	308078	1			T1	1059		T2	2		T3	106
valid_sources[0x76]	327371	1			T1	917		T2	4		T3	108
valid_sources[0x77]	325025	1			T1	1060		T2	10		T3	97
valid_sources[0x78]	272647	1			T1	1135		T2	1		T3	100
valid_sources[0x79]	263501	1			T1	934		T2	1		T3	85
valid_sources[0x7a]	272649	1			T1	1155		T2	5		T3	86
valid_sources[0x7b]	337632	1			T1	1034		T2	3		T3	88
valid_sources[0x7c]	276497	1			T1	1196		T2	5		T3	82
valid_sources[0x7d]	280153	1			T1	1110		T2	4		T3	86
valid_sources[0x7e]	258052	1			T1	1125		T2	9		T3	96
valid_sources[0x7f]	287575	1			T1	1000		T2	5		T3	72
valid_sources[0x80]	325523	1			T1	1221		T2	2		T3	92

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30420587

1

T1

121845

T2

6

T3

10299

values[0x0]

all_enables

biggest_size

15310872

1

T1

60838

T2

25

T3

5724

values[0x1]

all_enables

biggest_size

15313563

1

T1

61190

T2

31

T3

5897

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140748

1

T1

1

T2

2

T3

1958

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50004	1			T3	585		T4	605		T9	22
values[0x0]	60965	1			T2	2		T3	766		T4	766
values[0x1]	64939	1			T1	3		T2	1		T3	796

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149432

1

T1

2

T2

2

T3

2024

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	470	1			T9	1		T53	2		T15	5
valid_sources[0x01]	613	1			T4	3		T15	6		T28	2
valid_sources[0x02]	491	1			T3	4		T9	1		T15	10
valid_sources[0x03]	539	1			T15	8		T38	11		T132	1
valid_sources[0x04]	1076	1			T15	14		T38	2		T42	3
valid_sources[0x05]	611	1			T9	1		T15	5		T38	14
valid_sources[0x06]	599	1			T10	1		T15	4		T38	10
valid_sources[0x07]	686	1			T15	4		T38	9		T42	6
valid_sources[0x08]	528	1			T14	3		T15	13		T38	10
valid_sources[0x09]	484	1			T9	1		T68	1		T15	3
valid_sources[0x0a]	527	1			T15	8		T38	12		T22	2
valid_sources[0x0b]	598	1			T4	3		T15	5		T38	11
valid_sources[0x0c]	770	1			T14	1		T15	9		T38	11
valid_sources[0x0d]	631	1			T9	1		T15	8		T38	14
valid_sources[0x0e]	671	1			T20	1		T15	11		T38	14
valid_sources[0x0f]	674	1			T15	8		T38	4		T22	2
valid_sources[0x10]	496	1			T15	6		T38	7		T133	1
valid_sources[0x11]	837	1			T15	8		T38	9		T6	1
valid_sources[0x12]	718	1			T15	12		T38	4		T127	1
valid_sources[0x13]	763	1			T9	2		T20	1		T15	3
valid_sources[0x14]	575	1			T14	1		T15	10		T38	12
valid_sources[0x15]	591	1			T15	3		T38	12		T22	1
valid_sources[0x16]	822	1			T4	3		T14	1		T15	11
valid_sources[0x17]	927	1			T3	3		T15	14		T38	8
valid_sources[0x18]	843	1			T14	3		T15	4		T38	7
valid_sources[0x19]	700	1			T4	7		T9	2		T15	8
valid_sources[0x1a]	571	1			T3	4		T9	2		T15	7
valid_sources[0x1b]	979	1			T3	140		T15	9		T38	3
valid_sources[0x1c]	620	1			T15	8		T38	15		T40	1
valid_sources[0x1d]	773	1			T9	1		T15	8		T38	5
valid_sources[0x1e]	709	1			T9	1		T15	8		T38	12
valid_sources[0x1f]	727	1			T9	2		T15	14		T38	8
valid_sources[0x20]	531	1			T91	1		T15	6		T71	1
valid_sources[0x21]	725	1			T1	1		T9	1		T15	2
valid_sources[0x22]	625	1			T3	5		T9	1		T36	2
valid_sources[0x23]	677	1			T9	1		T15	6		T38	4
valid_sources[0x24]	864	1			T9	1		T53	1		T15	11
valid_sources[0x25]	586	1			T3	3		T14	6		T15	8
valid_sources[0x26]	727	1			T9	1		T15	7		T28	2
valid_sources[0x27]	674	1			T4	3		T14	1		T15	8
valid_sources[0x28]	727	1			T9	1		T15	10		T38	9
valid_sources[0x29]	593	1			T15	8		T38	10		T127	2
valid_sources[0x2a]	685	1			T12	3		T15	6		T38	7
valid_sources[0x2b]	594	1			T15	10		T38	10		T6	1
valid_sources[0x2c]	650	1			T15	6		T38	7		T133	3
valid_sources[0x2d]	941	1			T15	5		T38	6		T42	20
valid_sources[0x2e]	840	1			T3	3		T9	1		T14	1
valid_sources[0x2f]	602	1			T9	1		T15	11		T38	15
valid_sources[0x30]	539	1			T58	1		T15	9		T38	6
valid_sources[0x31]	549	1			T9	1		T15	5		T38	13
valid_sources[0x32]	681	1			T3	17		T15	6		T38	11
valid_sources[0x33]	546	1			T15	3		T38	13		T127	1
valid_sources[0x34]	877	1			T2	1		T9	2		T15	8
valid_sources[0x35]	735	1			T3	6		T9	1		T53	1
valid_sources[0x36]	718	1			T3	186		T15	6		T38	6
valid_sources[0x37]	555	1			T15	9		T38	13		T22	1
valid_sources[0x38]	600	1			T9	1		T15	8		T38	8
valid_sources[0x39]	567	1			T4	59		T15	6		T38	8
valid_sources[0x3a]	731	1			T4	155		T15	10		T38	15
valid_sources[0x3b]	608	1			T15	7		T38	10		T92	4
valid_sources[0x3c]	794	1			T15	1		T38	7		T134	1
valid_sources[0x3d]	580	1			T15	9		T38	20		T6	1
valid_sources[0x3e]	679	1			T9	2		T15	11		T38	15
valid_sources[0x3f]	580	1			T3	2		T15	4		T38	10
valid_sources[0x40]	706	1			T9	1		T15	10		T38	11
valid_sources[0x41]	672	1			T9	3		T15	9		T38	10
valid_sources[0x42]	601	1			T9	1		T15	7		T38	17
valid_sources[0x43]	706	1			T15	4		T38	14		T126	1
valid_sources[0x44]	589	1			T53	1		T15	7		T38	11
valid_sources[0x45]	510	1			T14	2		T15	2		T38	4
valid_sources[0x46]	770	1			T4	4		T15	7		T38	15
valid_sources[0x47]	718	1			T15	7		T38	9		T135	1
valid_sources[0x48]	791	1			T9	1		T15	11		T38	11
valid_sources[0x49]	1071	1			T4	187		T9	1		T11	1
valid_sources[0x4a]	691	1			T4	3		T9	1		T15	3
valid_sources[0x4b]	944	1			T15	5		T38	12		T7	1
valid_sources[0x4c]	669	1			T4	103		T15	7		T38	7
valid_sources[0x4d]	744	1			T4	108		T15	7		T38	11
valid_sources[0x4e]	798	1			T9	1		T53	2		T15	8
valid_sources[0x4f]	680	1			T9	1		T14	2		T15	3
valid_sources[0x50]	750	1			T15	5		T38	7		T22	1
valid_sources[0x51]	570	1			T4	3		T15	4		T38	12
valid_sources[0x52]	916	1			T4	5		T9	1		T15	2
valid_sources[0x53]	744	1			T3	119		T10	1		T15	3
valid_sources[0x54]	626	1			T53	1		T15	7		T38	12
valid_sources[0x55]	609	1			T9	1		T15	5		T38	7
valid_sources[0x56]	806	1			T9	1		T15	4		T38	12
valid_sources[0x57]	821	1			T4	91		T15	5		T38	13
valid_sources[0x58]	689	1			T15	7		T38	10		T56	5
valid_sources[0x59]	833	1			T9	2		T15	6		T38	6
valid_sources[0x5a]	598	1			T15	5		T70	1		T38	9
valid_sources[0x5b]	744	1			T9	1		T21	1		T15	9
valid_sources[0x5c]	1011	1			T15	7		T38	12		T133	1
valid_sources[0x5d]	756	1			T14	2		T53	3		T15	9
valid_sources[0x5e]	648	1			T15	16		T38	8		T136	2
valid_sources[0x5f]	598	1			T9	1		T15	4		T38	12
valid_sources[0x60]	704	1			T4	3		T15	7		T38	8
valid_sources[0x61]	690	1			T4	3		T27	20		T15	10
valid_sources[0x62]	856	1			T15	6		T38	7		T133	1
valid_sources[0x63]	585	1			T15	10		T38	14		T42	23
valid_sources[0x64]	867	1			T9	1		T15	3		T38	11
valid_sources[0x65]	611	1			T15	3		T38	11		T127	1
valid_sources[0x66]	509	1			T9	1		T15	8		T38	11
valid_sources[0x67]	598	1			T14	4		T15	3		T38	7
valid_sources[0x68]	565	1			T9	2		T15	12		T38	9
valid_sources[0x69]	650	1			T15	7		T38	11		T134	1
valid_sources[0x6a]	892	1			T4	92		T15	5		T71	1
valid_sources[0x6b]	605	1			T58	1		T15	4		T38	10
valid_sources[0x6c]	559	1			T3	5		T9	1		T15	4
valid_sources[0x6d]	621	1			T15	8		T38	10		T22	1
valid_sources[0x6e]	668	1			T15	9		T38	5		T29	3
valid_sources[0x6f]	556	1			T9	1		T14	5		T15	2
valid_sources[0x70]	970	1			T15	5		T38	7		T8	8
valid_sources[0x71]	604	1			T9	1		T15	6		T38	19
valid_sources[0x72]	579	1			T15	7		T38	8		T127	1
valid_sources[0x73]	978	1			T15	2		T38	12		T127	1
valid_sources[0x74]	751	1			T9	1		T15	4		T38	12
valid_sources[0x75]	888	1			T4	230		T15	6		T28	2
valid_sources[0x76]	727	1			T9	1		T15	7		T38	13
valid_sources[0x77]	605	1			T68	1		T15	7		T5	35
valid_sources[0x78]	860	1			T3	155		T14	2		T15	10
valid_sources[0x79]	723	1			T4	56		T9	1		T53	2
valid_sources[0x7a]	816	1			T1	1		T15	8		T38	12
valid_sources[0x7b]	715	1			T15	13		T38	10		T7	1
valid_sources[0x7c]	717	1			T9	2		T15	9		T38	7
valid_sources[0x7d]	971	1			T9	2		T15	6		T38	8
valid_sources[0x7e]	910	1			T3	112		T4	100		T15	6
valid_sources[0x7f]	810	1			T2	1		T53	1		T20	1
valid_sources[0x80]	668	1			T9	1		T15	5		T71	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38329

1

T3

531

T4

546

T9

11

values[0x0]

all_enables

biggest_size

52614

1

T2

1

T3

734

T4

753

values[0x1]

all_enables

biggest_size

49805

1

T1

1

T2

1

T3

693