Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13657092

1

T1

24306

T2

876

T3

3939

full_word

56063460

1

T1

243873

T2

62

T3

18381

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69720282	1			T1	268179		T2	938		T3	22320
auto[TlIntgErrCmd]	90	1			T47	1		T48	5		T49	6
auto[TlIntgErrData]	91	1			T47	4		T48	2		T49	2
auto[TlIntgErrBoth]	89	1			T47	5		T48	3		T49	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32037386

1

T1

133833

T2

342

T3

7584

auto[1]

37683166

1

T1

134346

T2

596

T3

14736

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6520253	1			T1	11988		T2	336		T3	1059
auto[TlIntgErrNone]	partial	auto[1]	7136585	1			T1	12318		T2	540		T3	2880
auto[TlIntgErrNone]	full_word	auto[0]	25517013	1			T1	121845		T2	6		T3	6525
auto[TlIntgErrNone]	full_word	auto[1]	30546431	1			T1	122028		T2	56		T3	11856
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T47	1		T49	5		T114	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T48	5		T49	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T116	1		T117	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T119	1		T118	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T47	4		T48	1		T114	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T48	1		T49	2		T114	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T120	1		T121	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T47	2		T48	2		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T47	2		T49	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T47	1		T121	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T48	1		T114	1		T115	1