Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	688121	1			T9	1238		T11	580		T27	715
auto[1]	10468842	1			T1	112462		T3	1		T4	9
auto[2]	596803	1			T9	769		T11	570		T27	638
auto[3]	10390141	1			T1	112978		T3	1		T4	13

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14455792	1			T1	186163		T3	1		T4	16
auto[1]	2127687	1			T1	18808		T4	4		T9	313
auto[2]	2128645	1			T1	18594		T3	1		T4	1
auto[3]	3431783	1			T1	1875		T4	1		T9	36

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8523491

1

T3

2

T4

22

T9

3336

auto[1]

13620416

1

T1

225440

T9

1

T10

99989

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	373616	1			T9	1015		T11	17		T27	590
auto[0]	auto[0]	auto[1]	38540	1			T9	114		T11	81		T27	63
auto[0]	auto[0]	auto[2]	38822	1			T9	100		T11	84		T27	58
auto[0]	auto[0]	auto[3]	9989	1			T9	8		T11	397		T27	4
auto[0]	auto[1]	auto[0]	3132287	1			T3	1		T4	5		T9	663
auto[0]	auto[1]	auto[1]	343851	1			T4	3		T9	119		T11	87
auto[0]	auto[1]	auto[2]	316652	1			T9	81		T10	1		T11	45
auto[0]	auto[1]	auto[3]	66872	1			T4	1		T9	9		T11	433
auto[0]	auto[2]	auto[0]	327654	1			T9	608		T11	13		T27	549
auto[0]	auto[2]	auto[1]	33564	1			T9	51		T11	46		T27	51
auto[0]	auto[2]	auto[2]	30062	1			T9	102		T11	90		T27	32
auto[0]	auto[2]	auto[3]	8134	1			T9	8		T11	421		T27	5
auto[0]	auto[3]	auto[0]	3089213	1			T4	11		T9	302		T10	10
auto[0]	auto[3]	auto[1]	311764	1			T4	1		T9	29		T10	2
auto[0]	auto[3]	auto[2]	335399	1			T3	1		T4	1		T9	116
auto[0]	auto[3]	auto[3]	67072	1			T9	11		T11	524		T14	6
auto[1]	auto[0]	auto[0]	7934	1			T9	1		T22	1		T93	643
auto[1]	auto[0]	auto[1]	33716	1			T93	2896		T126	2		T130	1
auto[1]	auto[0]	auto[2]	33940	1			T58	1		T93	2953		T126	3
auto[1]	auto[0]	auto[3]	151564	1			T11	1		T93	13015		T76	3
auto[1]	auto[1]	auto[0]	3758835	1			T1	92907		T10	41639		T12	110362
auto[1]	auto[1]	auto[1]	679844	1			T1	9461		T10	3655		T12	11246
auto[1]	auto[1]	auto[2]	666405	1			T1	9185		T10	4128		T12	11059
auto[1]	auto[1]	auto[3]	1504096	1			T1	909		T10	373		T12	1104
auto[1]	auto[2]	auto[0]	6200	1			T31	1		T22	3		T56	1
auto[1]	auto[2]	auto[1]	26695	1			T27	1		T93	2707		T126	4
auto[1]	auto[2]	auto[2]	30324	1			T31	1		T93	1944		T126	3
auto[1]	auto[2]	auto[3]	134170	1			T93	8709		T94	8823		T131	1
auto[1]	auto[3]	auto[0]	3760053	1			T1	93256		T10	41934		T12	110195
auto[1]	auto[3]	auto[1]	659713	1			T1	9347		T10	4102		T12	11240
auto[1]	auto[3]	auto[2]	677041	1			T1	9409		T10	3784		T12	11193
auto[1]	auto[3]	auto[3]	1489886	1			T1	966		T10	374		T12	1117