Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.25	100.00	81.82	100.00		100.00	44.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	330434922	215233	0	0
ctrl_regwen_rd_A	330434922	3211	0	0
exec_rd_A	330434922	3162	0	0
exec_regwen_rd_A	330434922	3423	0	0
readback_rd_A	330434922	2367	0	0
readback_regwen_rd_A	330434922	1935	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	215233	0	0
T3	172644	3386	0	0
T4	86045	3257	0	0
T9	156998	0	0	0
T10	148008	0	0	0
T11	57008	0	0	0
T12	377081	0	0	0
T13	22449	0	0	0
T14	550785	0	0	0
T15	0	3130	0	0
T27	101631	0	0	0
T32	0	2123	0	0
T38	0	4547	0	0
T42	0	5272	0	0
T43	0	2474	0	0
T45	0	4233	0	0
T53	707639	0	0	0
T54	0	2426	0	0
T55	0	6222	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	3211	0	0
T32	0	221	0	0
T35	0	191	0	0
T45	0	181	0	0
T54	125105	62	0	0
T98	0	132	0	0
T99	0	80	0	0
T100	0	121	0	0
T101	0	165	0	0
T102	0	502	0	0
T103	0	556	0	0
T104	498282	0	0	0
T105	119378	0	0	0
T106	177708	0	0	0
T107	1576	0	0	0
T108	193144	0	0	0
T109	92213	0	0	0
T110	12462	0	0	0
T111	102184	0	0	0
T112	11284	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	3162	0	0
T32	0	177	0	0
T35	0	246	0	0
T45	0	209	0	0
T54	125105	55	0	0
T98	0	146	0	0
T99	0	72	0	0
T100	0	125	0	0
T101	0	153	0	0
T102	0	494	0	0
T103	0	539	0	0
T104	498282	0	0	0
T105	119378	0	0	0
T106	177708	0	0	0
T107	1576	0	0	0
T108	193144	0	0	0
T109	92213	0	0	0
T110	12462	0	0	0
T111	102184	0	0	0
T112	11284	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	3423	0	0
T32	0	257	0	0
T35	0	290	0	0
T45	0	167	0	0
T54	125105	80	0	0
T98	0	151	0	0
T99	0	101	0	0
T100	0	125	0	0
T101	0	154	0	0
T102	0	529	0	0
T103	0	589	0	0
T104	498282	0	0	0
T105	119378	0	0	0
T106	177708	0	0	0
T107	1576	0	0	0
T108	193144	0	0	0
T109	92213	0	0	0
T110	12462	0	0	0
T111	102184	0	0	0
T112	11284	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	2367	0	0
T32	0	175	0	0
T35	0	228	0	0
T45	0	170	0	0
T54	125105	93	0	0
T98	0	67	0	0
T99	0	54	0	0
T100	0	117	0	0
T101	0	192	0	0
T102	0	578	0	0
T103	0	509	0	0
T104	498282	0	0	0
T105	119378	0	0	0
T106	177708	0	0	0
T107	1576	0	0	0
T108	193144	0	0	0
T109	92213	0	0	0
T110	12462	0	0	0
T111	102184	0	0	0
T112	11284	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330434922	1935	0	0
T32	0	169	0	0
T35	0	178	0	0
T45	0	116	0	0
T54	125105	47	0	0
T98	0	87	0	0
T99	0	71	0	0
T100	0	90	0	0
T101	0	149	0	0
T102	0	469	0	0
T103	0	448	0	0
T104	498282	0	0	0
T105	119378	0	0	0
T106	177708	0	0	0
T107	1576	0	0	0
T108	193144	0	0	0
T109	92213	0	0	0
T110	12462	0	0	0
T111	102184	0	0	0
T112	11284	0	0	0