Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13788644	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59486696

1

T1

179508

T2

435134

T3

3071

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36537863	1			T1	98925		T2	239199		T3	1024
values[0x0]	16989678	1			T1	47283		T2	115547		T3	1041
values[0x1]	19747799	1			T1	51213		T2	123683		T3	1006

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6873366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66401974

1

T1

188535

T2

456987

T3

3071

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	243124	1			T1	710		T2	1877		T5	851
valid_sources[0x01]	278814	1			T1	788		T2	1863		T5	890
valid_sources[0x02]	247864	1			T1	700		T2	1895		T5	927
valid_sources[0x03]	261276	1			T1	751		T2	1887		T5	954
valid_sources[0x04]	276406	1			T1	748		T2	1880		T5	849
valid_sources[0x05]	309023	1			T1	776		T2	1900		T5	853
valid_sources[0x06]	243232	1			T1	778		T2	1826		T5	815
valid_sources[0x07]	292771	1			T1	784		T2	1845		T5	881
valid_sources[0x08]	286369	1			T1	761		T2	1844		T5	921
valid_sources[0x09]	295420	1			T1	787		T2	1881		T5	817
valid_sources[0x0a]	379779	1			T1	782		T2	1947		T5	860
valid_sources[0x0b]	264431	1			T1	808		T2	1894		T5	866
valid_sources[0x0c]	241327	1			T1	758		T2	1851		T5	915
valid_sources[0x0d]	271273	1			T1	740		T2	1869		T5	841
valid_sources[0x0e]	321654	1			T1	763		T2	1911		T5	935
valid_sources[0x0f]	258749	1			T1	774		T2	1928		T5	864
valid_sources[0x10]	283324	1			T1	761		T2	1889		T5	750
valid_sources[0x11]	297570	1			T1	788		T2	1900		T5	870
valid_sources[0x12]	269364	1			T1	804		T2	1964		T5	836
valid_sources[0x13]	261757	1			T1	795		T2	1888		T5	900
valid_sources[0x14]	303440	1			T1	741		T2	1865		T5	824
valid_sources[0x15]	301142	1			T1	813		T2	1835		T5	791
valid_sources[0x16]	317153	1			T1	776		T2	1816		T5	864
valid_sources[0x17]	288784	1			T1	780		T2	1912		T5	843
valid_sources[0x18]	375301	1			T1	745		T2	1961		T5	878
valid_sources[0x19]	301702	1			T1	770		T2	1913		T5	860
valid_sources[0x1a]	313015	1			T1	747		T2	1852		T5	850
valid_sources[0x1b]	258880	1			T1	765		T2	1897		T5	848
valid_sources[0x1c]	285586	1			T1	744		T2	1886		T5	880
valid_sources[0x1d]	253754	1			T1	774		T2	1865		T5	885
valid_sources[0x1e]	295127	1			T1	744		T2	1844		T5	890
valid_sources[0x1f]	261028	1			T1	761		T2	1835		T5	898
valid_sources[0x20]	310767	1			T1	775		T2	1800		T5	983
valid_sources[0x21]	280587	1			T1	775		T2	1806		T5	803
valid_sources[0x22]	258831	1			T1	807		T2	1872		T5	873
valid_sources[0x23]	302717	1			T1	797		T2	1875		T5	887
valid_sources[0x24]	287407	1			T1	785		T2	1871		T5	835
valid_sources[0x25]	288164	1			T1	777		T2	1921		T5	829
valid_sources[0x26]	271876	1			T1	759		T2	1914		T5	886
valid_sources[0x27]	277474	1			T1	802		T2	1879		T5	889
valid_sources[0x28]	276612	1			T1	745		T2	1840		T5	815
valid_sources[0x29]	326950	1			T1	768		T2	1844		T5	844
valid_sources[0x2a]	293519	1			T1	755		T2	1993		T5	898
valid_sources[0x2b]	236258	1			T1	835		T2	1832		T5	923
valid_sources[0x2c]	283500	1			T1	735		T2	1914		T5	827
valid_sources[0x2d]	288097	1			T1	762		T2	1830		T5	814
valid_sources[0x2e]	296991	1			T1	747		T2	1865		T5	852
valid_sources[0x2f]	347880	1			T1	802		T2	1908		T5	864
valid_sources[0x30]	295319	1			T1	754		T2	1814		T5	890
valid_sources[0x31]	290502	1			T1	768		T2	1896		T5	929
valid_sources[0x32]	296441	1			T1	792		T2	1927		T5	929
valid_sources[0x33]	368459	1			T1	763		T2	1856		T5	850
valid_sources[0x34]	236428	1			T1	802		T2	1900		T5	880
valid_sources[0x35]	283938	1			T1	736		T2	1922		T5	809
valid_sources[0x36]	314498	1			T1	804		T2	1883		T5	911
valid_sources[0x37]	289816	1			T1	737		T2	1908		T5	816
valid_sources[0x38]	339410	1			T1	753		T2	1911		T5	829
valid_sources[0x39]	241051	1			T1	755		T2	1891		T5	839
valid_sources[0x3a]	328375	1			T1	711		T2	1918		T5	873
valid_sources[0x3b]	256649	1			T1	769		T2	1853		T5	844
valid_sources[0x3c]	276781	1			T1	782		T2	1780		T5	870
valid_sources[0x3d]	267117	1			T1	779		T2	1883		T5	772
valid_sources[0x3e]	346734	1			T1	735		T2	1890		T5	841
valid_sources[0x3f]	293587	1			T1	740		T2	1857		T5	854
valid_sources[0x40]	249490	1			T1	775		T2	1879		T5	866
valid_sources[0x41]	269152	1			T1	816		T2	1817		T5	848
valid_sources[0x42]	333520	1			T1	761		T2	1838		T5	817
valid_sources[0x43]	282893	1			T1	750		T2	1781		T5	853
valid_sources[0x44]	295755	1			T1	771		T2	1819		T5	909
valid_sources[0x45]	289562	1			T1	762		T2	1901		T5	845
valid_sources[0x46]	317340	1			T1	813		T2	1803		T5	855
valid_sources[0x47]	314330	1			T1	764		T2	1816		T5	825
valid_sources[0x48]	325651	1			T1	784		T2	1864		T5	842
valid_sources[0x49]	328219	1			T1	775		T2	1899		T5	825
valid_sources[0x4a]	308734	1			T1	781		T2	1893		T5	882
valid_sources[0x4b]	264139	1			T1	774		T2	1899		T5	891
valid_sources[0x4c]	290294	1			T1	765		T2	1822		T5	903
valid_sources[0x4d]	253264	1			T1	760		T2	1872		T5	831
valid_sources[0x4e]	301967	1			T1	786		T2	1824		T5	762
valid_sources[0x4f]	273783	1			T1	789		T2	1914		T5	914
valid_sources[0x50]	337411	1			T1	754		T2	1906		T5	918
valid_sources[0x51]	319306	1			T1	775		T2	1795		T5	888
valid_sources[0x52]	249516	1			T1	765		T2	1831		T5	897
valid_sources[0x53]	294526	1			T1	786		T2	1823		T5	853
valid_sources[0x54]	374672	1			T1	811		T2	1832		T5	945
valid_sources[0x55]	307665	1			T1	772		T2	1807		T5	871
valid_sources[0x56]	293338	1			T1	787		T2	1807		T5	885
valid_sources[0x57]	343712	1			T1	750		T2	1900		T5	901
valid_sources[0x58]	289094	1			T1	770		T2	1927		T5	883
valid_sources[0x59]	299769	1			T1	754		T2	1871		T5	942
valid_sources[0x5a]	269853	1			T1	794		T2	1863		T5	806
valid_sources[0x5b]	324811	1			T1	814		T2	1855		T5	935
valid_sources[0x5c]	278496	1			T1	759		T2	1872		T5	910
valid_sources[0x5d]	299484	1			T1	774		T2	1896		T5	840
valid_sources[0x5e]	293927	1			T1	776		T2	1857		T5	878
valid_sources[0x5f]	235243	1			T1	727		T2	1908		T5	847
valid_sources[0x60]	272207	1			T1	777		T2	1905		T5	782
valid_sources[0x61]	342934	1			T1	774		T2	1875		T5	933
valid_sources[0x62]	288843	1			T1	786		T2	1860		T5	765
valid_sources[0x63]	353135	1			T1	751		T2	1836		T5	783
valid_sources[0x64]	301362	1			T1	739		T2	1848		T5	814
valid_sources[0x65]	238344	1			T1	739		T2	1815		T5	866
valid_sources[0x66]	240672	1			T1	791		T2	1800		T5	881
valid_sources[0x67]	253213	1			T1	771		T2	1853		T5	889
valid_sources[0x68]	257040	1			T1	752		T2	1909		T5	808
valid_sources[0x69]	347109	1			T1	763		T2	1853		T5	838
valid_sources[0x6a]	332078	1			T1	741		T2	1773		T5	749
valid_sources[0x6b]	308117	1			T1	838		T2	1920		T5	826
valid_sources[0x6c]	267415	1			T1	778		T2	1978		T5	781
valid_sources[0x6d]	321940	1			T1	774		T2	1883		T5	813
valid_sources[0x6e]	261229	1			T1	782		T2	1806		T5	913
valid_sources[0x6f]	308993	1			T1	766		T2	1844		T5	812
valid_sources[0x70]	334277	1			T1	779		T2	1950		T5	846
valid_sources[0x71]	342759	1			T1	793		T2	1852		T5	805
valid_sources[0x72]	314677	1			T1	741		T2	1826		T5	945
valid_sources[0x73]	276381	1			T1	769		T2	1956		T5	846
valid_sources[0x74]	253048	1			T1	797		T2	1895		T5	772
valid_sources[0x75]	287696	1			T1	773		T2	1860		T5	909
valid_sources[0x76]	322185	1			T1	784		T2	1850		T5	948
valid_sources[0x77]	274619	1			T1	799		T2	1952		T5	917
valid_sources[0x78]	310940	1			T1	775		T2	1834		T5	818
valid_sources[0x79]	277925	1			T1	807		T2	1859		T5	885
valid_sources[0x7a]	302273	1			T1	797		T2	1890		T5	932
valid_sources[0x7b]	243394	1			T1	724		T2	1845		T5	877
valid_sources[0x7c]	249749	1			T1	843		T2	1845		T5	865
valid_sources[0x7d]	239256	1			T1	775		T2	1904		T5	793
valid_sources[0x7e]	295609	1			T1	764		T2	1867		T5	891
valid_sources[0x7f]	326568	1			T1	821		T2	1873		T5	892
valid_sources[0x80]	246087	1			T1	765		T2	1887		T5	835

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29647822

1

T1

89921

T2

217676

T3

1024

values[0x0]

all_enables

biggest_size

14919367

1

T1

44626

T2

109034

T3

1041

values[0x1]

all_enables

biggest_size

14919507

1

T1

44961

T2

108424

T3

1006

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116702

1

T1

6

T2

48

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44479	1			T2	26		T12	651		T6	11
values[0x0]	51499	1			T1	11		T2	64		T3	1
values[0x1]	55455	1			T1	11		T2	53		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

124893

1

T1

11

T2

57

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	511	1			T12	8		T16	23		T21	12
valid_sources[0x01]	551	1			T3	1		T12	7		T15	4
valid_sources[0x02]	337	1			T12	8		T16	10		T21	5
valid_sources[0x03]	671	1			T2	1		T12	11		T16	6
valid_sources[0x04]	783	1			T12	9		T16	8		T26	1
valid_sources[0x05]	682	1			T12	7		T16	37		T21	4
valid_sources[0x06]	468	1			T2	2		T12	7		T16	34
valid_sources[0x07]	480	1			T2	3		T12	4		T16	11
valid_sources[0x08]	543	1			T12	12		T16	12		T21	9
valid_sources[0x09]	862	1			T2	3		T12	8		T16	10
valid_sources[0x0a]	465	1			T9	1		T12	15		T15	19
valid_sources[0x0b]	363	1			T2	2		T12	10		T22	1
valid_sources[0x0c]	572	1			T12	10		T16	22		T21	9
valid_sources[0x0d]	374	1			T12	17		T15	1		T16	16
valid_sources[0x0e]	653	1			T2	2		T12	13		T16	14
valid_sources[0x0f]	467	1			T2	1		T12	4		T16	13
valid_sources[0x10]	439	1			T12	8		T16	13		T21	11
valid_sources[0x11]	624	1			T12	5		T16	4		T21	10
valid_sources[0x12]	638	1			T12	12		T16	26		T21	13
valid_sources[0x13]	543	1			T2	1		T12	5		T16	41
valid_sources[0x14]	567	1			T12	9		T16	33		T21	10
valid_sources[0x15]	684	1			T12	15		T16	13		T21	8
valid_sources[0x16]	672	1			T2	1		T12	11		T16	6
valid_sources[0x17]	850	1			T12	15		T16	22		T21	10
valid_sources[0x18]	403	1			T2	1		T12	5		T16	14
valid_sources[0x19]	432	1			T2	1		T10	1		T12	6
valid_sources[0x1a]	583	1			T12	8		T16	26		T21	15
valid_sources[0x1b]	552	1			T12	7		T16	34		T21	12
valid_sources[0x1c]	737	1			T12	8		T16	22		T21	9
valid_sources[0x1d]	388	1			T12	4		T22	1		T16	10
valid_sources[0x1e]	466	1			T12	4		T16	4		T21	9
valid_sources[0x1f]	377	1			T2	1		T12	7		T16	30
valid_sources[0x20]	436	1			T2	1		T12	10		T16	8
valid_sources[0x21]	466	1			T12	4		T16	21		T21	14
valid_sources[0x22]	692	1			T12	15		T22	1		T16	15
valid_sources[0x23]	484	1			T12	6		T16	9		T21	7
valid_sources[0x24]	483	1			T2	1		T12	24		T22	1
valid_sources[0x25]	581	1			T12	8		T16	11		T21	10
valid_sources[0x26]	441	1			T11	3		T12	5		T16	1
valid_sources[0x27]	722	1			T2	1		T12	3		T16	6
valid_sources[0x28]	613	1			T12	8		T16	29		T21	9
valid_sources[0x29]	600	1			T2	2		T12	15		T22	1
valid_sources[0x2a]	560	1			T2	1		T10	1		T12	11
valid_sources[0x2b]	1069	1			T2	1		T12	2		T16	15
valid_sources[0x2c]	519	1			T2	1		T12	4		T16	18
valid_sources[0x2d]	808	1			T12	10		T16	10		T21	10
valid_sources[0x2e]	647	1			T12	17		T16	4		T21	8
valid_sources[0x2f]	390	1			T2	1		T12	2		T16	4
valid_sources[0x30]	1080	1			T10	2		T12	16		T16	11
valid_sources[0x31]	467	1			T2	1		T11	7		T12	7
valid_sources[0x32]	467	1			T12	10		T16	10		T21	6
valid_sources[0x33]	616	1			T2	1		T12	8		T16	25
valid_sources[0x34]	732	1			T2	1		T12	10		T16	4
valid_sources[0x35]	833	1			T12	8		T16	23		T21	4
valid_sources[0x36]	403	1			T2	2		T12	12		T16	20
valid_sources[0x37]	528	1			T12	7		T16	9		T21	11
valid_sources[0x38]	628	1			T2	1		T8	1		T9	1
valid_sources[0x39]	920	1			T2	2		T12	7		T16	28
valid_sources[0x3a]	397	1			T12	14		T16	17		T21	6
valid_sources[0x3b]	516	1			T2	1		T10	1		T12	5
valid_sources[0x3c]	743	1			T12	10		T16	28		T21	8
valid_sources[0x3d]	419	1			T12	4		T16	13		T21	8
valid_sources[0x3e]	442	1			T12	10		T16	35		T21	17
valid_sources[0x3f]	705	1			T12	16		T22	1		T16	10
valid_sources[0x40]	448	1			T12	8		T16	10		T21	11
valid_sources[0x41]	552	1			T12	12		T16	36		T21	5
valid_sources[0x42]	679	1			T2	3		T12	5		T16	14
valid_sources[0x43]	749	1			T12	5		T16	8		T45	2
valid_sources[0x44]	623	1			T2	1		T10	1		T12	3
valid_sources[0x45]	431	1			T12	15		T16	12		T47	1
valid_sources[0x46]	429	1			T12	3		T16	41		T21	10
valid_sources[0x47]	705	1			T12	13		T15	7		T16	24
valid_sources[0x48]	901	1			T12	4		T15	2		T16	20
valid_sources[0x49]	519	1			T2	3		T12	7		T16	6
valid_sources[0x4a]	614	1			T12	14		T16	9		T21	10
valid_sources[0x4b]	549	1			T2	3		T12	6		T16	7
valid_sources[0x4c]	700	1			T12	8		T16	25		T21	10
valid_sources[0x4d]	476	1			T2	1		T12	10		T16	6
valid_sources[0x4e]	489	1			T2	1		T3	1		T12	3
valid_sources[0x4f]	620	1			T12	9		T22	1		T16	28
valid_sources[0x50]	418	1			T2	1		T12	12		T22	1
valid_sources[0x51]	553	1			T2	1		T12	13		T16	3
valid_sources[0x52]	632	1			T2	2		T12	8		T22	1
valid_sources[0x53]	624	1			T2	1		T11	12		T12	7
valid_sources[0x54]	653	1			T12	9		T16	4		T21	10
valid_sources[0x55]	705	1			T12	12		T16	20		T21	13
valid_sources[0x56]	385	1			T2	1		T12	8		T16	12
valid_sources[0x57]	740	1			T12	12		T16	8		T21	5
valid_sources[0x58]	642	1			T2	1		T12	9		T16	18
valid_sources[0x59]	603	1			T2	1		T12	4		T16	6
valid_sources[0x5a]	647	1			T12	14		T22	1		T16	9
valid_sources[0x5b]	464	1			T2	1		T12	10		T22	1
valid_sources[0x5c]	869	1			T12	10		T16	19		T21	12
valid_sources[0x5d]	419	1			T12	10		T16	10		T21	7
valid_sources[0x5e]	880	1			T12	12		T16	7		T21	7
valid_sources[0x5f]	717	1			T2	3		T12	4		T22	1
valid_sources[0x60]	573	1			T2	1		T12	7		T16	21
valid_sources[0x61]	786	1			T12	11		T16	11		T21	7
valid_sources[0x62]	531	1			T3	2		T12	9		T16	6
valid_sources[0x63]	435	1			T2	1		T12	7		T16	2
valid_sources[0x64]	364	1			T12	18		T22	1		T16	18
valid_sources[0x65]	643	1			T12	9		T16	17		T21	18
valid_sources[0x66]	660	1			T2	1		T12	17		T16	18
valid_sources[0x67]	489	1			T12	10		T16	12		T21	13
valid_sources[0x68]	794	1			T12	4		T6	4		T22	1
valid_sources[0x69]	493	1			T12	8		T16	16		T21	10
valid_sources[0x6a]	606	1			T12	9		T16	13		T21	9
valid_sources[0x6b]	369	1			T12	8		T16	15		T21	8
valid_sources[0x6c]	691	1			T11	2		T12	12		T16	11
valid_sources[0x6d]	400	1			T2	1		T12	6		T16	6
valid_sources[0x6e]	805	1			T2	3		T12	12		T22	1
valid_sources[0x6f]	567	1			T11	2		T12	7		T16	7
valid_sources[0x70]	595	1			T12	3		T6	1		T16	20
valid_sources[0x71]	596	1			T11	3		T12	14		T16	17
valid_sources[0x72]	583	1			T2	1		T12	12		T16	13
valid_sources[0x73]	446	1			T4	4		T12	3		T16	6
valid_sources[0x74]	492	1			T2	2		T12	10		T15	3
valid_sources[0x75]	675	1			T2	2		T12	13		T16	11
valid_sources[0x76]	672	1			T12	9		T16	17		T21	7
valid_sources[0x77]	642	1			T12	10		T16	29		T21	12
valid_sources[0x78]	887	1			T5	35		T12	16		T16	17
valid_sources[0x79]	639	1			T12	6		T16	6		T21	11
valid_sources[0x7a]	854	1			T12	5		T16	11		T21	12
valid_sources[0x7b]	760	1			T12	5		T16	14		T21	16
valid_sources[0x7c]	562	1			T12	17		T16	13		T21	12
valid_sources[0x7d]	461	1			T8	4		T12	12		T16	45
valid_sources[0x7e]	425	1			T2	1		T12	20		T16	10
valid_sources[0x7f]	574	1			T12	4		T16	11		T21	7
valid_sources[0x80]	599	1			T2	2		T12	6		T16	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

32667

1

T2

16

T12

592

T6

5

values[0x0]

all_enables

biggest_size

43119

1

T1

4

T2

25

T8

1

values[0x1]

all_enables

biggest_size

40916

1

T1

2

T2

7

T3

1