Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13432701

1

T1

14438

T2

38177

T5

19943

full_word

54278173

1

T1

143631

T2

384644

T3

3071

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	67710604	1			T1	158069		T2	422821		T3	3071
auto[TlIntgErrCmd]	87	1			T49	6		T50	3		T51	3
auto[TlIntgErrData]	86	1			T49	6		T50	3		T51	9
auto[TlIntgErrBoth]	97	1			T49	8		T50	4		T51	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30928287

1

T1

59573

T2

184523

T3

1024

auto[1]

36782587

1

T1

98496

T2

238298

T3

2047

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6409740	1			T1	5529		T2	16477		T5	10124
auto[TlIntgErrNone]	partial	auto[1]	7022717	1			T1	8909		T2	21700		T5	9819
auto[TlIntgErrNone]	full_word	auto[0]	24518421	1			T1	54044		T2	168046		T3	1024
auto[TlIntgErrNone]	full_word	auto[1]	29759726	1			T1	89587		T2	216598		T3	2047
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T49	5		T50	3		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T49	1		T126	3		T121	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T51	1		T127	2		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T51	1		T132	1		T128	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T49	3		T50	2		T51	2
auto[TlIntgErrData]	partial	auto[1]	37	1			T49	2		T50	1		T51	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T49	1		T51	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T51	2		T133	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T49	1		T51	4		T126	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T49	6		T50	3		T51	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T50	1		T130	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T49	1		T133	1		T124	1